include/configs/uc100.h

   1 /*
   2  * (C) Copyright 2000-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC860           1
  37 #define CONFIG_MPC860T          1
  38 #define CONFIG_MPC862           1       /* enable 862 since the         */
  39 #define CONFIG_MPC857           1       /* 857 is a variant of the 862  */
  40
  41 #define CONFIG_UC100            1       /* ...on a UC100 module         */
  42
  43 #define CONFIG_SYS_TEXT_BASE    0x40700000
  44
  45 #define MPC8XX_FACT             4               /* Multiply by 4        */
  46 #define MPC8XX_XIN              25000000        /* 25.0 MHz in          */
  47 #define CONFIG_8xx_GCLK_FREQ    (MPC8XX_FACT * MPC8XX_XIN)
  48                                     /* define if cant' use get_gclk_freq */
  49
  50 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  51 #undef  CONFIG_8xx_CONS_SMC2
  52 #undef  CONFIG_8xx_CONS_NONE
  53
  54 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  55
  56 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  57
  58 #define CONFIG_BOOTCOUNT_LIMIT
  59
  60 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  61
  62 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  63
  64 #define CONFIG_PREBOOT  "echo;" \
  65         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  66         "echo"
  67
  68 #undef  CONFIG_BOOTARGS
  69
  70 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  71         "netdev=eth0\0"                                                 \
  72         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  73                 "nfsroot=${serverip}:${rootpath}\0"                     \
  74         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  75         "addip=setenv bootargs ${bootargs} "                            \
  76                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  77                 ":${hostname}:${netdev}:off panic=1\0"                  \
  78         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
  79         "flash_nfs=run nfsargs addip addtty;"                           \
  80                 "bootm ${kernel_addr}\0"                                \
  81         "flash_self=run ramargs addip addtty;"                          \
  82                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  83         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
  84                 "bootm\0"                                               \
  85         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
  86         "bootfile=/tftpboot/uc100/uImage\0"                             \
  87         "kernel_addr=40000000\0"                                        \
  88         "ramdisk_addr=40100000\0"                                       \
  89         "load=tftp 100000 /tftpboot/uc100/u-boot.bin\0"                 \
  90         "update=protect off 40700000 4073ffff;era 40700000 4073ffff;"   \
  91                 "cp.b 100000 40700000 ${filesize};"                     \
  92                 "setenv filesize;saveenv\0"                             \
  93         ""
  94 #define CONFIG_BOOTCOMMAND      "run flash_self"
  95
  96 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  97 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  98
  99 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 100
 101 #undef CONFIG_STATUS_LED                /* no status-led                */
 102
 103 /*
 104  * BOOTP options
 105  */
 106 #define CONFIG_BOOTP_SUBNETMASK
 107 #define CONFIG_BOOTP_GATEWAY
 108 #define CONFIG_BOOTP_HOSTNAME
 109 #define CONFIG_BOOTP_BOOTPATH
 110 #define CONFIG_BOOTP_BOOTFILESIZE
 111
 112
 113 #define CONFIG_MAC_PARTITION
 114 #define CONFIG_DOS_PARTITION
 115
 116 #undef CONFIG_RTC_MPC8xx
 117 #define CONFIG_SYS_I2C_RTC_ADDR 0x51    /* PCF8563 RTC                  */
 118 #define CONFIG_RTC_PCF8563              /* use Philips PCF8563 RTC      */
 119
 120 /*
 121  * Power On Self Test support
 122  */
 123 #define CONFIG_POST           ( CONFIG_SYS_POST_CACHE           | \
 124                                 CONFIG_SYS_POST_MEMORY          | \
 125                                 CONFIG_SYS_POST_CPU             | \
 126                                 CONFIG_SYS_POST_UART            | \
 127                                 CONFIG_SYS_POST_SPR )
 128 #undef  CONFIG_POST
 129
 130
 131 /*
 132  * Command line configuration.
 133  */
 134 #include <config_cmd_default.h>
 135
 136 #define CONFIG_CMD_ASKENV
 137 #define CONFIG_CMD_DATE
 138 #define CONFIG_CMD_DHCP
 139 #define CONFIG_CMD_EEPROM
 140 #define CONFIG_CMD_ELF
 141 #define CONFIG_CMD_FAT
 142 #define CONFIG_CMD_I2C
 143 #define CONFIG_CMD_IDE
 144 #define CONFIG_CMD_MII
 145 #define CONFIG_CMD_NFS
 146 #define CONFIG_CMD_PING
 147 #define CONFIG_CMD_SNTP
 148
 149 #ifdef CONFIG_POST
 150 #define CONFIG_CMD_DIAG
 151 #endif
 152
 153
 154 #define CONFIG_NETCONSOLE
 155
 156 /*
 157  * Miscellaneous configurable options
 158  */
 159 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 160 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt       */
 161
 162 #if 0
 163 #define CONFIG_SYS_HUSH_PARSER          1       /* use "hush" command parser    */
 164 #endif
 165
 166 #if defined(CONFIG_CMD_KGDB)
 167 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 168 #else
 169 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 170 #endif
 171 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 172 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 173 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 174
 175 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 176 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 177
 178 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 179
 180 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 181
 182 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
 183
 184 /*
 185  * Low Level Configuration Settings
 186  * (address mappings, register initial values, etc.)
 187  * You should know what you are doing if you make changes here.
 188  */
 189 /*-----------------------------------------------------------------------
 190  * Internal Memory Mapped Register
 191  */
 192 #define CONFIG_SYS_IMMR         0xF0000000
 193
 194 /*-----------------------------------------------------------------------
 195  * Definitions for initial stack pointer and data area (in DPRAM)
 196  */
 197 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 198 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 199 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 200 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 201
 202 /*-----------------------------------------------------------------------
 203  * Start addresses for the final memory configuration
 204  * (Set up by the startup code)
 205  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 206  */
 207 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 208 #define CONFIG_SYS_FLASH_BASE           0x40000000
 209 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 210 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE+0x00700000) /* resetvec fff00100*/
 211 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 212
 213 /*-----------------------------------------------------------------------
 214  * Address accessed to reset the board - must not be mapped/assigned
 215  */
 216 #define CONFIG_SYS_RESET_ADDRESS       0x90000000
 217
 218 /*
 219  * For booting Linux, the board info and command line data
 220  * have to be in the first 8 MB of memory, since this is
 221  * the maximum mapped by the Linux kernel during initialization.
 222  */
 223 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 224
 225 /*-----------------------------------------------------------------------
 226  * FLASH organization
 227  */
 228 #define CONFIG_SYS_FLASH_CFI                            /* The flash is CFI compatible  */
 229 #define CONFIG_FLASH_CFI_DRIVER                 /* Use common CFI driver        */
 230 #define CONFIG_SYS_FLASH_CFI_AMD_RESET  1               /* AMD RESET for STM 29W320DB!  */
 231
 232 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 233 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 234
 235 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 236 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 237
 238 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 239
 240 #define CONFIG_ENV_IS_IN_FLASH  1
 241 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
 242 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector          */
 243 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 244
 245 /* Address and size of Redundant Environment Sector     */
 246 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE)
 247 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 248
 249 /*-----------------------------------------------------------------------
 250  * Cache Configuration
 251  */
 252 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 253 #if defined(CONFIG_CMD_KGDB)
 254 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 255 #endif
 256
 257 /*-----------------------------------------------------------------------
 258  * SYPCR - System Protection Control                            11-9
 259  * SYPCR can only be written once after reset!
 260  *-----------------------------------------------------------------------
 261  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 262  */
 263 #if defined(CONFIG_WATCHDOG)
 264 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 265                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 266 #else
 267 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 268 #endif
 269
 270 /*-----------------------------------------------------------------------
 271  * SIUMCR - SIU Module Configuration                            11-6
 272  *-----------------------------------------------------------------------
 273  * PCMCIA config., multi-function pin tri-state
 274  */
 275 #define CONFIG_SYS_SIUMCR       (SIUMCR_FRC | SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 276
 277 /*-----------------------------------------------------------------------
 278  * TBSCR - Time Base Status and Control                         11-26
 279  *-----------------------------------------------------------------------
 280  * Clear Reference Interrupt Status, Timebase freezing enabled
 281  */
 282 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 283
 284 /*-----------------------------------------------------------------------
 285  * RTCSC - Real-Time Clock Status and Control Register          11-27
 286  *-----------------------------------------------------------------------
 287  */
 288 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 289
 290 /*-----------------------------------------------------------------------
 291  * PISCR - Periodic Interrupt Status and Control                11-31
 292  *-----------------------------------------------------------------------
 293  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 294  */
 295 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 296
 297 /*-----------------------------------------------------------------------
 298  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 299  *-----------------------------------------------------------------------
 300  * Reset PLL lock status sticky bit, timer expired status bit and timer
 301  * interrupt status bit
 302  */
 303 #define CONFIG_SYS_PLPRCR       (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
 304                                 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 305
 306 /*-----------------------------------------------------------------------
 307  * SCCR - System Clock and reset Control Register               15-27
 308  *-----------------------------------------------------------------------
 309  * Set clock output, timebase and RTC source and divider,
 310  * power management and some other internal clocks
 311  */
 312 #define SCCR_MASK       0x00000000
 313 #define CONFIG_SYS_SCCR        (SCCR_EBDF11)
 314
 315 /*-----------------------------------------------------------------------
 316  * PCMCIA stuff
 317  *-----------------------------------------------------------------------
 318  *
 319  */
 320 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 321 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 322 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 323 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 324 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 325 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 326 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 327 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 328
 329 /*-----------------------------------------------------------------------
 330  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 331  *-----------------------------------------------------------------------
 332  */
 333
 334 #define CONFIG_IDE_PREINIT      1       /* Use preinit IDE hook */
 335 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 336
 337 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 338 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 339 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 340
 341 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 342 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 343
 344 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 345
 346 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 347
 348 /* Offset for data I/O                  */
 349 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 350
 351 /* Offset for normal register accesses  */
 352 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 353
 354 /* Offset for alternate registers       */
 355 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 356
 357 /*-----------------------------------------------------------------------
 358  *
 359  *-----------------------------------------------------------------------
 360  *
 361  */
 362 #define CONFIG_SYS_DER  0
 363
 364 /*
 365  * Init Memory Controller:
 366  *
 367  * BR0/1 and OR0/1 (FLASH)
 368  */
 369
 370 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 371 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 372
 373 /* used to re-map FLASH both when starting from SRAM or FLASH:
 374  * restrict access enough to keep SRAM working (if any)
 375  * but not too much to meddle with FLASH accesses
 376  */
 377 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 378 #define CONFIG_SYS_PRELIM_OR_AM 0xFF800000      /* OR addr mask */
 379
 380 /*
 381  * FLASH timing:
 382  */
 383 #define CONFIG_SYS_OR_TIMING_FLASH      (0x00000d24)
 384
 385 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 386 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 387 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 388
 389 #define CONFIG_SYS_BR1_PRELIM  0x00000081  /* Chip select for SDRAM (32 Bit, UPMA) */
 390 #define CONFIG_SYS_OR1_PRELIM  0xfc000a00
 391 #define CONFIG_SYS_BR2_PRELIM  0x80000001  /* Chip select for SRAM (32 Bit, GPCM) */
 392 #define CONFIG_SYS_OR2_PRELIM  0xfff00d24
 393 #define CONFIG_SYS_BR3_PRELIM  0x80600401  /* Chip select for Display (8 Bit, GPCM) */
 394 #define CONFIG_SYS_OR3_PRELIM  0xffff8f44
 395 #define CONFIG_SYS_BR4_PRELIM  0xc05108c1  /* Chip select for Interbus MPM (16 Bit, UPMB) */
 396 #define CONFIG_SYS_OR4_PRELIM  0xffff0300
 397 #define CONFIG_SYS_BR5_PRELIM  0xc0500401  /* Chip select for Interbus Status (8 Bit, GPCM) */
 398 #define CONFIG_SYS_OR5_PRELIM  0xffff8db0
 399
 400 /*
 401  * Memory Periodic Timer Prescaler
 402  *
 403  * The Divider for PTA (refresh timer) configuration is based on an
 404  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 405  * the number of chip selects (NCS) and the actually needed refresh
 406  * rate is done by setting MPTPR.
 407  *
 408  * PTA is calculated from
 409  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 410  *
 411  *      gclk      CPU clock (not bus clock!)
 412  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 413  *
 414  * 4096  Rows from SDRAM example configuration
 415  * 1000  factor s -> ms
 416  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 417  *    4  Number of refresh cycles per period
 418  *   64  Refresh cycle in ms per number of rows
 419  * --------------------------------------------
 420  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 421  *
 422  *  50 MHz =>  50.000.000 / Divider =  98
 423  *  66 Mhz =>  66.000.000 / Divider = 129
 424  *  80 Mhz =>  80.000.000 / Divider = 156
 425  * 100 Mhz => 100.000.000 / Divider = 195
 426  */
 427
 428 #define CONFIG_SYS_PTA_PER_CLK  ((4096 * 32 * 1000) / (4 * 64))
 429 #define CONFIG_SYS_MAMR_PTA     98
 430
 431 /*
 432  * For 16 MBit, refresh rates could be 31.3 us
 433  * (= 64 ms / 2K = 125 / quad bursts).
 434  * For a simpler initialization, 15.6 us is used instead.
 435  *
 436  * #define CONFIG_SYS_MPTPR_2BK_2K      MPTPR_PTP_DIV32         for 2 banks
 437  * #define CONFIG_SYS_MPTPR_1BK_2K      MPTPR_PTP_DIV64         for 1 bank
 438  */
 439 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 440 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 441
 442 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 443 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 444 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 445
 446 /*
 447  * MAMR settings for SDRAM
 448  */
 449
 450 /* 8 column SDRAM */
 451 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 452                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 453                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 454 /* 9 column SDRAM */
 455 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 456                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 457                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 458
 459 #define CONFIG_SYS_MAMR_VAL     0x30904114      /* for SDRAM */
 460 #define CONFIG_SYS_MBMR_VAL     0xff001111      /* for Interbus-MPM */
 461
 462 /*-----------------------------------------------------------------------
 463  * I2C stuff
 464  */
 465
 466 /* enable I2C and select the hardware/software driver */
 467 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 468 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
 469
 470 #define CONFIG_SYS_I2C_SPEED            93000   /* 93 kHz is supposed to work   */
 471 #define CONFIG_SYS_I2C_SLAVE            0xFE
 472
 473 #ifdef CONFIG_SOFT_I2C
 474 /*
 475  * Software (bit-bang) I2C driver configuration
 476  */
 477 #define PB_SCL          0x00000020      /* PB 26 */
 478 #define PB_SDA          0x00000010      /* PB 27 */
 479
 480 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 481 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 482 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 483 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 484 #define I2C_SDA(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 485                         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 486 #define I2C_SCL(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 487                         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 488 #define I2C_DELAY       udelay(2)       /* 1/4 I2C clock duration */
 489 #endif  /* CONFIG_SOFT_I2C */
 490
 491 /*-----------------------------------------------------------------------
 492  * I2C EEPROM (24C164)
 493  */
 494 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x58    /* EEPROM AT24C164              */
 495 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 496 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* takes up to 10 msec  */
 497 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 498
 499 #define CONFIG_FEC_ENET         1       /* use FEC ethernet  */
 500 #define FEC_ENET
 501 #define CONFIG_MII
 502 #define CONFIG_MII_INIT         1
 503 #define CONFIG_SYS_DISCOVER_PHY 1
 504
 505 #endif  /* __CONFIG_H */