include/configs/uc100.h

   1 /*
   2  * (C) Copyright 2000-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_MPC860           1
  21 #define CONFIG_MPC860T          1
  22 #define CONFIG_MPC862           1       /* enable 862 since the         */
  23 #define CONFIG_MPC857           1       /* 857 is a variant of the 862  */
  24
  25 #define CONFIG_UC100            1       /* ...on a UC100 module         */
  26
  27 #define CONFIG_SYS_TEXT_BASE    0x40700000
  28
  29 #define MPC8XX_FACT             4               /* Multiply by 4        */
  30 #define MPC8XX_XIN              25000000        /* 25.0 MHz in          */
  31 #define CONFIG_8xx_GCLK_FREQ    (MPC8XX_FACT * MPC8XX_XIN)
  32                                     /* define if cant' use get_gclk_freq */
  33
  34 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  35 #undef  CONFIG_8xx_CONS_SMC2
  36 #undef  CONFIG_8xx_CONS_NONE
  37
  38 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  39
  40 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  41
  42 #define CONFIG_BOOTCOUNT_LIMIT
  43
  44 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  45
  46 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  47
  48 #define CONFIG_PREBOOT  "echo;" \
  49         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  50         "echo"
  51
  52 #undef  CONFIG_BOOTARGS
  53
  54 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  55         "netdev=eth0\0"                                                 \
  56         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  57                 "nfsroot=${serverip}:${rootpath}\0"                     \
  58         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  59         "addip=setenv bootargs ${bootargs} "                            \
  60                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  61                 ":${hostname}:${netdev}:off panic=1\0"                  \
  62         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
  63         "flash_nfs=run nfsargs addip addtty;"                           \
  64                 "bootm ${kernel_addr}\0"                                \
  65         "flash_self=run ramargs addip addtty;"                          \
  66                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  67         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
  68                 "bootm\0"                                               \
  69         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
  70         "bootfile=/tftpboot/uc100/uImage\0"                             \
  71         "kernel_addr=40000000\0"                                        \
  72         "ramdisk_addr=40100000\0"                                       \
  73         "load=tftp 100000 /tftpboot/uc100/u-boot.bin\0"                 \
  74         "update=protect off 40700000 4073ffff;era 40700000 4073ffff;"   \
  75                 "cp.b 100000 40700000 ${filesize};"                     \
  76                 "setenv filesize;saveenv\0"                             \
  77         ""
  78 #define CONFIG_BOOTCOMMAND      "run flash_self"
  79
  80 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  81 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  82
  83 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  84
  85 #undef CONFIG_STATUS_LED                /* no status-led                */
  86
  87 /*
  88  * BOOTP options
  89  */
  90 #define CONFIG_BOOTP_SUBNETMASK
  91 #define CONFIG_BOOTP_GATEWAY
  92 #define CONFIG_BOOTP_HOSTNAME
  93 #define CONFIG_BOOTP_BOOTPATH
  94 #define CONFIG_BOOTP_BOOTFILESIZE
  95
  96
  97 #define CONFIG_MAC_PARTITION
  98 #define CONFIG_DOS_PARTITION
  99
 100 #undef CONFIG_RTC_MPC8xx
 101 #define CONFIG_SYS_I2C_RTC_ADDR 0x51    /* PCF8563 RTC                  */
 102 #define CONFIG_RTC_PCF8563              /* use Philips PCF8563 RTC      */
 103
 104 /*
 105  * Power On Self Test support
 106  */
 107 #define CONFIG_POST           ( CONFIG_SYS_POST_CACHE           | \
 108                                 CONFIG_SYS_POST_MEMORY          | \
 109                                 CONFIG_SYS_POST_CPU             | \
 110                                 CONFIG_SYS_POST_UART            | \
 111                                 CONFIG_SYS_POST_SPR )
 112 #undef  CONFIG_POST
 113
 114
 115 /*
 116  * Command line configuration.
 117  */
 118 #include <config_cmd_default.h>
 119
 120 #define CONFIG_CMD_ASKENV
 121 #define CONFIG_CMD_DATE
 122 #define CONFIG_CMD_DHCP
 123 #define CONFIG_CMD_EEPROM
 124 #define CONFIG_CMD_ELF
 125 #define CONFIG_CMD_FAT
 126 #define CONFIG_CMD_I2C
 127 #define CONFIG_CMD_IDE
 128 #define CONFIG_CMD_MII
 129 #define CONFIG_CMD_NFS
 130 #define CONFIG_CMD_PING
 131 #define CONFIG_CMD_SNTP
 132
 133 #ifdef CONFIG_POST
 134 #define CONFIG_CMD_DIAG
 135 #endif
 136
 137
 138 #define CONFIG_NETCONSOLE
 139
 140 /*
 141  * Miscellaneous configurable options
 142  */
 143 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 144 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt       */
 145
 146 #if 0
 147 #define CONFIG_SYS_HUSH_PARSER          1       /* use "hush" command parser    */
 148 #endif
 149
 150 #if defined(CONFIG_CMD_KGDB)
 151 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 152 #else
 153 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 154 #endif
 155 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 156 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 157 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 158
 159 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 160 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 161
 162 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 163
 164 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 165
 166 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
 167
 168 /*
 169  * Low Level Configuration Settings
 170  * (address mappings, register initial values, etc.)
 171  * You should know what you are doing if you make changes here.
 172  */
 173 /*-----------------------------------------------------------------------
 174  * Internal Memory Mapped Register
 175  */
 176 #define CONFIG_SYS_IMMR         0xF0000000
 177
 178 /*-----------------------------------------------------------------------
 179  * Definitions for initial stack pointer and data area (in DPRAM)
 180  */
 181 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 182 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 183 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 184 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 185
 186 /*-----------------------------------------------------------------------
 187  * Start addresses for the final memory configuration
 188  * (Set up by the startup code)
 189  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 190  */
 191 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 192 #define CONFIG_SYS_FLASH_BASE           0x40000000
 193 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 194 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE+0x00700000) /* resetvec fff00100*/
 195 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 196
 197 /*-----------------------------------------------------------------------
 198  * Address accessed to reset the board - must not be mapped/assigned
 199  */
 200 #define CONFIG_SYS_RESET_ADDRESS       0x90000000
 201
 202 /*
 203  * For booting Linux, the board info and command line data
 204  * have to be in the first 8 MB of memory, since this is
 205  * the maximum mapped by the Linux kernel during initialization.
 206  */
 207 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 208
 209 /*-----------------------------------------------------------------------
 210  * FLASH organization
 211  */
 212 #define CONFIG_SYS_FLASH_CFI                            /* The flash is CFI compatible  */
 213 #define CONFIG_FLASH_CFI_DRIVER                 /* Use common CFI driver        */
 214 #define CONFIG_SYS_FLASH_CFI_AMD_RESET  1               /* AMD RESET for STM 29W320DB!  */
 215
 216 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 217 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 218
 219 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 220 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 221
 222 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 223
 224 #define CONFIG_ENV_IS_IN_FLASH  1
 225 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
 226 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector          */
 227 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 228
 229 /* Address and size of Redundant Environment Sector     */
 230 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE)
 231 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 232
 233 /*-----------------------------------------------------------------------
 234  * Cache Configuration
 235  */
 236 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 237 #if defined(CONFIG_CMD_KGDB)
 238 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 239 #endif
 240
 241 /*-----------------------------------------------------------------------
 242  * SYPCR - System Protection Control                            11-9
 243  * SYPCR can only be written once after reset!
 244  *-----------------------------------------------------------------------
 245  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 246  */
 247 #if defined(CONFIG_WATCHDOG)
 248 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 249                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 250 #else
 251 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 252 #endif
 253
 254 /*-----------------------------------------------------------------------
 255  * SIUMCR - SIU Module Configuration                            11-6
 256  *-----------------------------------------------------------------------
 257  * PCMCIA config., multi-function pin tri-state
 258  */
 259 #define CONFIG_SYS_SIUMCR       (SIUMCR_FRC | SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 260
 261 /*-----------------------------------------------------------------------
 262  * TBSCR - Time Base Status and Control                         11-26
 263  *-----------------------------------------------------------------------
 264  * Clear Reference Interrupt Status, Timebase freezing enabled
 265  */
 266 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 267
 268 /*-----------------------------------------------------------------------
 269  * RTCSC - Real-Time Clock Status and Control Register          11-27
 270  *-----------------------------------------------------------------------
 271  */
 272 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 273
 274 /*-----------------------------------------------------------------------
 275  * PISCR - Periodic Interrupt Status and Control                11-31
 276  *-----------------------------------------------------------------------
 277  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 278  */
 279 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 280
 281 /*-----------------------------------------------------------------------
 282  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 283  *-----------------------------------------------------------------------
 284  * Reset PLL lock status sticky bit, timer expired status bit and timer
 285  * interrupt status bit
 286  */
 287 #define CONFIG_SYS_PLPRCR       (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
 288                                 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 289
 290 /*-----------------------------------------------------------------------
 291  * SCCR - System Clock and reset Control Register               15-27
 292  *-----------------------------------------------------------------------
 293  * Set clock output, timebase and RTC source and divider,
 294  * power management and some other internal clocks
 295  */
 296 #define SCCR_MASK       0x00000000
 297 #define CONFIG_SYS_SCCR        (SCCR_EBDF11)
 298
 299 /*-----------------------------------------------------------------------
 300  * PCMCIA stuff
 301  *-----------------------------------------------------------------------
 302  *
 303  */
 304 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 305 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 306 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 307 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 308 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 309 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 310 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 311 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 312
 313 /*-----------------------------------------------------------------------
 314  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 315  *-----------------------------------------------------------------------
 316  */
 317
 318 #define CONFIG_IDE_PREINIT      1       /* Use preinit IDE hook */
 319 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 320
 321 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 322 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 323 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 324
 325 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 326 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 327
 328 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 329
 330 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 331
 332 /* Offset for data I/O                  */
 333 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 334
 335 /* Offset for normal register accesses  */
 336 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 337
 338 /* Offset for alternate registers       */
 339 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 340
 341 /*-----------------------------------------------------------------------
 342  *
 343  *-----------------------------------------------------------------------
 344  *
 345  */
 346 #define CONFIG_SYS_DER  0
 347
 348 /*
 349  * Init Memory Controller:
 350  *
 351  * BR0/1 and OR0/1 (FLASH)
 352  */
 353
 354 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 355 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 356
 357 /* used to re-map FLASH both when starting from SRAM or FLASH:
 358  * restrict access enough to keep SRAM working (if any)
 359  * but not too much to meddle with FLASH accesses
 360  */
 361 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 362 #define CONFIG_SYS_PRELIM_OR_AM 0xFF800000      /* OR addr mask */
 363
 364 /*
 365  * FLASH timing:
 366  */
 367 #define CONFIG_SYS_OR_TIMING_FLASH      (0x00000d24)
 368
 369 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 370 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 371 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 372
 373 #define CONFIG_SYS_BR1_PRELIM  0x00000081  /* Chip select for SDRAM (32 Bit, UPMA) */
 374 #define CONFIG_SYS_OR1_PRELIM  0xfc000a00
 375 #define CONFIG_SYS_BR2_PRELIM  0x80000001  /* Chip select for SRAM (32 Bit, GPCM) */
 376 #define CONFIG_SYS_OR2_PRELIM  0xfff00d24
 377 #define CONFIG_SYS_BR3_PRELIM  0x80600401  /* Chip select for Display (8 Bit, GPCM) */
 378 #define CONFIG_SYS_OR3_PRELIM  0xffff8f44
 379 #define CONFIG_SYS_BR4_PRELIM  0xc05108c1  /* Chip select for Interbus MPM (16 Bit, UPMB) */
 380 #define CONFIG_SYS_OR4_PRELIM  0xffff0300
 381 #define CONFIG_SYS_BR5_PRELIM  0xc0500401  /* Chip select for Interbus Status (8 Bit, GPCM) */
 382 #define CONFIG_SYS_OR5_PRELIM  0xffff8db0
 383
 384 /*
 385  * Memory Periodic Timer Prescaler
 386  *
 387  * The Divider for PTA (refresh timer) configuration is based on an
 388  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 389  * the number of chip selects (NCS) and the actually needed refresh
 390  * rate is done by setting MPTPR.
 391  *
 392  * PTA is calculated from
 393  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 394  *
 395  *      gclk      CPU clock (not bus clock!)
 396  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 397  *
 398  * 4096  Rows from SDRAM example configuration
 399  * 1000  factor s -> ms
 400  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 401  *    4  Number of refresh cycles per period
 402  *   64  Refresh cycle in ms per number of rows
 403  * --------------------------------------------
 404  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 405  *
 406  *  50 MHz =>  50.000.000 / Divider =  98
 407  *  66 Mhz =>  66.000.000 / Divider = 129
 408  *  80 Mhz =>  80.000.000 / Divider = 156
 409  * 100 Mhz => 100.000.000 / Divider = 195
 410  */
 411
 412 #define CONFIG_SYS_PTA_PER_CLK  ((4096 * 32 * 1000) / (4 * 64))
 413 #define CONFIG_SYS_MAMR_PTA     98
 414
 415 /*
 416  * For 16 MBit, refresh rates could be 31.3 us
 417  * (= 64 ms / 2K = 125 / quad bursts).
 418  * For a simpler initialization, 15.6 us is used instead.
 419  *
 420  * #define CONFIG_SYS_MPTPR_2BK_2K      MPTPR_PTP_DIV32         for 2 banks
 421  * #define CONFIG_SYS_MPTPR_1BK_2K      MPTPR_PTP_DIV64         for 1 bank
 422  */
 423 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 424 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 425
 426 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 427 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 428 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 429
 430 /*
 431  * MAMR settings for SDRAM
 432  */
 433
 434 /* 8 column SDRAM */
 435 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 436                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 437                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 438 /* 9 column SDRAM */
 439 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 440                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 441                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 442
 443 #define CONFIG_SYS_MAMR_VAL     0x30904114      /* for SDRAM */
 444 #define CONFIG_SYS_MBMR_VAL     0xff001111      /* for Interbus-MPM */
 445
 446 /*-----------------------------------------------------------------------
 447  * I2C stuff
 448  */
 449
 450 /* enable I2C and select the hardware/software driver */
 451 #define CONFIG_SYS_I2C
 452 #define CONFIG_SYS_I2C_SOFT             /* I2C bit-banged */
 453 #define CONFIG_SYS_I2C_SOFT_SPEED       93000 /* 93 kHz is supposed to work */
 454 #define CONFIG_SYS_I2C_SOFT_SLAVE       0xFE
 455 /*
 456  * Software (bit-bang) I2C driver configuration
 457  */
 458 #define PB_SCL          0x00000020      /* PB 26 */
 459 #define PB_SDA          0x00000010      /* PB 27 */
 460
 461 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 462 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 463 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 464 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 465 #define I2C_SDA(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 466                         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 467 #define I2C_SCL(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 468                         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 469 #define I2C_DELAY       udelay(2)       /* 1/4 I2C clock duration */
 470
 471 /*-----------------------------------------------------------------------
 472  * I2C EEPROM (24C164)
 473  */
 474 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x58    /* EEPROM AT24C164              */
 475 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 476 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* takes up to 10 msec  */
 477 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 478
 479 #define CONFIG_FEC_ENET         1       /* use FEC ethernet  */
 480 #define FEC_ENET
 481 #define CONFIG_MII
 482 #define CONFIG_MII_INIT         1
 483 #define CONFIG_SYS_DISCOVER_PHY 1
 484
 485 #endif  /* __CONFIG_H */