include/configs/ulcb.h

   1 /*
   2  * include/configs/ulcb.h
   3  *     This file is ULCB board configuration.
   4  *
   5  * Copyright (C) 2017 Renesas Electronics Corporation
   6  *
   7  * SPDX-License-Identifier: GPL-2.0+
   8  */
   9
  10 #ifndef __ULCB_H
  11 #define __ULCB_H
  12
  13 #undef DEBUG
  14
  15 #define CONFIG_RCAR_BOARD_STRING "ULCB"
  16
  17 #include "rcar-gen3-common.h"
  18
  19 /* M3 ULCB has 2 banks, each with 1 GiB of RAM */
  20 #if defined(CONFIG_R8A7796)
  21 #undef PHYS_SDRAM_1_SIZE
  22 #undef PHYS_SDRAM_2_SIZE
  23 #define PHYS_SDRAM_1_SIZE               (0x40000000u - DRAM_RSV_SIZE)
  24 #define PHYS_SDRAM_2_SIZE               0x40000000u
  25 #endif
  26
  27 /* SCIF */
  28 #define CONFIG_CONS_SCIF2
  29 #define CONFIG_CONS_INDEX       2
  30 #define CONFIG_SH_SCIF_CLK_FREQ        CONFIG_S3D4_CLK_FREQ
  31
  32 /* [A] Hyper Flash */
  33 /* use to RPC(SPI Multi I/O Bus Controller) */
  34
  35 /* Ethernet RAVB */
  36 #define CONFIG_NET_MULTI
  37 #define CONFIG_PHY_MICREL
  38 #define CONFIG_BITBANGMII
  39 #define CONFIG_BITBANGMII_MULTI
  40
  41 /* Board Clock */
  42 /* XTAL_CLK : 33.33MHz */
  43 #define RCAR_XTAL_CLK           33333333u
  44 #define CONFIG_SYS_CLK_FREQ     RCAR_XTAL_CLK
  45 /* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */
  46 /* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz          */
  47 #define CONFIG_CP_CLK_FREQ      (CONFIG_SYS_CLK_FREQ / 2)
  48 #define CONFIG_PLL1_CLK_FREQ    (CONFIG_SYS_CLK_FREQ * 192 / 2)
  49 #define CONFIG_S3D2_CLK_FREQ    (266666666u/2)
  50 #define CONFIG_S3D4_CLK_FREQ    (266666666u/4)
  51
  52 /* Generic Timer Definitions (use in assembler source) */
  53 #define COUNTER_FREQUENCY       0xFE502A        /* 16.66MHz from CPclk */
  54
  55 /* Generic Interrupt Controller Definitions */
  56 #define CONFIG_GICV2
  57 #define GICD_BASE       0xF1010000
  58 #define GICC_BASE       0xF1020000
  59
  60 /* CPLD SPI */
  61 #define CONFIG_CMD_SPI
  62 #define CONFIG_SOFT_SPI
  63 #define SPI_DELAY       udelay(0)
  64 #define SPI_SDA(val)    ulcb_softspi_sda(val)
  65 #define SPI_SCL(val)    ulcb_softspi_scl(val)
  66 #define SPI_READ        ulcb_softspi_read()
  67 #ifndef __ASSEMBLY__
  68 void ulcb_softspi_sda(int);
  69 void ulcb_softspi_scl(int);
  70 unsigned char ulcb_softspi_read(void);
  71 #endif
  72
  73 /* i2c */
  74 #define CONFIG_SYS_I2C
  75 #define CONFIG_SYS_I2C_SH
  76 #define CONFIG_SYS_I2C_SLAVE            0x60
  77 #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS       1
  78 #define CONFIG_SYS_I2C_SH_SPEED0        400000
  79 #define CONFIG_SH_I2C_DATA_HIGH         4
  80 #define CONFIG_SH_I2C_DATA_LOW          5
  81 #define CONFIG_SH_I2C_CLOCK             10000000
  82
  83 #define CONFIG_SYS_I2C_POWERIC_ADDR     0x30
  84
  85 /* USB */
  86 #ifdef CONFIG_R8A7795
  87 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3
  88 #else
  89 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  90 #endif
  91
  92 /* SDHI */
  93 #define CONFIG_SH_SDHI_FREQ             200000000
  94
  95 /* Environment in eMMC, at the end of 2nd "boot sector" */
  96 #define CONFIG_ENV_OFFSET               (-CONFIG_ENV_SIZE)
  97 #define CONFIG_SYS_MMC_ENV_DEV          1
  98 #define CONFIG_SYS_MMC_ENV_PART         2
  99
 100 /* Module stop status bits */
 101 /* MFIS, SCIF1 */
 102 #define CONFIG_SMSTP2_ENA       0x00002040
 103 /* SCIF2 */
 104 #define CONFIG_SMSTP3_ENA       0x00000400
 105 /* INTC-AP, IRQC */
 106 #define CONFIG_SMSTP4_ENA       0x00000180
 107
 108 #endif /* __ULCB_H */