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1 /*
2 * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 /* U-Boot - Common settings for UniPhier Family */
8
9 #ifndef __CONFIG_UNIPHIER_COMMON_H__
10 #define __CONFIG_UNIPHIER_COMMON_H__
11
12 #define CONFIG_I2C_EEPROM
13 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
14
15 #ifdef CONFIG_SYS_NS16550_SERIAL
16 #define CONFIG_SYS_NS16550_COM1 CONFIG_SUPPORT_CARD_UART_BASE
17 #define CONFIG_SYS_NS16550_CLK 12288000
18 #define CONFIG_SYS_NS16550_REG_SIZE -2
19 #endif
20
21 /* TODO: move to Kconfig and device tree */
22 #if 0
23 #define CONFIG_SYS_NS16550_SERIAL
24 #endif
25
26 #define CONFIG_SMC911X
27
28 /* dummy: referenced by examples/standalone/smc911x_eeprom.c */
29 #define CONFIG_SMC911X_BASE 0
30 #define CONFIG_SMC911X_32_BIT
31
32 /*-----------------------------------------------------------------------
33 * MMU and Cache Setting
34 *----------------------------------------------------------------------*/
35
36 /* Comment out the following to enable L1 cache */
37 /* #define CONFIG_SYS_ICACHE_OFF */
38 /* #define CONFIG_SYS_DCACHE_OFF */
39
40 #define CONFIG_SYS_CACHELINE_SIZE 32
41
42 /* Comment out the following to enable L2 cache */
43 #define CONFIG_UNIPHIER_L2CACHE_ON
44
45 #define CONFIG_DISPLAY_CPUINFO
46 #define CONFIG_DISPLAY_BOARDINFO
47 #define CONFIG_MISC_INIT_F
48 #define CONFIG_BOARD_EARLY_INIT_F
49 #define CONFIG_BOARD_EARLY_INIT_R
50 #define CONFIG_BOARD_LATE_INIT
51
52 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
53
54 #define CONFIG_TIMESTAMP
55
56 /* FLASH related */
57 #define CONFIG_MTD_DEVICE
58
59 /*
60 * uncomment the following to disable FLASH related code.
61 */
62 /* #define CONFIG_SYS_NO_FLASH */
63
64 #define CONFIG_FLASH_CFI_DRIVER
65 #define CONFIG_SYS_FLASH_CFI
66
67 #define CONFIG_SYS_MAX_FLASH_SECT 256
68 #define CONFIG_SYS_MONITOR_BASE 0
69 #define CONFIG_SYS_FLASH_BASE 0
70
71 /*
72 * flash_toggle does not work for out supoort card.
73 * We need to use flash_status_poll.
74 */
75 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
76
77 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
78
79 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
80
81 /* serial console configuration */
82 #define CONFIG_BAUDRATE 115200
83
84
85 #if !defined(CONFIG_SPL_BUILD)
86 #define CONFIG_USE_ARCH_MEMSET
87 #define CONFIG_USE_ARCH_MEMCPY
88 #endif
89
90 #define CONFIG_SYS_LONGHELP /* undef to save memory */
91
92 #define CONFIG_CMDLINE_EDITING /* add command line history */
93 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
94 /* Print Buffer Size */
95 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
96 #define CONFIG_SYS_MAXARGS 16 /* max number of command */
97 /* Boot Argument Buffer Size */
98 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
99
100 #define CONFIG_CONS_INDEX 1
101
102 /* #define CONFIG_ENV_IS_NOWHERE */
103 /* #define CONFIG_ENV_IS_IN_NAND */
104 #define CONFIG_ENV_IS_IN_MMC
105 #define CONFIG_ENV_OFFSET 0x80000
106 #define CONFIG_ENV_SIZE 0x2000
107 /* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
108
109 #define CONFIG_SYS_MMC_ENV_DEV 0
110 #define CONFIG_SYS_MMC_ENV_PART 1
111
112 /* Time clock 1MHz */
113 #define CONFIG_SYS_TIMER_RATE 1000000
114
115 /*
116 * By default, ARP timeout is 5 sec.
117 * The first ARP request does not seem to work.
118 * So we need to retry ARP request anyway.
119 * We want to shrink the interval until the second ARP request.
120 */
121 #define CONFIG_ARP_TIMEOUT 500UL /* 0.5 msec */
122
123 #define CONFIG_SYS_MAX_NAND_DEVICE 1
124 #define CONFIG_SYS_NAND_MAX_CHIPS 2
125 #define CONFIG_SYS_NAND_ONFI_DETECTION
126
127 #define CONFIG_NAND_DENALI_ECC_SIZE 1024
128
129 #ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD3
130 #define CONFIG_SYS_NAND_REGS_BASE 0xf8100000
131 #define CONFIG_SYS_NAND_DATA_BASE 0xf8000000
132 #else
133 #define CONFIG_SYS_NAND_REGS_BASE 0x68100000
134 #define CONFIG_SYS_NAND_DATA_BASE 0x68000000
135 #endif
136
137 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
138
139 #define CONFIG_SYS_NAND_USE_FLASH_BBT
140 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
141
142 /* USB */
143 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
144 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4
145 #define CONFIG_CMD_FAT
146 #define CONFIG_FAT_WRITE
147 #define CONFIG_DOS_PARTITION
148
149 /* SD/MMC */
150 #define CONFIG_CMD_MMC
151 #define CONFIG_SUPPORT_EMMC_BOOT
152 #define CONFIG_GENERIC_MMC
153
154 /* memtest works on */
155 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
156 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000)
157
158 #define CONFIG_BOOTDELAY 3
159 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
160
161 /*
162 * Network Configuration
163 */
164 #define CONFIG_SERVERIP 192.168.11.1
165 #define CONFIG_IPADDR 192.168.11.10
166 #define CONFIG_GATEWAYIP 192.168.11.1
167 #define CONFIG_NETMASK 255.255.255.0
168
169 #define CONFIG_LOADADDR 0x84000000
170 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
171
172 #define CONFIG_CMDLINE_EDITING /* add command line history */
173
174 #define CONFIG_BOOTCOMMAND "run $bootmode"
175
176 #define CONFIG_ROOTPATH "/nfs/root/path"
177 #define CONFIG_NFSBOOTCOMMAND \
178 "setenv bootargs $bootargs root=/dev/nfs rw " \
179 "nfsroot=$serverip:$rootpath " \
180 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
181 "run __nfsboot"
182
183 #ifdef CONFIG_FIT
184 #define CONFIG_BOOTFILE "fitImage"
185 #define LINUXBOOT_ENV_SETTINGS \
186 "fit_addr=0x00100000\0" \
187 "fit_addr_r=0x84100000\0" \
188 "fit_size=0x00f00000\0" \
189 "norboot=setexpr fit_addr $nor_base + $fit_addr &&" \
190 "bootm $fit_addr\0" \
191 "nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \
192 "bootm $fit_addr_r\0" \
193 "tftpboot=tftpboot $fit_addr_r $bootfile &&" \
194 "bootm $fit_addr_r\0" \
195 "__nfsboot=run tftpboot\0"
196 #else
197 #define CONFIG_CMD_BOOTZ
198 #define CONFIG_BOOTFILE "zImage"
199 #define LINUXBOOT_ENV_SETTINGS \
200 "fdt_addr=0x00100000\0" \
201 "fdt_addr_r=0x84100000\0" \
202 "fdt_size=0x00008000\0" \
203 "kernel_addr=0x00200000\0" \
204 "kernel_addr_r=0x80208000\0" \
205 "kernel_size=0x00800000\0" \
206 "ramdisk_addr=0x00a00000\0" \
207 "ramdisk_addr_r=0x84a00000\0" \
208 "ramdisk_size=0x00600000\0" \
209 "ramdisk_file=rootfs.cpio.uboot\0" \
210 "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \
211 "bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
212 "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \
213 "cp.b $kernel_addr $kernel_addr_r $kernel_size &&" \
214 "setexpr ramdisk_addr_r $nor_base + $ramdisk_addr &&" \
215 "setexpr fdt_addr_r $nor_base + $fdt_addr &&" \
216 "run boot_common\0" \
217 "nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
218 "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
219 "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
220 "run boot_common\0" \
221 "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \
222 "tftpboot $ramdisk_addr_r $ramdisk_file &&" \
223 "tftpboot $fdt_addr_r $fdt_file &&" \
224 "run boot_common\0" \
225 "__nfsboot=tftpboot $kernel_addr_r $bootfile &&" \
226 "tftpboot $fdt_addr_r $fdt_file &&" \
227 "tftpboot $fdt_addr_r $fdt_file &&" \
228 "setenv ramdisk_addr_r - &&" \
229 "run boot_common\0"
230 #endif
231
232 #define CONFIG_EXTRA_ENV_SETTINGS \
233 "netdev=eth0\0" \
234 "verify=n\0" \
235 "nor_base=0x42000000\0" \
236 "emmcupdate=mmcsetn &&" \
237 "mmc partconf $mmc_first_dev 0 1 1 &&" \
238 "mmc erase 0 800 &&" \
239 "tftpboot u-boot-spl.bin &&" \
240 "mmc write $loadaddr 0 80 &&" \
241 "tftpboot u-boot.img &&" \
242 "mmc write $loadaddr 80 780\0" \
243 "nandupdate=nand erase 0 0x00100000 &&" \
244 "tftpboot u-boot-spl.bin &&" \
245 "nand write $loadaddr 0 0x00010000 &&" \
246 "tftpboot u-boot.img &&" \
247 "nand write $loadaddr 0x00010000 0x000f0000\0" \
248 LINUXBOOT_ENV_SETTINGS
249
250 #define CONFIG_SYS_BOOTMAPSZ 0x20000000
251
252 #define CONFIG_SYS_SDRAM_BASE 0x80000000
253 #define CONFIG_NR_DRAM_BANKS 2
254
255 #if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) || \
256 defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
257 defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
258 #define CONFIG_SPL_TEXT_BASE 0x00040000
259 #else
260 #define CONFIG_SPL_TEXT_BASE 0x00100000
261 #endif
262
263 #define CONFIG_SPL_STACK (0x00100000)
264 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
265
266 #define CONFIG_PANIC_HANG
267
268 #define CONFIG_SPL_FRAMEWORK
269 #define CONFIG_SPL_SERIAL_SUPPORT
270 #define CONFIG_SPL_NAND_SUPPORT
271 #define CONFIG_SPL_MMC_SUPPORT
272
273 #define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */
274 #define CONFIG_SPL_LIBGENERIC_SUPPORT
275
276 #define CONFIG_SPL_BOARD_INIT
277
278 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000
279 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x80
280
281 #define CONFIG_SPL_MAX_FOOTPRINT 0x10000
282
283 #endif /* __CONFIG_UNIPHIER_COMMON_H__ */