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ARM: uniphier: add sramupdate command
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1 /*
2 * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 /* U-Boot - Common settings for UniPhier Family */
8
9 #ifndef __CONFIG_UNIPHIER_COMMON_H__
10 #define __CONFIG_UNIPHIER_COMMON_H__
11
12 #define CONFIG_I2C_EEPROM
13 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
14
15 #ifdef CONFIG_SYS_NS16550_SERIAL
16 #define CONFIG_SYS_NS16550_COM1 CONFIG_SUPPORT_CARD_UART_BASE
17 #define CONFIG_SYS_NS16550_CLK 12288000
18 #define CONFIG_SYS_NS16550_REG_SIZE -2
19 #endif
20
21 #define CONFIG_SMC911X
22
23 /* dummy: referenced by examples/standalone/smc911x_eeprom.c */
24 #define CONFIG_SMC911X_BASE 0
25 #define CONFIG_SMC911X_32_BIT
26
27 /*-----------------------------------------------------------------------
28 * MMU and Cache Setting
29 *----------------------------------------------------------------------*/
30
31 /* Comment out the following to enable L1 cache */
32 /* #define CONFIG_SYS_ICACHE_OFF */
33 /* #define CONFIG_SYS_DCACHE_OFF */
34
35 #define CONFIG_SYS_CACHELINE_SIZE 32
36
37 /* Comment out the following to disable L2 cache */
38 #define CONFIG_UNIPHIER_L2CACHE_ON
39
40 #define CONFIG_DISPLAY_CPUINFO
41 #define CONFIG_DISPLAY_BOARDINFO
42 #define CONFIG_MISC_INIT_F
43 #define CONFIG_BOARD_EARLY_INIT_F
44 #define CONFIG_BOARD_EARLY_INIT_R
45 #define CONFIG_BOARD_LATE_INIT
46
47 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
48
49 #define CONFIG_TIMESTAMP
50
51 /* FLASH related */
52 #define CONFIG_MTD_DEVICE
53
54 /*
55 * uncomment the following to disable FLASH related code.
56 */
57 /* #define CONFIG_SYS_NO_FLASH */
58
59 #define CONFIG_FLASH_CFI_DRIVER
60 #define CONFIG_SYS_FLASH_CFI
61
62 #define CONFIG_SYS_MAX_FLASH_SECT 256
63 #define CONFIG_SYS_MONITOR_BASE 0
64 #define CONFIG_SYS_MONITOR_LEN 0x00080000 /* 512KB */
65 #define CONFIG_SYS_FLASH_BASE 0
66
67 /*
68 * flash_toggle does not work for out supoort card.
69 * We need to use flash_status_poll.
70 */
71 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
72
73 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
74
75 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
76
77 /* serial console configuration */
78 #define CONFIG_BAUDRATE 115200
79
80
81 #if !defined(CONFIG_SPL_BUILD)
82 #define CONFIG_USE_ARCH_MEMSET
83 #define CONFIG_USE_ARCH_MEMCPY
84 #endif
85
86 #define CONFIG_SYS_LONGHELP /* undef to save memory */
87
88 #define CONFIG_CMDLINE_EDITING /* add command line history */
89 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
90 /* Print Buffer Size */
91 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
92 #define CONFIG_SYS_MAXARGS 16 /* max number of command */
93 /* Boot Argument Buffer Size */
94 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
95
96 #define CONFIG_CONS_INDEX 1
97
98 /* #define CONFIG_ENV_IS_NOWHERE */
99 /* #define CONFIG_ENV_IS_IN_NAND */
100 #define CONFIG_ENV_IS_IN_MMC
101 #define CONFIG_ENV_OFFSET 0x80000
102 #define CONFIG_ENV_SIZE 0x2000
103 /* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
104
105 #define CONFIG_SYS_MMC_ENV_DEV 0
106 #define CONFIG_SYS_MMC_ENV_PART 1
107
108 /* Time clock 1MHz */
109 #define CONFIG_SYS_TIMER_RATE 1000000
110
111 /*
112 * By default, ARP timeout is 5 sec.
113 * The first ARP request does not seem to work.
114 * So we need to retry ARP request anyway.
115 * We want to shrink the interval until the second ARP request.
116 */
117 #define CONFIG_ARP_TIMEOUT 500UL /* 0.5 msec */
118
119 #define CONFIG_SYS_MAX_NAND_DEVICE 1
120 #define CONFIG_SYS_NAND_MAX_CHIPS 2
121 #define CONFIG_SYS_NAND_ONFI_DETECTION
122
123 #define CONFIG_NAND_DENALI_ECC_SIZE 1024
124
125 #ifdef CONFIG_ARCH_UNIPHIER_SLD3
126 #define CONFIG_SYS_NAND_REGS_BASE 0xf8100000
127 #define CONFIG_SYS_NAND_DATA_BASE 0xf8000000
128 #else
129 #define CONFIG_SYS_NAND_REGS_BASE 0x68100000
130 #define CONFIG_SYS_NAND_DATA_BASE 0x68000000
131 #endif
132
133 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
134
135 #define CONFIG_SYS_NAND_USE_FLASH_BBT
136 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
137
138 /* USB */
139 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
140 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4
141 #define CONFIG_CMD_FAT
142 #define CONFIG_FAT_WRITE
143 #define CONFIG_DOS_PARTITION
144
145 /* SD/MMC */
146 #define CONFIG_CMD_MMC
147 #define CONFIG_SUPPORT_EMMC_BOOT
148 #define CONFIG_GENERIC_MMC
149
150 /* memtest works on */
151 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
152 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000)
153
154 #define CONFIG_BOOTDELAY 3
155 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
156
157 /*
158 * Network Configuration
159 */
160 #define CONFIG_SERVERIP 192.168.11.1
161 #define CONFIG_IPADDR 192.168.11.10
162 #define CONFIG_GATEWAYIP 192.168.11.1
163 #define CONFIG_NETMASK 255.255.255.0
164
165 #define CONFIG_LOADADDR 0x84000000
166 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
167
168 #define CONFIG_CMDLINE_EDITING /* add command line history */
169
170 #define CONFIG_BOOTCOMMAND "run $bootmode"
171
172 #define CONFIG_ROOTPATH "/nfs/root/path"
173 #define CONFIG_NFSBOOTCOMMAND \
174 "setenv bootargs $bootargs root=/dev/nfs rw " \
175 "nfsroot=$serverip:$rootpath " \
176 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
177 "run __nfsboot"
178
179 #ifdef CONFIG_FIT
180 #define CONFIG_BOOTFILE "fitImage"
181 #define LINUXBOOT_ENV_SETTINGS \
182 "fit_addr=0x00100000\0" \
183 "fit_addr_r=0x84100000\0" \
184 "fit_size=0x00f00000\0" \
185 "norboot=setexpr fit_addr $nor_base + $fit_addr &&" \
186 "bootm $fit_addr\0" \
187 "nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \
188 "bootm $fit_addr_r\0" \
189 "tftpboot=tftpboot $fit_addr_r $bootfile &&" \
190 "bootm $fit_addr_r\0" \
191 "__nfsboot=run tftpboot\0"
192 #else
193 #define CONFIG_CMD_BOOTZ
194 #define CONFIG_BOOTFILE "zImage"
195 #define LINUXBOOT_ENV_SETTINGS \
196 "fdt_addr=0x00100000\0" \
197 "fdt_addr_r=0x84100000\0" \
198 "fdt_size=0x00008000\0" \
199 "kernel_addr=0x00200000\0" \
200 "kernel_addr_r=0x80208000\0" \
201 "kernel_size=0x00800000\0" \
202 "ramdisk_addr=0x00a00000\0" \
203 "ramdisk_addr_r=0x84a00000\0" \
204 "ramdisk_size=0x00600000\0" \
205 "ramdisk_file=rootfs.cpio.uboot\0" \
206 "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \
207 "bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
208 "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \
209 "cp.b $kernel_addr $kernel_addr_r $kernel_size &&" \
210 "setexpr ramdisk_addr_r $nor_base + $ramdisk_addr &&" \
211 "setexpr fdt_addr_r $nor_base + $fdt_addr &&" \
212 "run boot_common\0" \
213 "nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
214 "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
215 "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
216 "run boot_common\0" \
217 "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \
218 "tftpboot $ramdisk_addr_r $ramdisk_file &&" \
219 "tftpboot $fdt_addr_r $fdt_file &&" \
220 "run boot_common\0" \
221 "__nfsboot=tftpboot $kernel_addr_r $bootfile &&" \
222 "tftpboot $fdt_addr_r $fdt_file &&" \
223 "tftpboot $fdt_addr_r $fdt_file &&" \
224 "setenv ramdisk_addr_r - &&" \
225 "run boot_common\0"
226 #endif
227
228 #define CONFIG_EXTRA_ENV_SETTINGS \
229 "netdev=eth0\0" \
230 "verify=n\0" \
231 "nor_base=0x42000000\0" \
232 "sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \
233 "tftpboot $tmp_addr u-boot-spl.bin &&" \
234 "setexpr tmp_addr $nor_base + 0x60000 &&" \
235 "tftpboot $tmp_addr u-boot.bin\0" \
236 "emmcupdate=mmcsetn &&" \
237 "mmc partconf $mmc_first_dev 0 1 1 &&" \
238 "mmc erase 0 800 &&" \
239 "tftpboot u-boot-spl.bin &&" \
240 "mmc write $loadaddr 0 80 &&" \
241 "tftpboot u-boot.bin &&" \
242 "mmc write $loadaddr 80 780\0" \
243 "nandupdate=nand erase 0 0x00100000 &&" \
244 "tftpboot u-boot-spl.bin &&" \
245 "nand write $loadaddr 0 0x00010000 &&" \
246 "tftpboot u-boot.bin &&" \
247 "nand write $loadaddr 0x00010000 0x000f0000\0" \
248 LINUXBOOT_ENV_SETTINGS
249
250 #define CONFIG_SYS_BOOTMAPSZ 0x20000000
251
252 #define CONFIG_SYS_SDRAM_BASE 0x80000000
253 #define CONFIG_NR_DRAM_BANKS 2
254
255 #if defined(CONFIG_ARCH_UNIPHIER_SLD3) || defined(CONFIG_ARCH_UNIPHIER_LD4) || \
256 defined(CONFIG_ARCH_UNIPHIER_SLD8)
257 #define CONFIG_SPL_TEXT_BASE 0x00040000
258 #else
259 #define CONFIG_SPL_TEXT_BASE 0x00100000
260 #endif
261
262 #define CONFIG_SPL_STACK (0x00100000)
263 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
264
265 #define CONFIG_PANIC_HANG
266
267 #define CONFIG_SPL_FRAMEWORK
268 #define CONFIG_SPL_SERIAL_SUPPORT
269 #define CONFIG_SPL_NOR_SUPPORT
270 #define CONFIG_SPL_NAND_SUPPORT
271 #define CONFIG_SPL_MMC_SUPPORT
272
273 #define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */
274 #define CONFIG_SPL_LIBGENERIC_SUPPORT
275
276 #define CONFIG_SPL_BOARD_INIT
277
278 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000
279
280 /* subtract sizeof(struct image_header) */
281 #define CONFIG_SYS_UBOOT_BASE (0x60000 - 0x40)
282 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x80
283
284 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
285 #define CONFIG_SPL_MAX_FOOTPRINT 0x10000
286 #define CONFIG_SPL_MAX_SIZE 0x10000
287
288 #endif /* __CONFIG_UNIPHIER_COMMON_H__ */