include/configs/v37.h

   1 /*
   2  * (C) Copyright 2000, 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_MPC823           1       /* This is a MPC823 CPU         */
  21 #define CONFIG_V37              1       /* ...on a Marel V37 board      */
  22
  23 #define CONFIG_SYS_TEXT_BASE    0x40000000
  24
  25 #define CONFIG_LCD
  26 #define CONFIG_MPC8XX_LCD
  27 #define CONFIG_SHARP_LQ084V1DG21
  28 #undef CONFIG_LCD_LOGO
  29
  30 /*-----------------------------------------------------------------------------
  31  * I2C Configuration
  32  *-----------------------------------------------------------------------------
  33  */
  34 #define CONFIG_I2C              1
  35 #define CONFIG_SYS_I2C_SLAVE           0x2
  36
  37 #define CONFIG_8xx_CONS_SMC1    1
  38 #undef  CONFIG_8xx_CONS_SMC2            /* Console is on SMC2           */
  39 #undef  CONFIG_8xx_CONS_NONE
  40 #define CONFIG_BAUDRATE         9600    /* console baudrate = 115kbps   */
  41 #if 0
  42 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  43 #else
  44 #define CONFIG_BOOTDELAY        2       /* autoboot after 2 seconds     */
  45 #endif
  46
  47 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  48 #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  49
  50 #undef  CONFIG_BOOTARGS
  51
  52 #define CONFIG_BOOTCOMMAND                                                      \
  53         "tftpboot; "                                                            \
  54         "setenv bootargs console=tty0 "                                   \
  55         "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "                     \
  56         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
  57         "bootm"
  58
  59 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  60 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  61
  62 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  63
  64 #define CONFIG_CAN_DRIVER       1       /* CAN Driver support enabled   */
  65
  66 /*
  67  * BOOTP options
  68  */
  69 #define CONFIG_BOOTP_SUBNETMASK
  70 #define CONFIG_BOOTP_GATEWAY
  71 #define CONFIG_BOOTP_HOSTNAME
  72 #define CONFIG_BOOTP_BOOTPATH
  73 #define CONFIG_BOOTP_BOOTFILESIZE
  74
  75
  76 #define CONFIG_MAC_PARTITION
  77 #define CONFIG_DOS_PARTITION
  78
  79 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
  80
  81
  82 /*
  83  * Command line configuration.
  84  */
  85 #include <config_cmd_default.h>
  86
  87 #define CONFIG_CMD_JFFS2
  88 #define CONFIG_CMD_DATE
  89
  90
  91 /*
  92  * JFFS2 partitions
  93  *
  94  */
  95 /* No command line, one static partition, whole device */
  96 #undef CONFIG_CMD_MTDPARTS
  97 #define CONFIG_JFFS2_DEV                "nor1"
  98 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
  99 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 100
 101 /* mtdparts command line support */
 102 /* Note: fake mtd_id used, no linux mtd map file */
 103 /*
 104 #define CONFIG_CMD_MTDPARTS
 105 #define MTDIDS_DEFAULT          "nor1=v37-1"
 106 #define MTDPARTS_DEFAULT        "mtdparts=v37-1:-(jffs2)"
 107 */
 108
 109 /*
 110  * Miscellaneous configurable options
 111  */
 112 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 113 #if defined(CONFIG_CMD_KGDB)
 114 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 115 #else
 116 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 117 #endif
 118 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 119 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 120 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 121
 122 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 123 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 124
 125 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 126
 127 /*
 128  * Low Level Configuration Settings
 129  * (address mappings, register initial values, etc.)
 130  * You should know what you are doing if you make changes here.
 131  */
 132 /*-----------------------------------------------------------------------
 133  * Internal Memory Mapped Register
 134  */
 135 #define CONFIG_SYS_IMMR         0xF0000000
 136
 137 /*-----------------------------------------------------------------------
 138  * Definitions for initial stack pointer and data area (in DPRAM)
 139  */
 140 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 141 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 142 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 143 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 144
 145 /*-----------------------------------------------------------------------
 146  * Start addresses for the final memory configuration
 147  * (Set up by the startup code)
 148  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 149  */
 150 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 151 #define CONFIG_SYS_FLASH_BASE0          0x40000000
 152 #define CONFIG_SYS_FLASH_BASE1          0x60000000
 153 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_FLASH_BASE1
 154
 155 #if defined(DEBUG)
 156 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 157 #else
 158 #define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor   */
 159 #endif
 160 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE0
 161 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 162
 163 /*
 164  * For booting Linux, the board info and command line data
 165  * have to be in the first 8 MB of memory, since this is
 166  * the maximum mapped by the Linux kernel during initialization.
 167  */
 168 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 169
 170 /*-----------------------------------------------------------------------
 171  * FLASH organization
 172  */
 173 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks           */
 174 #define CONFIG_SYS_MAX_FLASH_SECT       35      /* max number of sectors on one chip    */
 175
 176 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 177 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 178
 179 #define CONFIG_ENV_IS_IN_NVRAM  1
 180 #define CONFIG_ENV_ADDR         0x80000000/* Address of Environment */
 181 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 182
 183 #define CONFIG_ENV_OFFSET               0
 184
 185 /*-----------------------------------------------------------------------
 186  * Cache Configuration
 187  */
 188 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 189 #if defined(CONFIG_CMD_KGDB)
 190 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 191 #endif
 192
 193 /*-----------------------------------------------------------------------
 194  * SYPCR - System Protection Control                            11-9
 195  * SYPCR can only be written once after reset!
 196  *-----------------------------------------------------------------------
 197  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 198  */
 199 #if defined(CONFIG_WATCHDOG)
 200 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 201                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 202 #else
 203 #define CONFIG_SYS_SYPCR        0xFFFFFF88
 204 #endif
 205
 206 /*-----------------------------------------------------------------------
 207  * SIUMCR - SIU Module Configuration                            11-6
 208  *-----------------------------------------------------------------------
 209  * PCMCIA config., multi-function pin tri-state
 210  */
 211 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_FRC | SIUMCR_GB5E)
 212
 213 /*-----------------------------------------------------------------------
 214  * TBSCR - Time Base Status and Control                         11-26
 215  *-----------------------------------------------------------------------
 216  * Clear Reference Interrupt Status, Timebase freezing enabled
 217  */
 218 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 219
 220 /*-----------------------------------------------------------------------
 221  * RTCSC - Real-Time Clock Status and Control Register          11-27
 222  *-----------------------------------------------------------------------
 223  */
 224 /*%%%#define CONFIG_SYS_RTCSC   (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
 225 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_RTE)
 226
 227 /*-----------------------------------------------------------------------
 228  * PISCR - Periodic Interrupt Status and Control                11-31
 229  *-----------------------------------------------------------------------
 230  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 231  */
 232 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
 233 /*
 234 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
 235 */
 236
 237 /*-----------------------------------------------------------------------
 238  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 239  *-----------------------------------------------------------------------
 240  * Reset PLL lock status sticky bit, timer expired status bit and timer
 241  * interrupt status bit
 242  *
 243  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 244  */
 245 /* up to 50 MHz we use a 1:1 clock */
 246 #define CONFIG_SYS_PLPRCR       ( (1524 << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TMIST | PLPRCR_TEXPS )
 247
 248 /*-----------------------------------------------------------------------
 249  * SCCR - System Clock and reset Control Register               15-27
 250  *-----------------------------------------------------------------------
 251  * Set clock output, timebase and RTC source and divider,
 252  * power management and some other internal clocks
 253  */
 254 #define SCCR_MASK       SCCR_EBDF11
 255 /* up to 50 MHz we use a 1:1 clock */
 256 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS)
 257
 258 /*-----------------------------------------------------------------------
 259  * PCMCIA stuff
 260  *-----------------------------------------------------------------------
 261  *
 262  */
 263 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 264 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 265 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 266 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 267 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 268 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 269 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 270 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 271
 272 /*-----------------------------------------------------------------------
 273  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 274  *-----------------------------------------------------------------------
 275  */
 276
 277 #undef  CONFIG_IDE_PCCARD               /* Use IDE with PC Card Adapter */
 278
 279 #undef  CONFIG_IDE_PCMCIA               /* Direct IDE    not supported  */
 280 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 281 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 282
 283 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 284 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 285
 286 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 287
 288 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 289
 290 /* Offset for data I/O                  */
 291 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 292
 293 /* Offset for normal register accesses  */
 294 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 295
 296 /* Offset for alternate registers       */
 297 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 298
 299 /*-----------------------------------------------------------------------
 300  *
 301  *-----------------------------------------------------------------------
 302  *
 303  */
 304 #define CONFIG_SYS_DER  0
 305
 306 /*
 307  * Init Memory Controller:
 308  *
 309  * BR0 and OR0 (FLASH)
 310  */
 311
 312 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 313 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #1        */
 314
 315 #define CONFIG_SYS_PRELIM_OR_AM 0xFE000000      /* OR addr mask */
 316
 317 #define CONFIG_SYS_OR_TIMING_FLASH      0xF56
 318
 319 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 320 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V)
 321
 322 #define CONFIG_SYS_OR5_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 323 #define CONFIG_SYS_BR5_PRELIM   ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V)
 324
 325 /*
 326  * BR1 and OR1 (Battery backed SRAM)
 327  */
 328 #define CONFIG_SYS_BR1_PRELIM   0x80000401
 329 #define CONFIG_SYS_OR1_PRELIM   0xFFC00736
 330
 331 /*
 332  * BR2 and OR2 (SDRAM)
 333  */
 334 #define SDRAM_BASE_PRELIM       0x00000000      /* SDRAM base   */
 335 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB */
 336
 337 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000A00
 338
 339 #define CONFIG_SYS_OR2_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
 340 #define CONFIG_SYS_BR2_PRELIM   ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 341
 342 /* Marel V37 mem setting */
 343
 344 #define CONFIG_SYS_BR3_CAN      0xC0000401
 345 #define CONFIG_SYS_OR3_CAN      0xFFFF0724
 346
 347 /*
 348 #define CONFIG_SYS_BR3_PRELIM   0xFA400001
 349 #define CONFIG_SYS_OR3_PRELIM   0xFFFF8910
 350 #define CONFIG_SYS_BR4_PRELIM   0xFA000401
 351 #define CONFIG_SYS_OR4_PRELIM   0xFFFE0970
 352 */
 353
 354 /*
 355  * Memory Periodic Timer Prescaler
 356  */
 357
 358 /* periodic timer for refresh */
 359 #define CONFIG_SYS_MAMR_PTA     97              /* start with divider for 100 MHz       */
 360
 361 /*
 362  * Refresh clock Prescalar
 363  */
 364 #define CONFIG_SYS_MPTPR        MPTPR_PTP_DIV16
 365
 366 /*
 367  * MAMR settings for SDRAM
 368  */
 369
 370 /* 10 column SDRAM */
 371 #define CONFIG_SYS_MAMR_10COL   ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 372                          MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 |   \
 373                          MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
 374
 375 #endif  /* __CONFIG_H */