include/configs/v38b.h

   1 /*
   2  * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering,
   3  * wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*
  12  * High Level Configuration Options
  13  * (easy to change)
  14  */
  15 #define CONFIG_MPC5200                  1       /* This is an MPC5200 CPU */
  16 #define CONFIG_V38B                     1       /* ...on V38B board */
  17
  18 #define CONFIG_SYS_TEXT_BASE            0xFF000000
  19
  20 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000        /* ...running at 33.000000MHz */
  21
  22 #define CONFIG_RTC_PCF8563              1       /* has PCF8563 RTC */
  23 #define CONFIG_MPC5200_DDR              1       /* has DDR SDRAM */
  24
  25 #undef CONFIG_HW_WATCHDOG                       /* don't use watchdog */
  26
  27 #define CONFIG_NETCONSOLE               1
  28
  29 #define CONFIG_BOARD_EARLY_INIT_R       1       /* do board-specific init */
  30 #define CONFIG_BOARD_EARLY_INIT_F       1       /* do board-specific init */
  31 #define CONFIG_MISC_INIT_R
  32
  33 #define CONFIG_SYS_XLB_PIPELINING               1       /* gives better performance */
  34
  35 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
  36
  37 /*
  38  * Serial console configuration
  39  */
  40 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
  41 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
  42 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  43
  44 /*
  45  * DDR
  46  */
  47 #define SDRAM_DDR               1       /* is DDR */
  48 /* Settings for XLB = 132 MHz */
  49 #define SDRAM_MODE              0x018D0000
  50 #define SDRAM_EMODE             0x40090000
  51 #define SDRAM_CONTROL           0x704f0f00
  52 #define SDRAM_CONFIG1           0x73722930
  53 #define SDRAM_CONFIG2           0x47770000
  54 #define SDRAM_TAPDELAY          0x10000000
  55
  56 /*
  57  * PCI - no support
  58  */
  59 #undef CONFIG_PCI
  60
  61 /*
  62  * Partitions
  63  */
  64 #define CONFIG_MAC_PARTITION    1
  65 #define CONFIG_DOS_PARTITION    1
  66
  67 /*
  68  * USB
  69  */
  70 #define CONFIG_USB_OHCI
  71 #define CONFIG_USB_CLOCK        0x0001BBBB
  72 #define CONFIG_USB_CONFIG       0x00001000
  73
  74 /*
  75  * BOOTP options
  76  */
  77 #define CONFIG_BOOTP_BOOTFILESIZE
  78 #define CONFIG_BOOTP_BOOTPATH
  79 #define CONFIG_BOOTP_GATEWAY
  80 #define CONFIG_BOOTP_HOSTNAME
  81
  82 /*
  83  * Command line configuration.
  84  */
  85 #define CONFIG_CMD_IDE
  86 #define CONFIG_CMD_DIAG
  87 #define CONFIG_CMD_IRQ
  88 #define CONFIG_CMD_JFFS2
  89 #define CONFIG_CMD_SDRAM
  90 #define CONFIG_CMD_DATE
  91
  92 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  93
  94 /*
  95  * Boot low with 16 MB Flash
  96  */
  97 #define CONFIG_SYS_LOWBOOT              1
  98 #define CONFIG_SYS_LOWBOOT16            1
  99
 100 /*
 101  * Autobooting
 102  */
 103
 104 #define CONFIG_PREBOOT  "echo;" \
 105         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 106         "echo"
 107
 108 #undef CONFIG_BOOTARGS
 109
 110 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 111         "bootcmd=run net_nfs\0"                                         \
 112         "bootdelay=3\0"                                                 \
 113         "baudrate=115200\0"                                             \
 114         "preboot=echo;echo Type \"run flash_nfs\" to mount root "       \
 115                 "filesystem over NFS; echo\0"                           \
 116         "netdev=eth0\0"                                                 \
 117         "ramargs=setenv bootargs root=/dev/ram rw wdt=off \0"           \
 118         "addip=setenv bootargs $(bootargs) "                            \
 119                 "ip=$(ipaddr):$(serverip):$(gatewayip):"                \
 120                 "$(netmask):$(hostname):$(netdev):off panic=1\0"        \
 121         "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0"            \
 122         "flash_self=run ramargs addip;bootm $(kernel_addr) "            \
 123                 "$(ramdisk_addr)\0"                                     \
 124         "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"     \
 125         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 126                 "nfsroot=$(serverip):$(rootpath) wdt=off\0"             \
 127         "hostname=v38b\0"                                               \
 128         "ethact=FEC\0"                                                  \
 129         "rootpath=/opt/eldk-3.1.1/ppc_6xx\0"                            \
 130         "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; "    \
 131                 "cp.b 200000 ff000000 $(filesize);"                     \
 132                 "prot on ff000000 ff03ffff\0"                           \
 133         "load=tftp 200000 $(u-boot)\0"                                  \
 134         "netmask=255.255.0.0\0"                                         \
 135         "ipaddr=192.168.160.18\0"                                       \
 136         "serverip=192.168.1.1\0"                                        \
 137         "bootfile=/tftpboot/v38b/uImage\0"                              \
 138         "u-boot=/tftpboot/v38b/u-boot.bin\0"                            \
 139         ""
 140
 141 #define CONFIG_BOOTCOMMAND      "run net_nfs"
 142
 143 /*
 144  * IPB Bus clocking configuration.
 145  */
 146 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK                  /* define for 133MHz speed */
 147
 148 /*
 149  * I2C configuration
 150  */
 151 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 152 #define CONFIG_SYS_I2C_MODULE           2       /* Select I2C module #1 or #2 */
 153 #define CONFIG_SYS_I2C_SPEED            100000  /* 100 kHz */
 154 #define CONFIG_SYS_I2C_SLAVE            0x7F
 155
 156 /*
 157  * EEPROM configuration
 158  */
 159 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x */
 160 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 161 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 162 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   70
 163
 164 /*
 165  * RTC configuration
 166  */
 167 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
 168
 169 /*
 170  * Flash configuration - use CFI driver
 171  */
 172 #define CONFIG_SYS_FLASH_CFI            1               /* Flash is CFI conformant */
 173 #define CONFIG_FLASH_CFI_DRIVER 1               /* Use the common driver */
 174 #define CONFIG_SYS_FLASH_CFI_AMD_RESET  1
 175 #define CONFIG_SYS_FLASH_BASE           0xFF000000
 176 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* max num of flash banks */
 177 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 178 #define CONFIG_SYS_FLASH_SIZE           0x01000000      /* 16 MiB */
 179 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* max num of sects on one chip */
 180 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1       /* flash write speed-up */
 181
 182 /*
 183  * Environment settings
 184  */
 185 #define CONFIG_ENV_IS_IN_FLASH  1
 186 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00040000)
 187 #define CONFIG_ENV_SIZE         0x10000
 188 #define CONFIG_ENV_SECT_SIZE    0x10000
 189 #define CONFIG_ENV_OVERWRITE    1
 190
 191 /*
 192  * Memory map
 193  */
 194 #define CONFIG_SYS_MBAR         0xF0000000
 195 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 196 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 197
 198 /* Use SRAM until RAM will be available */
 199 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 200 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE       /* Size of used area in DPRAM */
 201
 202 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 203 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 204
 205 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 206 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 207 #   define CONFIG_SYS_RAMBOOT           1
 208 #endif
 209
 210 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256kB for Monitor */
 211 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128kB for malloc() */
 212 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Linux initial memory map */
 213
 214 /*
 215  * Ethernet configuration
 216  */
 217 #define CONFIG_MPC5xxx_FEC      1
 218 #define CONFIG_MPC5xxx_FEC_MII100
 219 #define CONFIG_PHY_ADDR         0x00
 220 #define CONFIG_MII              1
 221
 222 /*
 223  * GPIO configuration
 224  */
 225 #define CONFIG_SYS_GPS_PORT_CONFIG      0x90001404
 226
 227 /*
 228  * Miscellaneous configurable options
 229  */
 230 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 231 #if defined(CONFIG_CMD_KGDB)
 232 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size */
 233 #else
 234 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 235 #endif
 236 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
 237 #define CONFIG_SYS_MAXARGS              16              /* max number of command args */
 238 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 239
 240 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 241 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM */
 242
 243 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 244
 245 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs */
 246 #if defined(CONFIG_CMD_KGDB)
 247 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 248 #endif
 249
 250 /*
 251  * Various low-level settings
 252  */
 253 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 254 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 255
 256 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 257 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 258 #define CONFIG_SYS_BOOTCS_CFG           0x00047801
 259 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 260 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 261
 262 #define CONFIG_SYS_CS_BURST             0x00000000
 263 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
 264
 265 #define CONFIG_SYS_RESET_ADDRESS        0xff000000
 266
 267 /*
 268  * IDE/ATA (supports IDE harddisk)
 269  */
 270 #undef CONFIG_IDE_8xx_PCCARD            /* Don't use IDE with PC Card Adapter */
 271 #undef CONFIG_IDE_8xx_DIRECT            /* Direct IDE not supported */
 272 #undef CONFIG_IDE_LED                   /* LED for ide not supported */
 273
 274 #define CONFIG_IDE_RESET                /* reset for ide supported */
 275 #define CONFIG_IDE_PREINIT
 276
 277 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus */
 278 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus */
 279
 280 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 281
 282 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 283
 284 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)        /* data I/O offset */
 285
 286 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)    /* normal register accesses offset */
 287
 288 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)        /* alternate registers offset */
 289
 290 #define CONFIG_SYS_ATA_STRIDE           4               /* Interval between registers */
 291
 292 /*
 293  * Status LED
 294  */
 295 #define  CONFIG_STATUS_LED              /* Status LED enabled */
 296 #define  CONFIG_BOARD_SPECIFIC_LED      /* version has board specific leds */
 297
 298 #define CONFIG_SYS_LED_BASE     MPC5XXX_GPT7_ENABLE     /* Timer 7 GPIO */
 299 #ifndef __ASSEMBLY__
 300 typedef unsigned int led_id_t;
 301
 302 #define __led_toggle(_msk) \
 303         do { \
 304                 *((volatile long *) (CONFIG_SYS_LED_BASE)) ^= (_msk); \
 305         } while(0)
 306
 307 #define __led_set(_msk, _st) \
 308         do { \
 309                 if ((_st)) \
 310                         *((volatile long *) (CONFIG_SYS_LED_BASE)) &= ~(_msk); \
 311                 else \
 312                         *((volatile long *) (CONFIG_SYS_LED_BASE)) |= (_msk); \
 313         } while(0)
 314
 315 #define __led_init(_msk, st) \
 316         do { \
 317                 *((volatile long *) (CONFIG_SYS_LED_BASE)) |= 0x34; \
 318         } while(0)
 319 #endif /* __ASSEMBLY__ */
 320
 321 #endif /* __CONFIG_H */