include/configs/v38b.h

   1 /*
   2  * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering,
   3  * wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*
  12  * High Level Configuration Options
  13  * (easy to change)
  14  */
  15 #define CONFIG_MPC5200                  1       /* This is an MPC5200 CPU */
  16 #define CONFIG_V38B                     1       /* ...on V38B board */
  17
  18 #define CONFIG_SYS_TEXT_BASE            0xFF000000
  19
  20 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000        /* ...running at 33.000000MHz */
  21
  22 #define CONFIG_RTC_PCF8563              1       /* has PCF8563 RTC */
  23 #define CONFIG_MPC5200_DDR              1       /* has DDR SDRAM */
  24
  25 #undef CONFIG_HW_WATCHDOG                       /* don't use watchdog */
  26
  27 #define CONFIG_NETCONSOLE               1
  28
  29 #define CONFIG_BOARD_EARLY_INIT_R       1       /* do board-specific init */
  30 #define CONFIG_MISC_INIT_R
  31
  32 #define CONFIG_SYS_XLB_PIPELINING               1       /* gives better performance */
  33
  34 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
  35
  36 /*
  37  * Serial console configuration
  38  */
  39 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
  40 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  41
  42 /*
  43  * DDR
  44  */
  45 #define SDRAM_DDR               1       /* is DDR */
  46 /* Settings for XLB = 132 MHz */
  47 #define SDRAM_MODE              0x018D0000
  48 #define SDRAM_EMODE             0x40090000
  49 #define SDRAM_CONTROL           0x704f0f00
  50 #define SDRAM_CONFIG1           0x73722930
  51 #define SDRAM_CONFIG2           0x47770000
  52 #define SDRAM_TAPDELAY          0x10000000
  53
  54 /*
  55  * PCI - no support
  56  */
  57
  58 /*
  59  * USB
  60  */
  61 #define CONFIG_USB_OHCI
  62 #define CONFIG_USB_CLOCK        0x0001BBBB
  63 #define CONFIG_USB_CONFIG       0x00001000
  64
  65 /*
  66  * BOOTP options
  67  */
  68 #define CONFIG_BOOTP_BOOTFILESIZE
  69 #define CONFIG_BOOTP_BOOTPATH
  70 #define CONFIG_BOOTP_GATEWAY
  71 #define CONFIG_BOOTP_HOSTNAME
  72
  73 /*
  74  * Command line configuration.
  75  */
  76 #define CONFIG_CMD_IDE
  77 #define CONFIG_CMD_IRQ
  78 #define CONFIG_CMD_JFFS2
  79 #define CONFIG_CMD_SDRAM
  80 #define CONFIG_CMD_DATE
  81
  82 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  83
  84 /*
  85  * Boot low with 16 MB Flash
  86  */
  87 #define CONFIG_SYS_LOWBOOT              1
  88 #define CONFIG_SYS_LOWBOOT16            1
  89
  90 /*
  91  * Autobooting
  92  */
  93
  94 #define CONFIG_PREBOOT  "echo;" \
  95         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  96         "echo"
  97
  98 #undef CONFIG_BOOTARGS
  99
 100 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 101         "bootcmd=run net_nfs\0"                                         \
 102         "bootdelay=3\0"                                                 \
 103         "baudrate=115200\0"                                             \
 104         "preboot=echo;echo Type \"run flash_nfs\" to mount root "       \
 105                 "filesystem over NFS; echo\0"                           \
 106         "netdev=eth0\0"                                                 \
 107         "ramargs=setenv bootargs root=/dev/ram rw wdt=off \0"           \
 108         "addip=setenv bootargs $(bootargs) "                            \
 109                 "ip=$(ipaddr):$(serverip):$(gatewayip):"                \
 110                 "$(netmask):$(hostname):$(netdev):off panic=1\0"        \
 111         "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0"            \
 112         "flash_self=run ramargs addip;bootm $(kernel_addr) "            \
 113                 "$(ramdisk_addr)\0"                                     \
 114         "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"     \
 115         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 116                 "nfsroot=$(serverip):$(rootpath) wdt=off\0"             \
 117         "hostname=v38b\0"                                               \
 118         "ethact=FEC\0"                                                  \
 119         "rootpath=/opt/eldk-3.1.1/ppc_6xx\0"                            \
 120         "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; "    \
 121                 "cp.b 200000 ff000000 $(filesize);"                     \
 122                 "prot on ff000000 ff03ffff\0"                           \
 123         "load=tftp 200000 $(u-boot)\0"                                  \
 124         "netmask=255.255.0.0\0"                                         \
 125         "ipaddr=192.168.160.18\0"                                       \
 126         "serverip=192.168.1.1\0"                                        \
 127         "bootfile=/tftpboot/v38b/uImage\0"                              \
 128         "u-boot=/tftpboot/v38b/u-boot.bin\0"                            \
 129         ""
 130
 131 #define CONFIG_BOOTCOMMAND      "run net_nfs"
 132
 133 /*
 134  * IPB Bus clocking configuration.
 135  */
 136 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK                  /* define for 133MHz speed */
 137
 138 /*
 139  * I2C configuration
 140  */
 141 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 142 #define CONFIG_SYS_I2C_MODULE           2       /* Select I2C module #1 or #2 */
 143 #define CONFIG_SYS_I2C_SPEED            100000  /* 100 kHz */
 144 #define CONFIG_SYS_I2C_SLAVE            0x7F
 145
 146 /*
 147  * EEPROM configuration
 148  */
 149 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x */
 150 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 151 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 152 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   70
 153
 154 /*
 155  * RTC configuration
 156  */
 157 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
 158
 159 /*
 160  * Flash configuration - use CFI driver
 161  */
 162 #define CONFIG_SYS_FLASH_CFI            1               /* Flash is CFI conformant */
 163 #define CONFIG_FLASH_CFI_DRIVER 1               /* Use the common driver */
 164 #define CONFIG_SYS_FLASH_CFI_AMD_RESET  1
 165 #define CONFIG_SYS_FLASH_BASE           0xFF000000
 166 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* max num of flash banks */
 167 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 168 #define CONFIG_SYS_FLASH_SIZE           0x01000000      /* 16 MiB */
 169 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* max num of sects on one chip */
 170 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1       /* flash write speed-up */
 171
 172 /*
 173  * Environment settings
 174  */
 175 #define CONFIG_ENV_IS_IN_FLASH  1
 176 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00040000)
 177 #define CONFIG_ENV_SIZE         0x10000
 178 #define CONFIG_ENV_SECT_SIZE    0x10000
 179 #define CONFIG_ENV_OVERWRITE    1
 180
 181 /*
 182  * Memory map
 183  */
 184 #define CONFIG_SYS_MBAR         0xF0000000
 185 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 186 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 187
 188 /* Use SRAM until RAM will be available */
 189 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 190 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE       /* Size of used area in DPRAM */
 191
 192 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 193 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 194
 195 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 196 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 197 #   define CONFIG_SYS_RAMBOOT           1
 198 #endif
 199
 200 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256kB for Monitor */
 201 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128kB for malloc() */
 202 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Linux initial memory map */
 203
 204 /*
 205  * Ethernet configuration
 206  */
 207 #define CONFIG_MPC5xxx_FEC      1
 208 #define CONFIG_MPC5xxx_FEC_MII100
 209 #define CONFIG_PHY_ADDR         0x00
 210 #define CONFIG_MII              1
 211
 212 /*
 213  * GPIO configuration
 214  */
 215 #define CONFIG_SYS_GPS_PORT_CONFIG      0x90001404
 216
 217 /*
 218  * Miscellaneous configurable options
 219  */
 220 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 221 #if defined(CONFIG_CMD_KGDB)
 222 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size */
 223 #else
 224 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 225 #endif
 226 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
 227 #define CONFIG_SYS_MAXARGS              16              /* max number of command args */
 228 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 229
 230 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 231 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM */
 232
 233 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 234
 235 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs */
 236 #if defined(CONFIG_CMD_KGDB)
 237 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 238 #endif
 239
 240 /*
 241  * Various low-level settings
 242  */
 243 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 244 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 245
 246 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 247 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 248 #define CONFIG_SYS_BOOTCS_CFG           0x00047801
 249 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 250 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 251
 252 #define CONFIG_SYS_CS_BURST             0x00000000
 253 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
 254
 255 #define CONFIG_SYS_RESET_ADDRESS        0xff000000
 256
 257 /*
 258  * IDE/ATA (supports IDE harddisk)
 259  */
 260 #undef CONFIG_IDE_8xx_PCCARD            /* Don't use IDE with PC Card Adapter */
 261 #undef CONFIG_IDE_8xx_DIRECT            /* Direct IDE not supported */
 262 #undef CONFIG_IDE_LED                   /* LED for ide not supported */
 263
 264 #define CONFIG_IDE_RESET                /* reset for ide supported */
 265 #define CONFIG_IDE_PREINIT
 266
 267 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus */
 268 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus */
 269
 270 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 271
 272 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 273
 274 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)        /* data I/O offset */
 275
 276 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)    /* normal register accesses offset */
 277
 278 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)        /* alternate registers offset */
 279
 280 #define CONFIG_SYS_ATA_STRIDE           4               /* Interval between registers */
 281
 282 /*
 283  * Status LED
 284  */
 285
 286 #define CONFIG_SYS_LED_BASE     MPC5XXX_GPT7_ENABLE     /* Timer 7 GPIO */
 287 #ifndef __ASSEMBLY__
 288 typedef unsigned int led_id_t;
 289
 290 #define __led_toggle(_msk) \
 291         do { \
 292                 *((volatile long *) (CONFIG_SYS_LED_BASE)) ^= (_msk); \
 293         } while(0)
 294
 295 #define __led_set(_msk, _st) \
 296         do { \
 297                 if ((_st)) \
 298                         *((volatile long *) (CONFIG_SYS_LED_BASE)) &= ~(_msk); \
 299                 else \
 300                         *((volatile long *) (CONFIG_SYS_LED_BASE)) |= (_msk); \
 301         } while(0)
 302
 303 #define __led_init(_msk, st) \
 304         do { \
 305                 *((volatile long *) (CONFIG_SYS_LED_BASE)) |= 0x34; \
 306         } while(0)
 307 #endif /* __ASSEMBLY__ */
 308
 309 #endif /* __CONFIG_H */