include/configs/v38b.h

   1 /*
   2  * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering,
   3  * wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*
  12  * High Level Configuration Options
  13  * (easy to change)
  14  */
  15 #define CONFIG_MPC5200                  1       /* This is an MPC5200 CPU */
  16 #define CONFIG_V38B                     1       /* ...on V38B board */
  17 #define CONFIG_DISPLAY_BOARDINFO
  18
  19 #define CONFIG_SYS_TEXT_BASE            0xFF000000
  20
  21 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000        /* ...running at 33.000000MHz */
  22
  23 #define CONFIG_RTC_PCF8563              1       /* has PCF8563 RTC */
  24 #define CONFIG_MPC5200_DDR              1       /* has DDR SDRAM */
  25
  26 #undef CONFIG_HW_WATCHDOG                       /* don't use watchdog */
  27
  28 #define CONFIG_NETCONSOLE               1
  29
  30 #define CONFIG_BOARD_EARLY_INIT_R       1       /* do board-specific init */
  31 #define CONFIG_BOARD_EARLY_INIT_F       1       /* do board-specific init */
  32 #define CONFIG_MISC_INIT_R
  33
  34 #define CONFIG_SYS_XLB_PIPELINING               1       /* gives better performance */
  35
  36 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
  37
  38 /*
  39  * Serial console configuration
  40  */
  41 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
  42 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
  43 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  44
  45 /*
  46  * DDR
  47  */
  48 #define SDRAM_DDR               1       /* is DDR */
  49 /* Settings for XLB = 132 MHz */
  50 #define SDRAM_MODE              0x018D0000
  51 #define SDRAM_EMODE             0x40090000
  52 #define SDRAM_CONTROL           0x704f0f00
  53 #define SDRAM_CONFIG1           0x73722930
  54 #define SDRAM_CONFIG2           0x47770000
  55 #define SDRAM_TAPDELAY          0x10000000
  56
  57 /*
  58  * PCI - no suport
  59  */
  60 #undef CONFIG_PCI
  61
  62 /*
  63  * Partitions
  64  */
  65 #define CONFIG_MAC_PARTITION    1
  66 #define CONFIG_DOS_PARTITION    1
  67
  68 /*
  69  * USB
  70  */
  71 #define CONFIG_USB_OHCI
  72 #define CONFIG_USB_STORAGE
  73 #define CONFIG_USB_CLOCK        0x0001BBBB
  74 #define CONFIG_USB_CONFIG       0x00001000
  75
  76
  77 /*
  78  * BOOTP options
  79  */
  80 #define CONFIG_BOOTP_BOOTFILESIZE
  81 #define CONFIG_BOOTP_BOOTPATH
  82 #define CONFIG_BOOTP_GATEWAY
  83 #define CONFIG_BOOTP_HOSTNAME
  84
  85
  86 /*
  87  * Command line configuration.
  88  */
  89 #define CONFIG_CMD_FAT
  90 #define CONFIG_CMD_I2C
  91 #define CONFIG_CMD_IDE
  92 #define CONFIG_CMD_PING
  93 #define CONFIG_CMD_DHCP
  94 #define CONFIG_CMD_DIAG
  95 #define CONFIG_CMD_IRQ
  96 #define CONFIG_CMD_JFFS2
  97 #define CONFIG_CMD_MII
  98 #define CONFIG_CMD_SDRAM
  99 #define CONFIG_CMD_DATE
 100 #define CONFIG_CMD_USB
 101 #define CONFIG_CMD_FAT
 102
 103
 104 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
 105
 106 /*
 107  * Boot low with 16 MB Flash
 108  */
 109 #define CONFIG_SYS_LOWBOOT              1
 110 #define CONFIG_SYS_LOWBOOT16            1
 111
 112 /*
 113  * Autobooting
 114  */
 115 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds */
 116
 117 #define CONFIG_PREBOOT  "echo;" \
 118         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 119         "echo"
 120
 121 #undef CONFIG_BOOTARGS
 122
 123 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 124         "bootcmd=run net_nfs\0"                                         \
 125         "bootdelay=3\0"                                                 \
 126         "baudrate=115200\0"                                             \
 127         "preboot=echo;echo Type \"run flash_nfs\" to mount root "       \
 128                 "filesystem over NFS; echo\0"                           \
 129         "netdev=eth0\0"                                                 \
 130         "ramargs=setenv bootargs root=/dev/ram rw wdt=off \0"           \
 131         "addip=setenv bootargs $(bootargs) "                            \
 132                 "ip=$(ipaddr):$(serverip):$(gatewayip):"                \
 133                 "$(netmask):$(hostname):$(netdev):off panic=1\0"        \
 134         "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0"            \
 135         "flash_self=run ramargs addip;bootm $(kernel_addr) "            \
 136                 "$(ramdisk_addr)\0"                                     \
 137         "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"     \
 138         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 139                 "nfsroot=$(serverip):$(rootpath) wdt=off\0"             \
 140         "hostname=v38b\0"                                               \
 141         "ethact=FEC\0"                                                  \
 142         "rootpath=/opt/eldk-3.1.1/ppc_6xx\0"                            \
 143         "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; "    \
 144                 "cp.b 200000 ff000000 $(filesize);"                     \
 145                 "prot on ff000000 ff03ffff\0"                           \
 146         "load=tftp 200000 $(u-boot)\0"                                  \
 147         "netmask=255.255.0.0\0"                                         \
 148         "ipaddr=192.168.160.18\0"                                       \
 149         "serverip=192.168.1.1\0"                                        \
 150         "bootfile=/tftpboot/v38b/uImage\0"                              \
 151         "u-boot=/tftpboot/v38b/u-boot.bin\0"                            \
 152         ""
 153
 154 #define CONFIG_BOOTCOMMAND      "run net_nfs"
 155
 156 /*
 157  * IPB Bus clocking configuration.
 158  */
 159 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK                  /* define for 133MHz speed */
 160
 161 /*
 162  * I2C configuration
 163  */
 164 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 165 #define CONFIG_SYS_I2C_MODULE           2       /* Select I2C module #1 or #2 */
 166 #define CONFIG_SYS_I2C_SPEED            100000  /* 100 kHz */
 167 #define CONFIG_SYS_I2C_SLAVE            0x7F
 168
 169 /*
 170  * EEPROM configuration
 171  */
 172 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x */
 173 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 174 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 175 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   70
 176
 177 /*
 178  * RTC configuration
 179  */
 180 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
 181
 182 /*
 183  * Flash configuration - use CFI driver
 184  */
 185 #define CONFIG_SYS_FLASH_CFI            1               /* Flash is CFI conformant */
 186 #define CONFIG_FLASH_CFI_DRIVER 1               /* Use the common driver */
 187 #define CONFIG_SYS_FLASH_CFI_AMD_RESET  1
 188 #define CONFIG_SYS_FLASH_BASE           0xFF000000
 189 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* max num of flash banks */
 190 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 191 #define CONFIG_SYS_FLASH_SIZE           0x01000000      /* 16 MiB */
 192 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* max num of sects on one chip */
 193 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1       /* flash write speed-up */
 194
 195 /*
 196  * Environment settings
 197  */
 198 #define CONFIG_ENV_IS_IN_FLASH  1
 199 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00040000)
 200 #define CONFIG_ENV_SIZE         0x10000
 201 #define CONFIG_ENV_SECT_SIZE    0x10000
 202 #define CONFIG_ENV_OVERWRITE    1
 203
 204 /*
 205  * Memory map
 206  */
 207 #define CONFIG_SYS_MBAR         0xF0000000
 208 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 209 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 210
 211 /* Use SRAM until RAM will be available */
 212 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 213 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE       /* Size of used area in DPRAM */
 214
 215 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 216 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 217
 218 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 219 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 220 #   define CONFIG_SYS_RAMBOOT           1
 221 #endif
 222
 223 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256kB for Monitor */
 224 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128kB for malloc() */
 225 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Linux initial memory map */
 226
 227 /*
 228  * Ethernet configuration
 229  */
 230 #define CONFIG_MPC5xxx_FEC      1
 231 #define CONFIG_MPC5xxx_FEC_MII100
 232 #define CONFIG_PHY_ADDR         0x00
 233 #define CONFIG_MII              1
 234
 235 /*
 236  * GPIO configuration
 237  */
 238 #define CONFIG_SYS_GPS_PORT_CONFIG      0x90001404
 239
 240 /*
 241  * Miscellaneous configurable options
 242  */
 243 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 244 #if defined(CONFIG_CMD_KGDB)
 245 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size */
 246 #else
 247 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 248 #endif
 249 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
 250 #define CONFIG_SYS_MAXARGS              16              /* max number of command args */
 251 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 252
 253 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 254 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM */
 255
 256 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 257
 258 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs */
 259 #if defined(CONFIG_CMD_KGDB)
 260 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 261 #endif
 262
 263 /*
 264  * Various low-level settings
 265  */
 266 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 267 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 268
 269 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 270 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 271 #define CONFIG_SYS_BOOTCS_CFG           0x00047801
 272 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 273 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 274
 275 #define CONFIG_SYS_CS_BURST             0x00000000
 276 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
 277
 278 #define CONFIG_SYS_RESET_ADDRESS        0xff000000
 279
 280 /*
 281  * IDE/ATA (supports IDE harddisk)
 282  */
 283 #undef CONFIG_IDE_8xx_PCCARD            /* Don't use IDE with PC Card Adapter */
 284 #undef CONFIG_IDE_8xx_DIRECT            /* Direct IDE not supported */
 285 #undef CONFIG_IDE_LED                   /* LED for ide not supported */
 286
 287 #define CONFIG_IDE_RESET                /* reset for ide supported */
 288 #define CONFIG_IDE_PREINIT
 289
 290 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus */
 291 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus */
 292
 293 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 294
 295 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 296
 297 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)        /* data I/O offset */
 298
 299 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)    /* normal register accesses offset */
 300
 301 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)        /* alternate registers offset */
 302
 303 #define CONFIG_SYS_ATA_STRIDE           4               /* Interval between registers */
 304
 305 /*
 306  * Status LED
 307  */
 308 #define  CONFIG_STATUS_LED              /* Status LED enabled */
 309 #define  CONFIG_BOARD_SPECIFIC_LED      /* version has board specific leds */
 310
 311 #define CONFIG_SYS_LED_BASE     MPC5XXX_GPT7_ENABLE     /* Timer 7 GPIO */
 312 #ifndef __ASSEMBLY__
 313 typedef unsigned int led_id_t;
 314
 315 #define __led_toggle(_msk) \
 316         do { \
 317                 *((volatile long *) (CONFIG_SYS_LED_BASE)) ^= (_msk); \
 318         } while(0)
 319
 320 #define __led_set(_msk, _st) \
 321         do { \
 322                 if ((_st)) \
 323                         *((volatile long *) (CONFIG_SYS_LED_BASE)) &= ~(_msk); \
 324                 else \
 325                         *((volatile long *) (CONFIG_SYS_LED_BASE)) |= (_msk); \
 326         } while(0)
 327
 328 #define __led_init(_msk, st) \
 329         do { \
 330                 *((volatile long *) (CONFIG_SYS_LED_BASE)) |= 0x34; \
 331         } while(0)
 332 #endif /* __ASSEMBLY__ */
 333
 334 #endif /* __CONFIG_H */