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1 /*
2 * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 /*
8 * This file contains the configuration parameters for the VCT board
9 * family:
10 *
11 * vct_premium
12 * vct_premium_small
13 * vct_premium_onenand
14 * vct_premium_onenand_small
15 * vct_platinum
16 * vct_platinum_small
17 * vct_platinum_onenand
18 * vct_platinum_onenand_small
19 * vct_platinumavc
20 * vct_platinumavc_small
21 * vct_platinumavc_onenand
22 * vct_platinumavc_onenand_small
23 */
24
25 #ifndef __CONFIG_H
26 #define __CONFIG_H
27
28 #define CPU_CLOCK_RATE 324000000 /* Clock for the MIPS core */
29 #define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2)
30
31 #define CONFIG_SKIP_LOWLEVEL_INIT /* SDRAM is initialized by the bootstrap code */
32
33 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
34 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
35 #define CONFIG_SYS_MALLOC_LEN (1 << 20)
36 #define CONFIG_SYS_BOOTPARAMS_LEN (128 << 10)
37 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000
38
39 #if !defined(CONFIG_VCT_NAND) && !defined(CONFIG_VCT_ONENAND)
40 #define CONFIG_VCT_NOR
41 #endif
42
43 /*
44 * UART
45 */
46 #ifdef CONFIG_VCT_PLATINUMAVC
47 #define UART_1_BASE 0xBDC30000
48 #else
49 #define UART_1_BASE 0xBF89C000
50 #endif
51
52 #define CONFIG_SYS_NS16550_SERIAL
53 #define CONFIG_SYS_NS16550_REG_SIZE -4
54 #define CONFIG_SYS_NS16550_COM1 UART_1_BASE
55 #define CONFIG_CONS_INDEX 1
56 #define CONFIG_SYS_NS16550_CLK 921600
57
58 /*
59 * SDRAM
60 */
61 #define CONFIG_SYS_SDRAM_BASE 0x80000000
62 #define CONFIG_SYS_MBYTES_SDRAM 128
63 #define CONFIG_SYS_MEMTEST_START 0x80200000
64 #define CONFIG_SYS_MEMTEST_END 0x80400000
65 #define CONFIG_SYS_LOAD_ADDR 0x80400000 /* default load address */
66
67 #if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
68 #define CONFIG_NET_RETRY_COUNT 20
69 #endif
70
71 /*
72 * Commands
73 */
74 #if defined(CONFIG_CMD_USB)
75 #define CONFIG_SUPPORT_VFAT
76
77 /*
78 * USB/EHCI
79 */
80 #define CONFIG_USB_EHCI_VCT /* on VCT platform */
81 #define CONFIG_EHCI_MMIO_BIG_ENDIAN
82 #define CONFIG_EHCI_DESC_BIG_ENDIAN
83 #define CONFIG_EHCI_IS_TDI
84 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
85 #endif /* CONFIG_CMD_USB */
86
87 /*
88 * BOOTP options
89 */
90 #define CONFIG_BOOTP_BOOTFILESIZE
91 #define CONFIG_BOOTP_BOOTPATH
92 #define CONFIG_BOOTP_GATEWAY
93 #define CONFIG_BOOTP_HOSTNAME
94 #define CONFIG_BOOTP_SUBNETMASK
95
96 /*
97 * Miscellaneous configurable options
98 */
99 #define CONFIG_SYS_LONGHELP /* undef to save memory */
100 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
101 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
102 #define CONFIG_CMDLINE_EDITING /* add command line history */
103
104 /*
105 * FLASH and environment organization
106 */
107 #if defined(CONFIG_VCT_NOR)
108 #define CONFIG_FLASH_NOT_MEM_MAPPED
109
110 /*
111 * We need special accessor functions for the CFI FLASH driver. This
112 * can be enabled via the CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS option.
113 */
114 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
115
116 /*
117 * For the non-memory-mapped NOR FLASH, we need to define the
118 * NOR FLASH area. This can't be detected via the addr2info()
119 * function, since we check for flash access in the very early
120 * U-Boot code, before the NOR FLASH is detected.
121 */
122 #define CONFIG_FLASH_BASE 0xb0000000
123 #define CONFIG_FLASH_END 0xbfffffff
124
125 /*
126 * CFI driver settings
127 */
128 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
129 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
130 #define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */
131 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */
132
133 #define CONFIG_SYS_FLASH_BASE 0xb0000000
134 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
135 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
136 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
137
138 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
139 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
140
141 #ifdef CONFIG_ENV_IS_IN_FLASH
142 #define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
143 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
144 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
145
146 /* Address and size of Redundant Environment Sector */
147 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
148 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
149 #endif /* CONFIG_ENV_IS_IN_FLASH */
150 #endif /* CONFIG_VCT_NOR */
151
152 #if defined(CONFIG_VCT_ONENAND)
153 #define CONFIG_USE_ONENAND_BOARD_INIT
154 #define CONFIG_SYS_ONENAND_BASE 0x00000000 /* this is not real address */
155 #define CONFIG_SYS_FLASH_BASE 0x00000000
156 #define CONFIG_ENV_ADDR (128 << 10) /* after compr. U-Boot image */
157 #define CONFIG_ENV_SIZE (128 << 10) /* erase size */
158 #endif /* CONFIG_VCT_ONENAND */
159
160 /*
161 * I2C/EEPROM
162 */
163 #define CONFIG_SYS_I2C
164 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
165 #define CONFIG_SYS_I2C_SOFT_SPEED 83000 /* 83 kHz is supposed to work */
166 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7f
167
168 /*
169 * Software (bit-bang) I2C driver configuration
170 */
171 #define CONFIG_SYS_GPIO_I2C_SCL 11
172 #define CONFIG_SYS_GPIO_I2C_SDA 10
173
174 #ifndef __ASSEMBLY__
175 int vct_gpio_dir(int pin, int dir);
176 void vct_gpio_set(int pin, int val);
177 int vct_gpio_get(int pin);
178 #endif
179
180 #define I2C_INIT vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SCL, 1)
181 #define I2C_ACTIVE vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 1)
182 #define I2C_TRISTATE vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 0)
183 #define I2C_READ vct_gpio_get(CONFIG_SYS_GPIO_I2C_SDA)
184 #define I2C_SDA(bit) vct_gpio_set(CONFIG_SYS_GPIO_I2C_SDA, bit)
185 #define I2C_SCL(bit) vct_gpio_set(CONFIG_SYS_GPIO_I2C_SCL, bit)
186 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
187
188 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
189 /* CAT24WC32 */
190 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
191 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
192 /* 32 byte page write mode using*/
193 /* last 5 bits of the address */
194 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
195
196 #define CONFIG_BOOTCOMMAND "run test3"
197
198 /*
199 * UBI configuration
200 */
201 #if defined(CONFIG_VCT_ONENAND)
202 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
203 #define CONFIG_MTD_PARTITIONS
204 #endif
205
206 /*
207 * We need a small, stripped down image to fit into the first 128k OneNAND
208 * erase block (gzipped). This image only needs basic commands for FLASH
209 * (NOR/OneNAND) usage and Linux kernel booting.
210 */
211 #if defined(CONFIG_VCT_SMALL_IMAGE)
212 #undef CONFIG_SYS_I2C_SOFT
213 #undef CONFIG_SOURCE
214 #undef CONFIG_SYS_LONGHELP
215 #undef CONFIG_TIMESTAMP
216 #endif /* CONFIG_VCT_SMALL_IMAGE */
217
218 #endif /* __CONFIG_H */