include/configs/vexpress_aemv8a.h

   1 /*
   2  * Configuration for Versatile Express. Parts were derived from other ARM
   3  *   configurations.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __VEXPRESS_AEMV8A_H
   9 #define __VEXPRESS_AEMV8A_H
  10
  11 /* We use generic board for v8 Versatile Express */
  12 #define CONFIG_SYS_GENERIC_BOARD
  13
  14 #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
  15 #ifndef CONFIG_SEMIHOSTING
  16 #error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING
  17 #endif
  18 #define CONFIG_ARMV8_SWITCH_TO_EL1
  19 #endif
  20
  21 #define CONFIG_REMAKE_ELF
  22
  23 #define CONFIG_SUPPORT_RAW_INITRD
  24
  25 /* Cache Definitions */
  26 #define CONFIG_SYS_DCACHE_OFF
  27 #define CONFIG_SYS_ICACHE_OFF
  28
  29 #define CONFIG_IDENT_STRING             " vexpress_aemv8a"
  30 #define CONFIG_BOOTP_VCI_STRING         "U-boot.armv8.vexpress_aemv8a"
  31
  32 /* Link Definitions */
  33 #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
  34 /* ATF loads u-boot here for BASE_FVP model */
  35 #define CONFIG_SYS_TEXT_BASE            0x88000000
  36 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
  37 #elif CONFIG_TARGET_VEXPRESS64_JUNO
  38 #define CONFIG_SYS_TEXT_BASE            0xe0000000
  39 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
  40 #else
  41 #error "Unknown board variant"
  42 #endif
  43
  44 /* Flat Device Tree Definitions */
  45 #define CONFIG_OF_LIBFDT
  46
  47 /* CS register bases for the original memory map. */
  48 #define V2M_PA_CS0                      0x00000000
  49 #define V2M_PA_CS1                      0x14000000
  50 #define V2M_PA_CS2                      0x18000000
  51 #define V2M_PA_CS3                      0x1c000000
  52 #define V2M_PA_CS4                      0x0c000000
  53 #define V2M_PA_CS5                      0x10000000
  54
  55 #define V2M_PERIPH_OFFSET(x)            (x << 16)
  56 #define V2M_SYSREGS                     (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
  57 #define V2M_SYSCTL                      (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
  58 #define V2M_SERIAL_BUS_PCI              (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
  59
  60 #define V2M_BASE                        0x80000000
  61
  62 /* Common peripherals relative to CS7. */
  63 #define V2M_AACI                        (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
  64 #define V2M_MMCI                        (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
  65 #define V2M_KMI0                        (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
  66 #define V2M_KMI1                        (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
  67
  68 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
  69 #define V2M_UART0                       0x7ff80000
  70 #define V2M_UART1                       0x7ff70000
  71 #else /* Not Juno */
  72 #define V2M_UART0                       (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
  73 #define V2M_UART1                       (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
  74 #define V2M_UART2                       (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
  75 #define V2M_UART3                       (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
  76 #endif
  77
  78 #define V2M_WDT                         (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
  79
  80 #define V2M_TIMER01                     (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
  81 #define V2M_TIMER23                     (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))
  82
  83 #define V2M_SERIAL_BUS_DVI              (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
  84 #define V2M_RTC                         (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))
  85
  86 #define V2M_CF                          (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))
  87
  88 #define V2M_CLCD                        (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))
  89
  90 /* System register offsets. */
  91 #define V2M_SYS_CFGDATA                 (V2M_SYSREGS + 0x0a0)
  92 #define V2M_SYS_CFGCTRL                 (V2M_SYSREGS + 0x0a4)
  93 #define V2M_SYS_CFGSTAT                 (V2M_SYSREGS + 0x0a8)
  94
  95 /* Generic Timer Definitions */
  96 #define COUNTER_FREQUENCY               (0x1800000)     /* 24MHz */
  97
  98 /* Generic Interrupt Controller Definitions */
  99 #ifdef CONFIG_GICV3
 100 #define GICD_BASE                       (0x2f000000)
 101 #define GICR_BASE                       (0x2f100000)
 102 #else
 103
 104 #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
 105 #define GICD_BASE                       (0x2f000000)
 106 #define GICC_BASE                       (0x2c000000)
 107 #elif CONFIG_TARGET_VEXPRESS64_JUNO
 108 #define GICD_BASE                       (0x2C010000)
 109 #define GICC_BASE                       (0x2C02f000)
 110 #else
 111 #error "Unknown board variant"
 112 #endif
 113 #endif /* !CONFIG_GICV3 */
 114
 115 #define CONFIG_SYS_MEMTEST_START        V2M_BASE
 116 #define CONFIG_SYS_MEMTEST_END          (V2M_BASE + 0x80000000)
 117
 118 /* Size of malloc() pool */
 119 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (8 << 20))
 120
 121 /* Ethernet Configuration */
 122 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
 123 /* The real hardware Versatile express uses SMSC9118 */
 124 #define CONFIG_SMC911X                  1
 125 #define CONFIG_SMC911X_32_BIT           1
 126 #define CONFIG_SMC911X_BASE             (0x018000000)
 127 #else
 128 /* The Vexpress64 simulators use SMSC91C111 */
 129 #define CONFIG_SMC91111                 1
 130 #define CONFIG_SMC91111_BASE            (0x01A000000)
 131 #endif
 132
 133 /* PL011 Serial Configuration */
 134 #define CONFIG_PL011_SERIAL
 135 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
 136 #define CONFIG_PL011_CLOCK              7273800
 137 #else
 138 #define CONFIG_PL011_CLOCK              24000000
 139 #endif
 140 #define CONFIG_PL01x_PORTS              {(void *)CONFIG_SYS_SERIAL0, \
 141                                          (void *)CONFIG_SYS_SERIAL1}
 142 #define CONFIG_CONS_INDEX               0
 143
 144 #define CONFIG_BAUDRATE                 115200
 145 #define CONFIG_SYS_SERIAL0              V2M_UART0
 146 #define CONFIG_SYS_SERIAL1              V2M_UART1
 147
 148 /* Command line configuration */
 149 #define CONFIG_MENU
 150 /*#define CONFIG_MENU_SHOW*/
 151 #define CONFIG_CMD_CACHE
 152 #define CONFIG_CMD_BDI
 153 #define CONFIG_CMD_BOOTI
 154 #define CONFIG_CMD_UNZIP
 155 #define CONFIG_CMD_DHCP
 156 #define CONFIG_CMD_PXE
 157 #define CONFIG_CMD_ENV
 158 #define CONFIG_CMD_IMI
 159 #define CONFIG_CMD_LOADB
 160 #define CONFIG_CMD_MEMORY
 161 #define CONFIG_CMD_MII
 162 #define CONFIG_CMD_NET
 163 #define CONFIG_CMD_PING
 164 #define CONFIG_CMD_SAVEENV
 165 #define CONFIG_CMD_RUN
 166 #define CONFIG_CMD_BOOTD
 167 #define CONFIG_CMD_ECHO
 168 #define CONFIG_CMD_SOURCE
 169 #define CONFIG_CMD_FAT
 170 #define CONFIG_DOS_PARTITION
 171
 172 /* BOOTP options */
 173 #define CONFIG_BOOTP_BOOTFILESIZE
 174 #define CONFIG_BOOTP_BOOTPATH
 175 #define CONFIG_BOOTP_GATEWAY
 176 #define CONFIG_BOOTP_HOSTNAME
 177 #define CONFIG_BOOTP_PXE
 178 #define CONFIG_BOOTP_PXE_CLIENTARCH     0x100
 179
 180 /* Miscellaneous configurable options */
 181 #define CONFIG_SYS_LOAD_ADDR            (V2M_BASE + 0x10000000)
 182
 183 /* Physical Memory Map */
 184 #define CONFIG_NR_DRAM_BANKS            1
 185 #define PHYS_SDRAM_1                    (V2M_BASE)      /* SDRAM Bank #1 */
 186 #define PHYS_SDRAM_1_SIZE               0x80000000      /* 2048 MB */
 187 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 188
 189 /* Initial environment variables */
 190 #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
 191 #define CONFIG_EXTRA_ENV_SETTINGS       \
 192                                 "kernel_name=uImage\0"          \
 193                                 "kernel_addr=0x80000000\0"      \
 194                                 "initrd_name=ramdisk.img\0"     \
 195                                 "initrd_addr=0x88000000\0"      \
 196                                 "fdt_name=devtree.dtb\0"        \
 197                                 "fdt_addr=0x83000000\0"         \
 198                                 "fdt_high=0xffffffffffffffff\0" \
 199                                 "initrd_high=0xffffffffffffffff\0"
 200
 201 #define CONFIG_BOOTARGS         "console=ttyAMA0 earlyprintk=pl011,"\
 202                                 "0x1c090000 debug user_debug=31 "\
 203                                 "loglevel=9"
 204
 205 #define CONFIG_BOOTCOMMAND      "smhload ${kernel_name} ${kernel_addr}; " \
 206                                 "smhload ${fdt_name} $fdt_addr; " \
 207                                 "smhload ${initrd_name} $initrd_addr initrd_end; " \
 208                                 "fdt addr $fdt_addr; fdt resize; " \
 209                                 "fdt chosen $initrd_addr $initrd_end; " \
 210                                 "bootm $kernel_addr - $fdt_addr"
 211
 212 #define CONFIG_BOOTDELAY                1
 213
 214 #else
 215 #error "Unknown board variant"
 216 #endif
 217
 218 /* Do not preserve environment */
 219 #define CONFIG_ENV_IS_NOWHERE           1
 220 #define CONFIG_ENV_SIZE                 0x1000
 221
 222 /* Monitor Command Prompt */
 223 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 224 #define CONFIG_SYS_PROMPT               "VExpress64# "
 225 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 226                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 227 #define CONFIG_SYS_HUSH_PARSER
 228 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 229 #define CONFIG_SYS_LONGHELP
 230 #define CONFIG_CMDLINE_EDITING
 231 #define CONFIG_SYS_MAXARGS              64      /* max command args */
 232
 233 /* Flash memory is available on the Juno board only */
 234 #ifndef CONFIG_TARGET_VEXPRESS64_JUNO
 235 #define CONFIG_SYS_NO_FLASH
 236 #else
 237 #define CONFIG_CMD_FLASH
 238 #define CONFIG_SYS_FLASH_CFI            1
 239 #define CONFIG_FLASH_CFI_DRIVER         1
 240 #define CONFIG_SYS_FLASH_BASE           0x08000000
 241 #define CONFIG_SYS_FLASH_SIZE           0x04000000 /* 64 MiB */
 242 #define CONFIG_SYS_MAX_FLASH_BANKS      2
 243
 244 /* Timeout values in ticks */
 245 #define CONFIG_SYS_FLASH_ERASE_TOUT     (2 * CONFIG_SYS_HZ) /* Erase Timeout */
 246 #define CONFIG_SYS_FLASH_WRITE_TOUT     (2 * CONFIG_SYS_HZ) /* Write Timeout */
 247
 248 /* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
 249 #define CONFIG_SYS_MAX_FLASH_SECT       259             /* Max sectors */
 250 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
 251 #define CONFIG_SYS_FLASH_PROTECTION     /* The devices have real protection */
 252 #define CONFIG_SYS_FLASH_EMPTY_INFO     /* flinfo indicates empty blocks */
 253
 254 #endif
 255
 256 #endif /* __VEXPRESS_AEMV8A_H */