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1 /*
2 * Configuration for Versatile Express. Parts were derived from other ARM
3 * configurations.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #ifndef __VEXPRESS_AEMV8A_H
9 #define __VEXPRESS_AEMV8A_H
10
11 #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
12 #ifndef CONFIG_SEMIHOSTING
13 #error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING
14 #endif
15 #define CONFIG_ARMV8_SWITCH_TO_EL1
16 #endif
17
18 #define CONFIG_REMAKE_ELF
19
20 #define CONFIG_SUPPORT_RAW_INITRD
21
22 /* Link Definitions */
23 #if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \
24 defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM)
25 /* ATF loads u-boot here for BASE_FVP model */
26 #define CONFIG_SYS_TEXT_BASE 0x88000000
27 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
28 #elif CONFIG_TARGET_VEXPRESS64_JUNO
29 #define CONFIG_SYS_TEXT_BASE 0xe0000000
30 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
31 #endif
32
33 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
34
35 /* CS register bases for the original memory map. */
36 #define V2M_PA_CS0 0x00000000
37 #define V2M_PA_CS1 0x14000000
38 #define V2M_PA_CS2 0x18000000
39 #define V2M_PA_CS3 0x1c000000
40 #define V2M_PA_CS4 0x0c000000
41 #define V2M_PA_CS5 0x10000000
42
43 #define V2M_PERIPH_OFFSET(x) (x << 16)
44 #define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
45 #define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
46 #define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
47
48 #define V2M_BASE 0x80000000
49
50 /* Common peripherals relative to CS7. */
51 #define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
52 #define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
53 #define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
54 #define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
55
56 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
57 #define V2M_UART0 0x7ff80000
58 #define V2M_UART1 0x7ff70000
59 #else /* Not Juno */
60 #define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
61 #define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
62 #define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
63 #define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
64 #endif
65
66 #define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
67
68 #define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
69 #define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))
70
71 #define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
72 #define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))
73
74 #define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))
75
76 #define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))
77
78 /* System register offsets. */
79 #define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
80 #define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
81 #define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
82
83 /* Generic Timer Definitions */
84 #define COUNTER_FREQUENCY (0x1800000) /* 24MHz */
85
86 /* Generic Interrupt Controller Definitions */
87 #ifdef CONFIG_GICV3
88 #define GICD_BASE (0x2f000000)
89 #define GICR_BASE (0x2f100000)
90 #else
91
92 #if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \
93 defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM)
94 #define GICD_BASE (0x2f000000)
95 #define GICC_BASE (0x2c000000)
96 #elif CONFIG_TARGET_VEXPRESS64_JUNO
97 #define GICD_BASE (0x2C010000)
98 #define GICC_BASE (0x2C02f000)
99 #endif
100 #endif /* !CONFIG_GICV3 */
101
102 /* Size of malloc() pool */
103 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20))
104
105 /* Ethernet Configuration */
106 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
107 /* The real hardware Versatile express uses SMSC9118 */
108 #define CONFIG_SMC911X 1
109 #define CONFIG_SMC911X_32_BIT 1
110 #define CONFIG_SMC911X_BASE (0x018000000)
111 #else
112 /* The Vexpress64 simulators use SMSC91C111 */
113 #define CONFIG_SMC91111 1
114 #define CONFIG_SMC91111_BASE (0x01A000000)
115 #endif
116
117 /* PL011 Serial Configuration */
118 #define CONFIG_BAUDRATE 115200
119 #define CONFIG_CONS_INDEX 0
120 #define CONFIG_PL01X_SERIAL
121 #define CONFIG_PL011_SERIAL
122 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
123 #define CONFIG_PL011_CLOCK 7273800
124 #else
125 #define CONFIG_PL011_CLOCK 24000000
126 #endif
127
128 /* Command line configuration */
129 #define CONFIG_MENU
130 /*#define CONFIG_MENU_SHOW*/
131 #define CONFIG_CMD_UNZIP
132 #define CONFIG_CMD_PXE
133 #define CONFIG_CMD_ENV
134 #define CONFIG_DOS_PARTITION
135
136 /* BOOTP options */
137 #define CONFIG_BOOTP_BOOTFILESIZE
138 #define CONFIG_BOOTP_BOOTPATH
139 #define CONFIG_BOOTP_GATEWAY
140 #define CONFIG_BOOTP_HOSTNAME
141 #define CONFIG_BOOTP_PXE
142
143 /* Miscellaneous configurable options */
144 #define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000)
145
146 /* Physical Memory Map */
147 #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */
148 /* Top 16MB reserved for secure world use */
149 #define DRAM_SEC_SIZE 0x01000000
150 #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE
151 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
152
153 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
154 #define CONFIG_NR_DRAM_BANKS 2
155 #define PHYS_SDRAM_2 (0x880000000)
156 #define PHYS_SDRAM_2_SIZE 0x180000000
157 #else
158 #define CONFIG_NR_DRAM_BANKS 1
159 #endif
160
161 /* Enable memtest */
162 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
163 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
164
165 /* Initial environment variables */
166 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
167 /*
168 * Defines where the kernel and FDT exist in NOR flash and where it will
169 * be copied into DRAM
170 */
171 #define CONFIG_EXTRA_ENV_SETTINGS \
172 "kernel_name=norkern\0" \
173 "kernel_alt_name=Image\0" \
174 "kernel_addr=0x80080000\0" \
175 "initrd_name=ramdisk.img\0" \
176 "initrd_addr=0x84000000\0" \
177 "fdtfile=board.dtb\0" \
178 "fdt_alt_name=juno\0" \
179 "fdt_addr=0x83000000\0" \
180 "fdt_high=0xffffffffffffffff\0" \
181 "initrd_high=0xffffffffffffffff\0" \
182
183 /* Assume we boot with root on the first partition of a USB stick */
184 #define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 " \
185 "root=/dev/sda2 rw " \
186 "rootwait "\
187 "earlyprintk=pl011,0x7ff80000 debug "\
188 "user_debug=31 "\
189 "androidboot.hardware=juno "\
190 "loglevel=9"
191
192 /* Copy the kernel and FDT to DRAM memory and boot */
193 #define CONFIG_BOOTCOMMAND "afs load ${kernel_name} ${kernel_addr} ; " \
194 "if test $? -eq 1; then "\
195 " echo Loading ${kernel_alt_name} instead of "\
196 "${kernel_name}; "\
197 " afs load ${kernel_alt_name} ${kernel_addr};"\
198 "fi ; "\
199 "afs load ${fdtfile} ${fdt_addr} ; " \
200 "if test $? -eq 1; then "\
201 " echo Loading ${fdt_alt_name} instead of "\
202 "${fdtfile}; "\
203 " afs load ${fdt_alt_name} ${fdt_addr}; "\
204 "fi ; "\
205 "fdt addr ${fdt_addr}; fdt resize; " \
206 "if afs load ${initrd_name} ${initrd_addr} ; "\
207 "then "\
208 " setenv initrd_param ${initrd_addr}; "\
209 " else setenv initrd_param -; "\
210 "fi ; " \
211 "booti ${kernel_addr} ${initrd_param} ${fdt_addr}"
212
213
214 #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP
215 #define CONFIG_EXTRA_ENV_SETTINGS \
216 "kernel_name=Image\0" \
217 "kernel_addr=0x80080000\0" \
218 "initrd_name=ramdisk.img\0" \
219 "initrd_addr=0x88000000\0" \
220 "fdtfile=devtree.dtb\0" \
221 "fdt_addr=0x83000000\0" \
222 "fdt_high=0xffffffffffffffff\0" \
223 "initrd_high=0xffffffffffffffff\0"
224
225 #define CONFIG_BOOTARGS "console=ttyAMA0 earlyprintk=pl011,"\
226 "0x1c090000 debug user_debug=31 "\
227 "loglevel=9"
228
229 #define CONFIG_BOOTCOMMAND "smhload ${kernel_name} ${kernel_addr}; " \
230 "smhload ${fdtfile} ${fdt_addr}; " \
231 "smhload ${initrd_name} ${initrd_addr} "\
232 "initrd_end; " \
233 "fdt addr ${fdt_addr}; fdt resize; " \
234 "fdt chosen ${initrd_addr} ${initrd_end}; " \
235 "booti $kernel_addr - $fdt_addr"
236
237
238 #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM
239 #define CONFIG_EXTRA_ENV_SETTINGS \
240 "kernel_addr=0x80080000\0" \
241 "initrd_addr=0x84000000\0" \
242 "fdt_addr=0x83000000\0" \
243 "fdt_high=0xffffffffffffffff\0" \
244 "initrd_high=0xffffffffffffffff\0"
245
246 #define CONFIG_BOOTARGS "console=ttyAMA0 earlyprintk=pl011,"\
247 "0x1c090000 debug user_debug=31 "\
248 "androidboot.hardware=fvpbase "\
249 "root=/dev/vda2 rw "\
250 "rootwait "\
251 "loglevel=9"
252
253 #define CONFIG_BOOTCOMMAND "booti $kernel_addr $initrd_addr $fdt_addr"
254
255
256 #endif
257
258 /* Monitor Command Prompt */
259 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
260 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
261 sizeof(CONFIG_SYS_PROMPT) + 16)
262 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
263 #define CONFIG_SYS_LONGHELP
264 #define CONFIG_CMDLINE_EDITING
265 #define CONFIG_SYS_MAXARGS 64 /* max command args */
266
267 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
268 #define CONFIG_SYS_FLASH_BASE 0x08000000
269 /* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */
270 #define CONFIG_SYS_MAX_FLASH_SECT 259
271 /* Store environment at top of flash in the same location as blank.img */
272 /* in the Juno firmware. */
273 #define CONFIG_ENV_ADDR 0x0BFC0000
274 #define CONFIG_ENV_SECT_SIZE 0x00010000
275 #else
276 #define CONFIG_SYS_FLASH_BASE 0x0C000000
277 /* 256 x 256KiB sectors */
278 #define CONFIG_SYS_MAX_FLASH_SECT 256
279 /* Store environment at top of flash */
280 #define CONFIG_ENV_ADDR 0x0FFC0000
281 #define CONFIG_ENV_SECT_SIZE 0x00040000
282 #endif
283
284 #define CONFIG_SYS_FLASH_CFI 1
285 #define CONFIG_FLASH_CFI_DRIVER 1
286 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
287 #define CONFIG_SYS_MAX_FLASH_BANKS 1
288
289 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
290 #define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */
291 #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
292 #define FLASH_MAX_SECTOR_SIZE 0x00040000
293 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
294 #define CONFIG_ENV_IS_IN_FLASH 1
295
296 #endif /* __VEXPRESS_AEMV8A_H */