include/configs/vision2.h

   1 /*
   2  * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
   3  *
   4  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   5  *
   6  * Configuration settings for the MX51-3Stack Freescale board.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27
  28 #define CONFIG_MX51     /* in a mx51 */
  29 #define CONFIG_SYS_TEXT_BASE    0x97800000
  30
  31 #include <asm/arch/imx-regs.h>
  32
  33 #define CONFIG_SYS_MX5_HCLK     24000000
  34 #define CONFIG_SYS_MX5_CLK32            32768
  35 #define CONFIG_DISPLAY_CPUINFO
  36 #define CONFIG_DISPLAY_BOARDINFO
  37
  38 #define CONFIG_CMDLINE_TAG      /* enable passing of ATAGs */
  39 #define CONFIG_SETUP_MEMORY_TAGS
  40 #define CONFIG_INITRD_TAG
  41 #define CONFIG_BOARD_LATE_INIT
  42
  43 #ifndef MACH_TYPE_TTC_VISION2
  44 #define MACH_TYPE_TTC_VISION2   2775
  45 #endif
  46 #define CONFIG_MACH_TYPE        MACH_TYPE_TTC_VISION2
  47
  48 /*
  49  * Size of malloc() pool
  50  */
  51 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
  52
  53 /*
  54  * Hardware drivers
  55  */
  56 #define CONFIG_MXC_UART
  57 #define CONFIG_MXC_UART_BASE    UART3_BASE
  58 #define CONFIG_MXC_GPIO
  59 #define CONFIG_MXC_SPI
  60 #define CONFIG_HW_WATCHDOG
  61
  62  /*
  63  * SPI Configs
  64  * */
  65 #define CONFIG_FSL_SF
  66 #define CONFIG_CMD_SF
  67
  68 #define CONFIG_SPI_FLASH
  69 #define CONFIG_SPI_FLASH_STMICRO
  70
  71 /*
  72  * Use gpio 4 pin 25 as chip select for SPI flash
  73  * This corresponds to gpio 121
  74  */
  75 #define CONFIG_SF_DEFAULT_CS    (1 | (121 << 8))
  76 #define CONFIG_SF_DEFAULT_MODE   SPI_MODE_0
  77 #define CONFIG_SF_DEFAULT_SPEED  25000000
  78
  79 #define CONFIG_ENV_SPI_CS       (1 | (121 << 8))
  80 #define CONFIG_ENV_SPI_BUS      0
  81 #define CONFIG_ENV_SPI_MAX_HZ   25000000
  82 #define CONFIG_ENV_SPI_MODE     SPI_MODE_0
  83
  84 #define CONFIG_ENV_OFFSET       (6 * 64 * 1024)
  85 #define CONFIG_ENV_SECT_SIZE    (1 * 64 * 1024)
  86 #define CONFIG_ENV_SIZE         (4 * 1024)
  87
  88 #define CONFIG_FSL_ENV_IN_SF
  89 #define CONFIG_ENV_IS_IN_SPI_FLASH
  90
  91 /* PMIC Controller */
  92 #define CONFIG_PMIC
  93 #define CONFIG_PMIC_SPI
  94 #define CONFIG_PMIC_FSL
  95 #define CONFIG_FSL_PMIC_BUS     0
  96 #define CONFIG_FSL_PMIC_CS      0
  97 #define CONFIG_FSL_PMIC_CLK     2500000
  98 #define CONFIG_FSL_PMIC_MODE    SPI_MODE_0
  99 #define CONFIG_FSL_PMIC_BITLEN  32
 100 #define CONFIG_RTC_MC13XXX
 101
 102 /*
 103  * MMC Configs
 104  */
 105 #define CONFIG_FSL_ESDHC
 106 #ifdef CONFIG_FSL_ESDHC
 107 #define CONFIG_SYS_FSL_ESDHC_ADDR       (0x70004000)
 108 #define CONFIG_SYS_FSL_ESDHC_NUM        1
 109
 110 #define CONFIG_MMC
 111
 112 #define CONFIG_CMD_MMC
 113 #define CONFIG_GENERIC_MMC
 114 #define CONFIG_CMD_FAT
 115 #define CONFIG_DOS_PARTITION
 116 #endif
 117
 118 #define CONFIG_CMD_DATE
 119
 120 /*
 121  * Eth Configs
 122  */
 123 #define CONFIG_HAS_ETH1
 124 #define CONFIG_MII
 125 #define CONFIG_DISCOVER_PHY
 126
 127 #define CONFIG_FEC_MXC
 128 #define IMX_FEC_BASE                            FEC_BASE_ADDR
 129 #define CONFIG_FEC_MXC_PHYADDR          0x1F
 130
 131 #define CONFIG_CMD_PING
 132 #define CONFIG_CMD_MII
 133 #define CONFIG_CMD_NET
 134
 135 /* allow to overwrite serial and ethaddr */
 136 #define CONFIG_ENV_OVERWRITE
 137 #define CONFIG_CONS_INDEX                       3
 138 #define CONFIG_BAUDRATE                         115200
 139
 140 /***********************************************************
 141  * Command definition
 142  ***********************************************************/
 143
 144 #include <config_cmd_default.h>
 145
 146 #define CONFIG_CMD_SPI
 147 #undef CONFIG_CMD_IMLS
 148
 149 #define CONFIG_BOOTDELAY        3
 150
 151 #define CONFIG_LOADADDR 0x90800000      /* loadaddr env var */
 152
 153 #define CONFIG_EXTRA_ENV_SETTINGS       \
 154                 "netdev=eth0\0"         \
 155                 "loadaddr=0x90800000\0"
 156
 157 /*
 158  * Miscellaneous configurable options
 159  */
 160 #define CONFIG_SYS_LONGHELP
 161 #define CONFIG_SYS_PROMPT               "Vision II U-boot > "
 162 #define CONFIG_AUTO_COMPLETE
 163 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 164
 165 /* Print Buffer Size */
 166 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 167                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 168 #define CONFIG_SYS_MAXARGS              64      /* max number of command args */
 169 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 170
 171 #define CONFIG_SYS_MEMTEST_START        0x90000000
 172 #define CONFIG_SYS_MEMTEST_END          0x10000
 173
 174 #define CONFIG_SYS_LOAD_ADDR            CONFIG_LOADADDR
 175
 176 #define CONFIG_SYS_HZ                   1000
 177 #define CONFIG_CMDLINE_EDITING
 178 #define CONFIG_SYS_HUSH_PARSER
 179
 180 /*
 181  * Stack sizes
 182  */
 183 #define CONFIG_STACKSIZE                (128 * 1024)    /* regular stack */
 184
 185 /*
 186  * Physical Memory Map
 187  */
 188 #define CONFIG_NR_DRAM_BANKS            2
 189 #define PHYS_SDRAM_1                    CSD0_BASE_ADDR
 190 #define PHYS_SDRAM_1_SIZE               (256 * 1024 * 1024)
 191 #define PHYS_SDRAM_2                    CSD1_BASE_ADDR
 192 #define PHYS_SDRAM_2_SIZE               (256 * 1024 * 1024)
 193 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 194 #define CONFIG_SYS_INIT_RAM_ADDR        IRAM_BASE_ADDR
 195 #define CONFIG_SYS_INIT_RAM_SIZE        IRAM_SIZE
 196
 197 #define CONFIG_SYS_INIT_SP_OFFSET \
 198         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 199 #define CONFIG_SYS_INIT_SP_ADDR \
 200         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 201
 202 #define CONFIG_BOARD_EARLY_INIT_F
 203
 204 /* 166 MHz DDR RAM */
 205 #define CONFIG_SYS_DDR_CLKSEL           0
 206 #define CONFIG_SYS_CLKTL_CBCDR          0x19239100
 207
 208 #define CONFIG_SYS_NO_FLASH
 209
 210 /*
 211  * Framebuffer and LCD
 212  */
 213 #define CONFIG_PREBOOT
 214 #define CONFIG_VIDEO
 215 #define CONFIG_VIDEO_MX5
 216 #define CONFIG_CFB_CONSOLE
 217 #define CONFIG_VGA_AS_SINGLE_DEVICE
 218 #define CONFIG_VIDEO_BMP_RLE8
 219 #define CONFIG_SPLASH_SCREEN
 220 #define CONFIG_CMD_BMP
 221 #define CONFIG_BMP_16BPP
 222
 223 #endif                          /* __CONFIG_H */