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Move defaults from config_cmd_default.h to Kconfig
[people/ms/u-boot.git] / include / configs / vision2.h
1 /*
2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
3 *
4 * (C) Copyright 2009 Freescale Semiconductor, Inc.
5 *
6 * Configuration settings for the MX51-3Stack Freescale board.
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14
15 #define CONFIG_MX51 /* in a mx51 */
16 #define CONFIG_SYS_TEXT_BASE 0x97800000
17
18 #include <asm/arch/imx-regs.h>
19
20 #define CONFIG_DISPLAY_CPUINFO
21 #define CONFIG_DISPLAY_BOARDINFO
22
23 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
24 #define CONFIG_SETUP_MEMORY_TAGS
25 #define CONFIG_INITRD_TAG
26 #define CONFIG_BOARD_LATE_INIT
27
28 #ifndef MACH_TYPE_TTC_VISION2
29 #define MACH_TYPE_TTC_VISION2 2775
30 #endif
31 #define CONFIG_MACH_TYPE MACH_TYPE_TTC_VISION2
32
33 /*
34 * Size of malloc() pool
35 */
36 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
37
38 /*
39 * Hardware drivers
40 */
41 #define CONFIG_MXC_UART
42 #define CONFIG_MXC_UART_BASE UART3_BASE
43 #define CONFIG_MXC_GPIO
44 #define CONFIG_MXC_SPI
45 #define CONFIG_HW_WATCHDOG
46
47 /*
48 * SPI Configs
49 * */
50 #define CONFIG_FSL_SF
51 #define CONFIG_CMD_SF
52
53 #define CONFIG_SPI_FLASH_STMICRO
54
55 /*
56 * Use gpio 4 pin 25 as chip select for SPI flash
57 * This corresponds to gpio 121
58 */
59 #define CONFIG_SF_DEFAULT_CS 1
60 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
61 #define CONFIG_SF_DEFAULT_SPEED 25000000
62
63 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
64 #define CONFIG_ENV_SPI_BUS 0
65 #define CONFIG_ENV_SPI_MAX_HZ 25000000
66 #define CONFIG_ENV_SPI_MODE SPI_MODE_0
67
68 #define CONFIG_ENV_OFFSET (6 * 64 * 1024)
69 #define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024)
70 #define CONFIG_ENV_SIZE (4 * 1024)
71
72 #define CONFIG_FSL_ENV_IN_SF
73 #define CONFIG_ENV_IS_IN_SPI_FLASH
74
75 /* PMIC Controller */
76 #define CONFIG_POWER
77 #define CONFIG_POWER_SPI
78 #define CONFIG_POWER_FSL
79 #define CONFIG_FSL_PMIC_BUS 0
80 #define CONFIG_FSL_PMIC_CS 0
81 #define CONFIG_FSL_PMIC_CLK 2500000
82 #define CONFIG_FSL_PMIC_MODE SPI_MODE_0
83 #define CONFIG_FSL_PMIC_BITLEN 32
84 #define CONFIG_RTC_MC13XXX
85
86 /*
87 * MMC Configs
88 */
89 #define CONFIG_FSL_ESDHC
90 #ifdef CONFIG_FSL_ESDHC
91 #define CONFIG_SYS_FSL_ESDHC_ADDR (0x70004000)
92 #define CONFIG_SYS_FSL_ESDHC_NUM 1
93
94 #define CONFIG_MMC
95
96 #define CONFIG_CMD_MMC
97 #define CONFIG_GENERIC_MMC
98 #define CONFIG_CMD_FAT
99 #define CONFIG_DOS_PARTITION
100 #endif
101
102 #define CONFIG_CMD_DATE
103
104 /*
105 * Eth Configs
106 */
107 #define CONFIG_HAS_ETH1
108 #define CONFIG_MII
109
110 #define CONFIG_FEC_MXC
111 #define IMX_FEC_BASE FEC_BASE_ADDR
112 #define CONFIG_FEC_MXC_PHYADDR 0x1F
113
114 #define CONFIG_CMD_PING
115 #define CONFIG_CMD_MII
116
117 /* allow to overwrite serial and ethaddr */
118 #define CONFIG_ENV_OVERWRITE
119 #define CONFIG_CONS_INDEX 3
120 #define CONFIG_BAUDRATE 115200
121
122 /***********************************************************
123 * Command definition
124 ***********************************************************/
125
126 #define CONFIG_CMD_SPI
127
128 #define CONFIG_BOOTDELAY 3
129
130 #define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
131
132 #define CONFIG_EXTRA_ENV_SETTINGS \
133 "netdev=eth0\0" \
134 "loadaddr=0x90800000\0"
135
136 /*
137 * Miscellaneous configurable options
138 */
139 #define CONFIG_SYS_LONGHELP
140 #define CONFIG_SYS_PROMPT "Vision II U-boot > "
141 #define CONFIG_AUTO_COMPLETE
142 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
143
144 /* Print Buffer Size */
145 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
146 sizeof(CONFIG_SYS_PROMPT) + 16)
147 #define CONFIG_SYS_MAXARGS 64 /* max number of command args */
148 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
149
150 #define CONFIG_SYS_MEMTEST_START 0x90000000
151 #define CONFIG_SYS_MEMTEST_END 0x10000
152
153 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
154
155 #define CONFIG_CMDLINE_EDITING
156 #define CONFIG_SYS_HUSH_PARSER
157
158 /*
159 * Physical Memory Map
160 */
161 #define CONFIG_NR_DRAM_BANKS 2
162 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
163 #define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
164 #define PHYS_SDRAM_2 CSD1_BASE_ADDR
165 #define PHYS_SDRAM_2_SIZE (256 * 1024 * 1024)
166 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
167 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
168 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
169
170 #define CONFIG_SYS_INIT_SP_OFFSET \
171 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
172 #define CONFIG_SYS_INIT_SP_ADDR \
173 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
174
175 #define CONFIG_BOARD_EARLY_INIT_F
176
177 /* 166 MHz DDR RAM */
178 #define CONFIG_SYS_DDR_CLKSEL 0
179 #define CONFIG_SYS_CLKTL_CBCDR 0x19239100
180 #define CONFIG_SYS_MAIN_PWR_ON
181
182 #define CONFIG_SYS_NO_FLASH
183
184 /*
185 * Framebuffer and LCD
186 */
187 #define CONFIG_PREBOOT
188 #define CONFIG_VIDEO
189 #define CONFIG_VIDEO_IPUV3
190 #define CONFIG_CFB_CONSOLE
191 #define CONFIG_VGA_AS_SINGLE_DEVICE
192 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
193 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
194 #define CONFIG_VIDEO_BMP_RLE8
195 #define CONFIG_SPLASH_SCREEN
196 #define CONFIG_CMD_BMP
197 #define CONFIG_BMP_16BPP
198 #define CONFIG_IPUV3_CLK 133000000
199
200 #endif /* __CONFIG_H */