include/configs/vme8349.h

   1 /*
   2  * esd vme8349 U-Boot configuration file
   3  * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
   4  *
   5  * (C) Copyright 2006-2010
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  *
   8  * reinhard.arlt@esd-electronics.de
   9  * Based on the MPC8349EMDS config.
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 /*
  15  * vme8349 board configuration file.
  16  */
  17
  18 #ifndef __CONFIG_H
  19 #define __CONFIG_H
  20
  21 /*
  22  * Top level Makefile configuration choices
  23  */
  24 #ifdef CONFIG_CADDY2
  25 #define VME_CADDY2
  26 #endif
  27
  28 /*
  29  * High Level Configuration Options
  30  */
  31 #define CONFIG_E300             1       /* E300 Family */
  32 #define CONFIG_MPC834x          1       /* MPC834x family */
  33 #define CONFIG_MPC8349          1       /* MPC8349 specific */
  34 #define CONFIG_VME8349          1       /* ESD VME8349 board specific */
  35
  36 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  37
  38 #define CONFIG_MISC_INIT_R
  39
  40 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */
  41 #undef CONFIG_MPC83XX_PCI2              /* support for 2nd PCI controller */
  42
  43 #define CONFIG_PCI_66M
  44 #ifdef CONFIG_PCI_66M
  45 #define CONFIG_83XX_CLKIN       66000000        /* in Hz */
  46 #else
  47 #define CONFIG_83XX_CLKIN       33000000        /* in Hz */
  48 #endif
  49
  50 #ifndef CONFIG_SYS_CLK_FREQ
  51 #ifdef CONFIG_PCI_66M
  52 #define CONFIG_SYS_CLK_FREQ     66000000
  53 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_4X1
  54 #else
  55 #define CONFIG_SYS_CLK_FREQ     33000000
  56 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_8X1
  57 #endif
  58 #endif
  59
  60 #define CONFIG_SYS_IMMR         0xE0000000
  61
  62 #undef CONFIG_SYS_DRAM_TEST                     /* memory test, takes time */
  63 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  64 #define CONFIG_SYS_MEMTEST_END          0x00100000
  65
  66 /*
  67  * DDR Setup
  68  */
  69 #define CONFIG_DDR_ECC                  /* only for ECC DDR module */
  70 #define CONFIG_DDR_ECC_CMD              /* use DDR ECC user commands */
  71 #define CONFIG_SPD_EEPROM
  72 #define SPD_EEPROM_ADDRESS              0x54
  73 #define CONFIG_SYS_READ_SPD             vme8349_read_spd
  74 #define CONFIG_SYS_83XX_DDR_USES_CS0    /* esd; Fsl board uses CS2/CS3 */
  75
  76 /*
  77  * 32-bit data path mode.
  78  *
  79  * Please note that using this mode for devices with the real density of 64-bit
  80  * effectively reduces the amount of available memory due to the effect of
  81  * wrapping around while translating address to row/columns, for example in the
  82  * 256MB module the upper 128MB get aliased with contents of the lower
  83  * 128MB); normally this define should be used for devices with real 32-bit
  84  * data path.
  85  */
  86 #undef CONFIG_DDR_32BIT
  87
  88 #define CONFIG_SYS_DDR_BASE             0x00000000      /* DDR is sys memory*/
  89 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  90 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  91 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
  92                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
  93 #define CONFIG_DDR_2T_TIMING
  94 #define CONFIG_SYS_DDRCDR               (DDRCDR_DHC_EN \
  95                                         | DDRCDR_ODT \
  96                                         | DDRCDR_Q_DRN)
  97                                         /* 0x80080001 */
  98
  99 /*
 100  * FLASH on the Local Bus
 101  */
 102 #define CONFIG_SYS_FLASH_CFI
 103 #define CONFIG_FLASH_CFI_DRIVER                         /* use the CFI driver */
 104 #ifdef VME_CADDY2
 105 #define CONFIG_SYS_FLASH_BASE           0xffc00000      /* start of FLASH   */
 106 #define CONFIG_SYS_FLASH_SIZE           4               /* flash size in MB */
 107 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | \
 108                                          BR_PS_16 |     /*  16bit */ \
 109                                          BR_MS_GPCM |   /*  MSEL = GPCM */ \
 110                                          BR_V)          /* valid */
 111
 112 #define CONFIG_SYS_OR0_PRELIM           (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 113                                         | OR_GPCM_XAM \
 114                                         | OR_GPCM_CSNT \
 115                                         | OR_GPCM_ACS_DIV2 \
 116                                         | OR_GPCM_XACS \
 117                                         | OR_GPCM_SCY_15 \
 118                                         | OR_GPCM_TRLX_SET \
 119                                         | OR_GPCM_EHTR_SET \
 120                                         | OR_GPCM_EAD)
 121                                         /* 0xffc06ff7 */
 122 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 123 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_4MB)
 124 #else
 125 #define CONFIG_SYS_FLASH_BASE           0xf8000000      /* start of FLASH   */
 126 #define CONFIG_SYS_FLASH_SIZE           128             /* flash size in MB */
 127 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | \
 128                                          BR_PS_16 |     /*  16bit */ \
 129                                          BR_MS_GPCM |   /*  MSEL = GPCM */ \
 130                                          BR_V)          /* valid */
 131
 132 #define CONFIG_SYS_OR0_PRELIM           (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 133                                         | OR_GPCM_XAM \
 134                                         | OR_GPCM_CSNT \
 135                                         | OR_GPCM_ACS_DIV2 \
 136                                         | OR_GPCM_XACS \
 137                                         | OR_GPCM_SCY_15 \
 138                                         | OR_GPCM_TRLX_SET \
 139                                         | OR_GPCM_EHTR_SET \
 140                                         | OR_GPCM_EAD)
 141                                         /* 0xf8006ff7 */
 142 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 143 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_128MB)
 144 #endif
 145 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
 146
 147 #define CONFIG_SYS_WINDOW1_BASE         0xf0000000
 148 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_WINDOW1_BASE \
 149                                         | BR_PS_32 \
 150                                         | BR_MS_GPCM \
 151                                         | BR_V)
 152                                         /* 0xF0001801 */
 153 #define CONFIG_SYS_OR1_PRELIM           (OR_AM_256KB \
 154                                         | OR_GPCM_SETA)
 155                                         /* 0xfffc0208 */
 156 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_WINDOW1_BASE
 157 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_256KB)
 158
 159 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 160 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device*/
 161
 162 #undef CONFIG_SYS_FLASH_CHECKSUM
 163 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase TO (ms) */
 164 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write TO (ms) */
 165
 166 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 167
 168 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 169 #define CONFIG_SYS_RAMBOOT
 170 #else
 171 #undef CONFIG_SYS_RAMBOOT
 172 #endif
 173
 174 #define CONFIG_SYS_INIT_RAM_LOCK        1
 175 #define CONFIG_SYS_INIT_RAM_ADDR        0xF7000000      /* Initial RAM addr */
 176 #define CONFIG_SYS_INIT_RAM_SIZE                0x1000          /* size */
 177
 178 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 179                                          GENERATED_GBL_DATA_SIZE)
 180 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 181
 182 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB */
 183 #define CONFIG_SYS_MALLOC_LEN           (256 * 1024)    /* Malloc size */
 184
 185 /*
 186  * Local Bus LCRR and LBCR regs
 187  *    LCRR:  no DLL bypass, Clock divider is 4
 188  * External Local Bus rate is
 189  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 190  */
 191 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 192 #define CONFIG_SYS_LBC_LBCR     0x00000000
 193
 194 #undef CONFIG_SYS_LB_SDRAM      /* if board has SDRAM on local bus */
 195
 196 /*
 197  * Serial Port
 198  */
 199 #define CONFIG_CONS_INDEX       1
 200 #define CONFIG_SYS_NS16550_SERIAL
 201 #define CONFIG_SYS_NS16550_REG_SIZE     1
 202 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 203
 204 #define CONFIG_SYS_BAUDRATE_TABLE  \
 205                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 206
 207 #define CONFIG_SYS_NS16550_COM1         (CONFIG_SYS_IMMR + 0x4500)
 208 #define CONFIG_SYS_NS16550_COM2         (CONFIG_SYS_IMMR + 0x4600)
 209
 210 #define CONFIG_CMDLINE_EDITING          /* add command line history     */
 211 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
 212
 213 /* I2C */
 214 #define CONFIG_SYS_I2C
 215 #define CONFIG_SYS_I2C_FSL
 216 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 217 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 218 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 219 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 220 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 221 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 222 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 223 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
 224
 225 #define CONFIG_SYS_I2C_8574_ADDR2       0x20    /* I2C1, PCF8574 */
 226
 227 /* TSEC */
 228 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 229 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 230 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 231 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
 232
 233 /*
 234  * General PCI
 235  * Addresses are mapped 1-1.
 236  */
 237 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 238 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 239 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 240 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 241 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 242 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 243 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 244 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 245 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 246
 247 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 248 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 249 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 250 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 251 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 252 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 253 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 254 #define CONFIG_SYS_PCI2_IO_PHYS         0xE2100000
 255 #define CONFIG_SYS_PCI2_IO_SIZE         0x00100000      /* 1M */
 256
 257 #if defined(CONFIG_PCI)
 258
 259 #define PCI_64BIT
 260 #define PCI_ONE_PCI1
 261 #if defined(PCI_64BIT)
 262 #undef PCI_ALL_PCI1
 263 #undef PCI_TWO_PCI1
 264 #undef PCI_ONE_PCI1
 265 #endif
 266
 267 #ifndef VME_CADDY2
 268 #endif
 269 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 270
 271 #undef CONFIG_EEPRO100
 272 #undef CONFIG_TULIP
 273
 274 #if !defined(CONFIG_PCI_PNP)
 275         #define PCI_ENET0_IOADDR        0xFIXME
 276         #define PCI_ENET0_MEMADDR       0xFIXME
 277         #define PCI_IDSEL_NUMBER        0xFIXME
 278 #endif
 279
 280 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 281 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 282
 283 #endif  /* CONFIG_PCI */
 284
 285 /*
 286  * TSEC configuration
 287  */
 288 #ifdef VME_CADDY2
 289 #else
 290 #define CONFIG_TSEC_ENET                /* TSEC ethernet support */
 291 #endif
 292
 293 #if defined(CONFIG_TSEC_ENET)
 294
 295 #define CONFIG_GMII                     /* MII PHY management */
 296 #define CONFIG_TSEC1
 297 #define CONFIG_TSEC1_NAME       "TSEC0"
 298 #define CONFIG_TSEC2
 299 #define CONFIG_TSEC2_NAME       "TSEC1"
 300 #define CONFIG_PHY_M88E1111
 301 #define TSEC1_PHY_ADDR          0x08
 302 #define TSEC2_PHY_ADDR          0x10
 303 #define TSEC1_PHYIDX            0
 304 #define TSEC2_PHYIDX            0
 305 #define TSEC1_FLAGS             TSEC_GIGABIT
 306 #define TSEC2_FLAGS             TSEC_GIGABIT
 307
 308 /* Options are: TSEC[0-1] */
 309 #define CONFIG_ETHPRIME         "TSEC0"
 310
 311 #endif  /* CONFIG_TSEC_ENET */
 312
 313 /*
 314  * Environment
 315  */
 316 #ifndef CONFIG_SYS_RAMBOOT
 317         #define CONFIG_ENV_IS_IN_FLASH
 318         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0xc0000)
 319         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 320         #define CONFIG_ENV_SIZE         0x2000
 321
 322 /* Address and size of Redundant Environment Sector     */
 323 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 324 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 325
 326 #else
 327         #define CONFIG_SYS_NO_FLASH             /* Flash is not usable now */
 328         #define CONFIG_ENV_IS_NOWHERE           /* Store ENV in memory only */
 329         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 330         #define CONFIG_ENV_SIZE         0x2000
 331 #endif
 332
 333 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 334 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 335
 336 /*
 337  * BOOTP options
 338  */
 339 #define CONFIG_BOOTP_BOOTFILESIZE
 340 #define CONFIG_BOOTP_BOOTPATH
 341 #define CONFIG_BOOTP_GATEWAY
 342 #define CONFIG_BOOTP_HOSTNAME
 343
 344 /*
 345  * Command line configuration.
 346  */
 347 #define CONFIG_CMD_DATE
 348 #define CONFIG_SYS_RTC_BUS_NUM  0x01
 349 #define CONFIG_SYS_I2C_RTC_ADDR 0x32
 350 #define CONFIG_RTC_RX8025
 351 #define CONFIG_CMD_TSI148
 352
 353 #if defined(CONFIG_PCI)
 354     #define CONFIG_CMD_PCI
 355 #endif
 356
 357 #if defined(CONFIG_SYS_RAMBOOT)
 358     #undef CONFIG_CMD_ENV
 359 #endif
 360
 361 /* Pass Ethernet MAC to VxWorks */
 362 #define CONFIG_SYS_VXWORKS_MAC_PTR      0x000043f0
 363
 364 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 365
 366 /*
 367  * Miscellaneous configurable options
 368  */
 369 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 370 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 371
 372 #if defined(CONFIG_CMD_KGDB)
 373         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
 374 #else
 375         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 376 #endif
 377
 378 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 379 #define CONFIG_SYS_MAXARGS      16              /* max num of command args */
 380 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Argument Buf Size */
 381
 382 /*
 383  * For booting Linux, the board info and command line data
 384  * have to be in the first 256 MB of memory, since this is
 385  * the maximum mapped by the Linux kernel during initialization.
 386  */
 387 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Init Memory map for Linux*/
 388
 389 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 390
 391 #define CONFIG_SYS_HRCW_LOW (\
 392         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 393         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 394         HRCWL_CSB_TO_CLKIN |\
 395         HRCWL_VCO_1X2 |\
 396         HRCWL_CORE_TO_CSB_2X1)
 397
 398 #if defined(PCI_64BIT)
 399 #define CONFIG_SYS_HRCW_HIGH (\
 400         HRCWH_PCI_HOST |\
 401         HRCWH_64_BIT_PCI |\
 402         HRCWH_PCI1_ARBITER_ENABLE |\
 403         HRCWH_PCI2_ARBITER_DISABLE |\
 404         HRCWH_CORE_ENABLE |\
 405         HRCWH_FROM_0X00000100 |\
 406         HRCWH_BOOTSEQ_DISABLE |\
 407         HRCWH_SW_WATCHDOG_DISABLE |\
 408         HRCWH_ROM_LOC_LOCAL_16BIT |\
 409         HRCWH_TSEC1M_IN_GMII |\
 410         HRCWH_TSEC2M_IN_GMII)
 411 #else
 412 #define CONFIG_SYS_HRCW_HIGH (\
 413         HRCWH_PCI_HOST |\
 414         HRCWH_32_BIT_PCI |\
 415         HRCWH_PCI1_ARBITER_ENABLE |\
 416         HRCWH_PCI2_ARBITER_ENABLE |\
 417         HRCWH_CORE_ENABLE |\
 418         HRCWH_FROM_0X00000100 |\
 419         HRCWH_BOOTSEQ_DISABLE |\
 420         HRCWH_SW_WATCHDOG_DISABLE |\
 421         HRCWH_ROM_LOC_LOCAL_16BIT |\
 422         HRCWH_TSEC1M_IN_GMII |\
 423         HRCWH_TSEC2M_IN_GMII)
 424 #endif
 425
 426 /* System IO Config */
 427 #define CONFIG_SYS_SICRH 0
 428 #define CONFIG_SYS_SICRL SICRL_LDP_A
 429
 430 #define CONFIG_SYS_HID0_INIT    0x000000000
 431 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 432                                  HID0_ENABLE_INSTRUCTION_CACHE)
 433
 434 #define CONFIG_SYS_HID2         HID2_HBE
 435
 436 #define CONFIG_SYS_GPIO1_PRELIM
 437 #define CONFIG_SYS_GPIO1_DIR    0x00100000
 438 #define CONFIG_SYS_GPIO1_DAT    0x00100000
 439
 440 #define CONFIG_SYS_GPIO2_PRELIM
 441 #define CONFIG_SYS_GPIO2_DIR    0x78900000
 442 #define CONFIG_SYS_GPIO2_DAT    0x70100000
 443
 444 #define CONFIG_HIGH_BATS                /* High BATs supported */
 445
 446 /* DDR @ 0x00000000 */
 447 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 448                                  BATL_MEMCOHERENCE)
 449 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
 450                                  BATU_VS | BATU_VP)
 451
 452 /* PCI @ 0x80000000 */
 453 #ifdef CONFIG_PCI
 454 #define CONFIG_PCI_INDIRECT_BRIDGE
 455 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \
 456                                  BATL_MEMCOHERENCE)
 457 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
 458                                  BATU_VS | BATU_VP)
 459 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \
 460                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 461 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
 462                                  BATU_VS | BATU_VP)
 463 #else
 464 #define CONFIG_SYS_IBAT1L       (0)
 465 #define CONFIG_SYS_IBAT1U       (0)
 466 #define CONFIG_SYS_IBAT2L       (0)
 467 #define CONFIG_SYS_IBAT2U       (0)
 468 #endif
 469
 470 #ifdef CONFIG_MPC83XX_PCI2
 471 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \
 472                                  BATL_MEMCOHERENCE)
 473 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
 474                                  BATU_VS | BATU_VP)
 475 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \
 476                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 477 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
 478                                  BATU_VS | BATU_VP)
 479 #else
 480 #define CONFIG_SYS_IBAT3L       (0)
 481 #define CONFIG_SYS_IBAT3U       (0)
 482 #define CONFIG_SYS_IBAT4L       (0)
 483 #define CONFIG_SYS_IBAT4U       (0)
 484 #endif
 485
 486 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
 487 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 488                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 489 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR | BATU_BL_256M | \
 490                                  BATU_VS | BATU_VP)
 491
 492 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE)
 493 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 494
 495 #if (CONFIG_SYS_DDR_SIZE == 512)
 496 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
 497                                  BATL_PP_RW | BATL_MEMCOHERENCE)
 498 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
 499                                  BATU_BL_256M | BATU_VS | BATU_VP)
 500 #else
 501 #define CONFIG_SYS_IBAT7L       (0)
 502 #define CONFIG_SYS_IBAT7U       (0)
 503 #endif
 504
 505 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 506 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 507 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 508 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 509 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 510 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 511 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 512 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 513 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 514 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 515 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 516 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 517 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 518 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 519 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 520 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 521
 522 #if defined(CONFIG_CMD_KGDB)
 523 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 524 #endif
 525
 526 /*
 527  * Environment Configuration
 528  */
 529 #define CONFIG_ENV_OVERWRITE
 530
 531 #if defined(CONFIG_TSEC_ENET)
 532 #define CONFIG_HAS_ETH0
 533 #define CONFIG_HAS_ETH1
 534 #endif
 535
 536 #define CONFIG_HOSTNAME         VME8349
 537 #define CONFIG_ROOTPATH         "/tftpboot/rootfs"
 538 #define CONFIG_BOOTFILE         "uImage"
 539
 540 #define CONFIG_LOADADDR         800000  /* def location for tftp and bootm */
 541
 542 #undef  CONFIG_BOOTARGS                 /* boot command will set bootargs */
 543
 544 #define CONFIG_BAUDRATE  9600
 545
 546 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 547         "netdev=eth0\0"                                                 \
 548         "hostname=vme8349\0"                                            \
 549         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 550                 "nfsroot=${serverip}:${rootpath}\0"                     \
 551         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 552         "addip=setenv bootargs ${bootargs} "                            \
 553                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 554                 ":${hostname}:${netdev}:off panic=1\0"                  \
 555         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 556         "flash_nfs=run nfsargs addip addtty;"                           \
 557                 "bootm ${kernel_addr}\0"                                \
 558         "flash_self=run ramargs addip addtty;"                          \
 559                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 560         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 561                 "bootm\0"                                               \
 562         "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0"              \
 563         "update=protect off fff00000 fff3ffff; "                        \
 564                 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
 565         "upd=run load update\0"                                         \
 566         "fdtaddr=780000\0"                                              \
 567         "fdtfile=vme8349.dtb\0"                                         \
 568         ""
 569
 570 #define CONFIG_NFSBOOTCOMMAND                                           \
 571         "setenv bootargs root=/dev/nfs rw "                             \
 572                 "nfsroot=$serverip:$rootpath "                          \
 573                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 574                                                         "$netdev:off "  \
 575                 "console=$consoledev,$baudrate $othbootargs;"           \
 576         "tftp $loadaddr $bootfile;"                                     \
 577         "tftp $fdtaddr $fdtfile;"                                       \
 578         "bootm $loadaddr - $fdtaddr"
 579
 580 #define CONFIG_RAMBOOTCOMMAND                                           \
 581         "setenv bootargs root=/dev/ram rw "                             \
 582                 "console=$consoledev,$baudrate $othbootargs;"           \
 583         "tftp $ramdiskaddr $ramdiskfile;"                               \
 584         "tftp $loadaddr $bootfile;"                                     \
 585         "tftp $fdtaddr $fdtfile;"                                       \
 586         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 587
 588 #define CONFIG_BOOTCOMMAND      "run flash_self"
 589
 590 #ifndef __ASSEMBLY__
 591 int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
 592                      unsigned char *buffer, int len);
 593 #endif
 594
 595 #endif  /* __CONFIG_H */