include/configs/walnut.h

   1 /*
   2  * (C) Copyright 2000-2005
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  21 #define CONFIG_WALNUT           1       /* ...on a WALNUT board         */
  22                                         /* ...or on a SYCAMORE board    */
  23
  24 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  25
  26 /*
  27  * Include common defines/options for all AMCC eval boards
  28  */
  29 #define CONFIG_HOSTNAME         walnut
  30 #include "amcc-common.h"
  31
  32 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  33
  34 #define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
  35
  36 /*
  37  * Default environment variables
  38  */
  39 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  40         CONFIG_AMCC_DEF_ENV                                             \
  41         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
  42         CONFIG_AMCC_DEF_ENV_PPC_OLD                                     \
  43         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
  44         "kernel_addr=fff80000\0"                                        \
  45         "ramdisk_addr=fff80000\0"                                       \
  46         ""
  47
  48 #define CONFIG_PHY_ADDR         1       /* PHY address                  */
  49 #define CONFIG_HAS_ETH0         1
  50
  51 #define CONFIG_RTC_DS174x       1       /* use DS1743 RTC in Walnut     */
  52
  53 /*
  54  * Commands additional to the ones defined in amcc-common.h
  55  */
  56 #define CONFIG_CMD_DATE
  57 #define CONFIG_CMD_PCI
  58 #define CONFIG_CMD_SDRAM
  59
  60 #define CONFIG_SPD_EEPROM      1       /* use SPD EEPROM for setup    */
  61
  62 /*
  63  * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
  64  * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
  65  * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
  66  * The Linux BASE_BAUD define should match this configuration.
  67  *    baseBaud = cpuClock/(uartDivisor*16)
  68  * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
  69  * set Linux BASE_BAUD to 403200.
  70  */
  71 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  72 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* external serial clock */
  73 #undef  CONFIG_SYS_405_UART_ERRATA_59          /* 405GP/CR Rev. D silicon */
  74 #define CONFIG_SYS_BASE_BAUD        691200
  75
  76 /*-----------------------------------------------------------------------
  77  * I2C stuff
  78  *-----------------------------------------------------------------------
  79  */
  80 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
  81
  82 #define CONFIG_SYS_I2C_EEPROM_ADDR      (0xa8>>1)
  83 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  84 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  85 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
  86
  87 /*-----------------------------------------------------------------------
  88  * PCI stuff
  89  *-----------------------------------------------------------------------
  90  */
  91 #define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
  92 #define PCI_HOST_FORCE  1               /* configure as pci host        */
  93 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
  94
  95 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
  96 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
  97                                         /* resource configuration       */
  98 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
  99
 100 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8   /* AMCC */
 101 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever */
 102 #define CONFIG_SYS_PCI_PTM1LA   0x00000000      /* point to sdram               */
 103 #define CONFIG_SYS_PCI_PTM1MS   0x80000001      /* 2GB, enable hard-wired to 1  */
 104 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000       /* Host: use this pci address   */
 105 #define CONFIG_SYS_PCI_PTM2LA   0x00000000      /* disabled                     */
 106 #define CONFIG_SYS_PCI_PTM2MS   0x00000000      /* disabled                     */
 107 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000       /* Host: use this pci address   */
 108
 109 /*-----------------------------------------------------------------------
 110  * Start addresses for the final memory configuration
 111  * (Set up by the startup code)
 112  */
 113 #define CONFIG_SYS_FLASH_BASE           0xFFF80000
 114
 115 /*
 116  * Define here the location of the environment variables (FLASH or NVRAM).
 117  * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
 118  *       supported for backward compatibility.
 119  */
 120 #if 1
 121 #define CONFIG_ENV_IS_IN_FLASH  1       /* use FLASH for environment vars       */
 122 #else
 123 #define CONFIG_ENV_IS_IN_NVRAM  1       /* use NVRAM for environment vars       */
 124 #endif
 125
 126 /*-----------------------------------------------------------------------
 127  * FLASH organization
 128  */
 129 #define FLASH_BASE0_PRELIM      CONFIG_SYS_FLASH_BASE   /* FLASH bank #0                */
 130 #define FLASH_BASE1_PRELIM      0               /* FLASH bank #1                */
 131
 132 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 133 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 134
 135 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 136 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 137
 138 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 139
 140 #define CONFIG_SYS_FLASH_ADDR0          0x5555
 141 #define CONFIG_SYS_FLASH_ADDR1          0x2aaa
 142 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned char
 143
 144 #ifdef CONFIG_ENV_IS_IN_FLASH
 145 #define CONFIG_ENV_SECT_SIZE    0x10000         /* size of one complete sector  */
 146 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 147 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 148
 149 /* Address and size of Redundant Environment Sector     */
 150 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 151 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 152 #endif /* CONFIG_ENV_IS_IN_FLASH */
 153
 154 /*-----------------------------------------------------------------------
 155  * NVRAM organization
 156  */
 157 #define CONFIG_SYS_NVRAM_BASE_ADDR      0xf0000000      /* NVRAM base address   */
 158 #define CONFIG_SYS_NVRAM_SIZE           0x1ff8          /* NVRAM size   */
 159
 160 #ifdef CONFIG_ENV_IS_IN_NVRAM
 161 #define CONFIG_ENV_SIZE         0x1000          /* Size of Environment vars     */
 162 #define CONFIG_ENV_ADDR         \
 163         (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)      /* Env  */
 164 #endif
 165
 166 /*-----------------------------------------------------------------------
 167  * External Bus Controller (EBC) Setup
 168  */
 169
 170 /* Memory Bank 0 (Flash Bank 0) initialization                                  */
 171 #define CONFIG_SYS_EBC_PB0AP            0x9B015480
 172 #define CONFIG_SYS_EBC_PB0CR            0xFFF18000  /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit  */
 173
 174 #define CONFIG_SYS_EBC_PB1AP            0x02815480
 175 #define CONFIG_SYS_EBC_PB1CR            0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 176
 177 #define CONFIG_SYS_EBC_PB2AP            0x04815A80
 178 #define CONFIG_SYS_EBC_PB2CR            0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit  */
 179
 180 #define CONFIG_SYS_EBC_PB3AP            0x01815280
 181 #define CONFIG_SYS_EBC_PB3CR            0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit  */
 182
 183 #define CONFIG_SYS_EBC_PB7AP            0x01815280
 184 #define CONFIG_SYS_EBC_PB7CR            0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit  */
 185
 186 /*-----------------------------------------------------------------------
 187  * External peripheral base address
 188  *-----------------------------------------------------------------------
 189  */
 190 #define CONFIG_SYS_KEY_REG_BASE_ADDR    0xF0100000
 191 #define CONFIG_SYS_IR_REG_BASE_ADDR     0xF0200000
 192 #define CONFIG_SYS_FPGA_REG_BASE_ADDR   0xF0300000
 193
 194 /*-----------------------------------------------------------------------
 195  * Definitions for initial stack pointer and data area
 196  */
 197 #define CONFIG_SYS_INIT_DCACHE_CS       4       /* use cs # 4 for data cache memory    */
 198
 199 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000  /* inside of SDRAM                     */
 200 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000  /* Size of used area in RAM            */
 201 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 202 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 203
 204 /*-----------------------------------------------------------------------
 205  * Definitions for Serial Presence Detect EEPROM address
 206  * (to get SDRAM settings)
 207  */
 208 #define SPD_EEPROM_ADDRESS      0x50
 209
 210 #endif  /* __CONFIG_H */