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1 /*
2 * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
3 *
4 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
5 *
6 * Configuration for the woodburn board.
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11 #ifndef __WOODBURN_COMMON_CONFIG_H
12 #define __WOODBURN_COMMON_CONFIG_H
13
14 #include <asm/arch/imx-regs.h>
15
16 /* High Level Configuration Options */
17 #define CONFIG_MX35
18 #define CONFIG_MX35_HCLK_FREQ 24000000
19 #define CONFIG_SYS_FSL_CLK
20
21 #define CONFIG_SYS_DCACHE_OFF
22
23 #define CONFIG_MACH_TYPE MACH_TYPE_FLEA3
24
25 /* This is required to setup the ESDC controller */
26
27 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
28 #define CONFIG_REVISION_TAG
29 #define CONFIG_SETUP_MEMORY_TAGS
30 #define CONFIG_INITRD_TAG
31
32 /*
33 * Size of malloc() pool
34 */
35 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
36
37 /*
38 * Hardware drivers
39 */
40 #define CONFIG_SYS_I2C
41 #define CONFIG_SYS_I2C_MXC
42 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
43 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
44 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
45 #define CONFIG_SYS_SPD_BUS_NUM 0
46 #define CONFIG_MXC_SPI
47 #define CONFIG_MXC_GPIO
48
49 /* PMIC Controller */
50 #define CONFIG_POWER
51 #define CONFIG_POWER_I2C
52 #define CONFIG_POWER_FSL
53 #define CONFIG_POWER_FSL_MC13892
54 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
55 #define CONFIG_RTC_MC13XXX
56
57 /* mmc driver */
58 #define CONFIG_FSL_ESDHC
59 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
60 #define CONFIG_SYS_FSL_ESDHC_NUM 1
61
62 /*
63 * UART (console)
64 */
65 #define CONFIG_MXC_UART
66 #define CONFIG_MXC_UART_BASE UART1_BASE
67
68 /* allow to overwrite serial and ethaddr */
69 #define CONFIG_ENV_OVERWRITE
70 #define CONFIG_CONS_INDEX 1
71 #define CONFIG_BAUDRATE 115200
72
73 /*
74 * Command definition
75 */
76 #define CONFIG_CMD_DATE
77 #define CONFIG_BOOTP_SUBNETMASK
78 #define CONFIG_BOOTP_GATEWAY
79 #define CONFIG_BOOTP_DNS
80
81 #define CONFIG_CMD_NAND
82
83 #define CONFIG_MXC_GPIO
84
85 #define CONFIG_NET_RETRY_COUNT 100
86
87
88 #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
89
90 /*
91 * Ethernet on SOC (FEC)
92 */
93 #define CONFIG_FEC_MXC
94 #define IMX_FEC_BASE FEC_BASE_ADDR
95 #define CONFIG_PHYLIB
96 #define CONFIG_PHY_MICREL
97 #define CONFIG_FEC_MXC_PHYADDR 0x1
98
99 #define CONFIG_MII
100 #define CONFIG_DISCOVER_PHY
101
102 #define CONFIG_ARP_TIMEOUT 200UL
103
104 /*
105 * Miscellaneous configurable options
106 */
107 #define CONFIG_SYS_LONGHELP /* undef to save memory */
108 #define CONFIG_CMDLINE_EDITING
109
110 #define CONFIG_AUTO_COMPLETE
111 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
112 /* Print Buffer Size */
113 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
114 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
115 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
116
117 #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
118 #define CONFIG_SYS_MEMTEST_END 0x10000
119
120 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
121
122 /*
123 * Stack sizes
124 *
125 * The stack sizes are set up in start.S using the settings below
126 */
127 #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
128
129 /*
130 * Physical Memory Map
131 */
132 #define CONFIG_NR_DRAM_BANKS 1
133 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
134 #define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
135
136 #define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR
137
138 #define CONFIG_SYS_GBL_DATA_OFFSET (LOW_LEVEL_SRAM_STACK - \
139 IRAM_BASE_ADDR - \
140 GENERATED_GBL_DATA_SIZE)
141 #define CONFIG_SYS_INIT_SP_ADDR (IRAM_BASE_ADDR + \
142 CONFIG_SYS_GBL_DATA_OFFSET)
143
144 /*
145 * MTD Command for mtdparts
146 */
147 #define CONFIG_CMD_MTDPARTS
148 #define CONFIG_MTD_DEVICE
149 #define CONFIG_FLASH_CFI_MTD
150 #define CONFIG_MTD_PARTITIONS
151 #define MTDIDS_DEFAULT "nand0=mxc_nand,nor0=physmap-flash.0"
152 #define MTDPARTS_DEFAULT "mtdparts=mxc_nand:50m(root1)," \
153 "32m(rootfb)," \
154 "64m(pcache)," \
155 "64m(app1)," \
156 "10m(app2),-(spool);" \
157 "physmap-flash.0:512k(u-boot),64k(env1)," \
158 "64k(env2),3776k(kernel1),3776k(kernel2)"
159
160 /*
161 * FLASH and environment organization
162 */
163 #define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
164 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
165 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
166 /* Monitor at beginning of flash */
167 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
168 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
169
170 #define CONFIG_ENV_SECT_SIZE (128 * 1024)
171 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
172
173 /* Address and size of Redundant Environment Sector */
174 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
175 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
176
177 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
178 CONFIG_SYS_MONITOR_LEN)
179
180 #define CONFIG_ENV_IS_IN_FLASH
181
182 /*
183 * CFI FLASH driver setup
184 */
185 #define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
186 #define CONFIG_FLASH_CFI_DRIVER
187
188 /* A non-standard buffered write algorithm */
189 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* faster */
190 #define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
191
192 /*
193 * NAND FLASH driver setup
194 */
195 #define CONFIG_NAND_MXC
196 #define CONFIG_NAND_MXC_V1_1
197 #define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
198 #define CONFIG_SYS_MAX_NAND_DEVICE 1
199 #define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
200 #define CONFIG_MXC_NAND_HWECC
201 #define CONFIG_SYS_NAND_LARGEPAGE
202
203 #if 0
204 #define CONFIG_MTD_DEBUG
205 #define CONFIG_MTD_DEBUG_VERBOSE 7
206 #endif
207 #define CONFIG_SYS_NAND_ONFI_DETECTION
208
209 /*
210 * Default environment and default scripts
211 * to update uboot and load kernel
212 */
213
214 #define CONFIG_HOSTNAME woodburn
215 #define CONFIG_EXTRA_ENV_SETTINGS \
216 "netdev=eth0\0" \
217 "nfsargs=setenv bootargs root=/dev/nfs rw " \
218 "nfsroot=${serverip}:${rootpath}\0" \
219 "ramargs=setenv bootargs root=/dev/ram rw\0" \
220 "addip_sta=setenv bootargs ${bootargs} " \
221 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
222 ":${hostname}:${netdev}:off panic=1\0" \
223 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
224 "addip=if test -n ${ipdyn};then run addip_dyn;" \
225 "else run addip_sta;fi\0" \
226 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
227 "addtty=setenv bootargs ${bootargs}" \
228 " console=ttymxc0,${baudrate}\0" \
229 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
230 "loadaddr=80800000\0" \
231 "kernel_addr_r=80800000\0" \
232 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
233 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
234 "ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0" \
235 "flash_self=run ramargs addip addtty addmtd addmisc;" \
236 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
237 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
238 "bootm ${kernel_addr}\0" \
239 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
240 "run nfsargs addip addtty addmtd addmisc;" \
241 "bootm ${kernel_addr_r}\0" \
242 "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
243 "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
244 "net_self=if run net_self_load;then " \
245 "run ramargs addip addtty addmtd addmisc;" \
246 "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
247 "else echo Images not loades;fi\0" \
248 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
249 "load=tftp ${loadaddr} ${u-boot}\0" \
250 "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
251 "update=protect off ${uboot_addr} +80000;" \
252 "erase ${uboot_addr} +80000;" \
253 "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
254 "upd=if run load;then echo Updating u-boot;if run update;" \
255 "then echo U-Boot updated;" \
256 "else echo Error updating u-boot !;" \
257 "echo Board without bootloader !!;" \
258 "fi;" \
259 "else echo U-Boot not downloaded..exiting;fi\0" \
260 "bootcmd=run net_nfs\0"
261
262 #endif /* __CONFIG_H */