include/configs/work_92105.h

   1 /*
   2  * WORK Microwave work_92105 board configuration file
   3  *
   4  * (C) Copyright 2014  DENX Software Engineering GmbH
   5  * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __CONFIG_WORK_92105_H__
  11 #define __CONFIG_WORK_92105_H__
  12
  13 /* SoC and board defines */
  14 #include <linux/sizes.h>
  15 #include <asm/arch/cpu.h>
  16
  17 /*
  18  * Define work_92105 machine type by hand -- done only for compatibility
  19  * with original board code
  20  */
  21 #define MACH_TYPE_WORK_92105            736
  22 #define CONFIG_MACH_TYPE                MACH_TYPE_WORK_92105
  23
  24 #define CONFIG_SYS_ICACHE_OFF
  25 #define CONFIG_SYS_DCACHE_OFF
  26 #if !defined(CONFIG_SPL_BUILD)
  27 #define CONFIG_SKIP_LOWLEVEL_INIT
  28 #endif
  29 #define CONFIG_BOARD_EARLY_INIT_F
  30 #define CONFIG_BOARD_EARLY_INIT_R
  31
  32 /* generate LPC32XX-specific SPL image */
  33 #define CONFIG_LPC32XX_SPL
  34
  35 /*
  36  * Memory configurations
  37  */
  38 #define CONFIG_NR_DRAM_BANKS            1
  39 #define CONFIG_SYS_MALLOC_LEN           SZ_1M
  40 #define CONFIG_SYS_SDRAM_BASE           EMC_DYCS0_BASE
  41 #define CONFIG_SYS_SDRAM_SIZE           SZ_128M
  42 #define CONFIG_SYS_TEXT_BASE            0x80100000
  43 #define CONFIG_SYS_MEMTEST_START        (CONFIG_SYS_SDRAM_BASE + SZ_32K)
  44 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_TEXT_BASE - SZ_1M)
  45
  46 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + SZ_32K)
  47
  48 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + SZ_512K \
  49                                          - GENERATED_GBL_DATA_SIZE)
  50
  51 /*
  52  * Serial Driver
  53  */
  54 #define CONFIG_SYS_LPC32XX_UART         5   /* UART5 - NS16550 */
  55 #define CONFIG_BAUDRATE                 115200
  56
  57 /*
  58  * Ethernet Driver
  59  */
  60
  61 #define CONFIG_PHY_SMSC
  62 #define CONFIG_LPC32XX_ETH
  63 #define CONFIG_PHYLIB
  64 #define CONFIG_PHY_ADDR 0
  65 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  66 #define CONFIG_CMD_MII
  67 /* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */
  68
  69 /*
  70  * I2C driver
  71  */
  72
  73 #define CONFIG_SYS_I2C_LPC32XX
  74 #define CONFIG_SYS_I2C
  75 #define CONFIG_SYS_I2C_SPEED 350000
  76
  77 /*
  78  * I2C EEPROM
  79  */
  80
  81 #define CONFIG_CMD_EEPROM
  82 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x56
  83 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  84
  85 /*
  86  * I2C RTC
  87  */
  88
  89 #define CONFIG_CMD_DATE
  90 #define CONFIG_RTC_DS1374
  91
  92 /*
  93  * I2C Temperature Sensor (DTT)
  94  */
  95
  96 #define CONFIG_CMD_DTT
  97 #define CONFIG_DTT_SENSORS { 0, 1 }
  98 #define CONFIG_DTT_DS620
  99
 100 /*
 101  * U-Boot General Configurations
 102  */
 103 #define CONFIG_SYS_LONGHELP
 104 #define CONFIG_SYS_CBSIZE               1024
 105 #define CONFIG_SYS_PBSIZE               \
 106         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 107 #define CONFIG_SYS_MAXARGS              16
 108 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 109
 110
 111 #define CONFIG_AUTO_COMPLETE
 112 #define CONFIG_CMDLINE_EDITING
 113 #define CONFIG_VERSION_VARIABLE
 114 #define CONFIG_DISPLAY_CPUINFO
 115 #define CONFIG_DOS_PARTITION
 116
 117 /*
 118  * No NOR
 119  */
 120
 121 #define CONFIG_SYS_NO_FLASH
 122
 123 /*
 124  * NAND chip timings for FIXME: which one?
 125  */
 126
 127 #define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY  333333333
 128 #define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY   10000000
 129 #define CONFIG_LPC32XX_NAND_MLC_NAND_TA      18181818
 130 #define CONFIG_LPC32XX_NAND_MLC_RD_HIGH      31250000
 131 #define CONFIG_LPC32XX_NAND_MLC_RD_LOW       45454545
 132 #define CONFIG_LPC32XX_NAND_MLC_WR_HIGH      40000000
 133 #define CONFIG_LPC32XX_NAND_MLC_WR_LOW       83333333
 134
 135 /*
 136  * NAND
 137  */
 138
 139 /* driver configuration */
 140 #define CONFIG_SYS_NAND_SELF_INIT
 141 #define CONFIG_SYS_MAX_NAND_DEVICE 1
 142 #define CONFIG_SYS_MAX_NAND_CHIPS 1
 143 #define CONFIG_SYS_NAND_BASE MLC_NAND_BASE
 144 #define CONFIG_NAND_LPC32XX_MLC
 145
 146 #define CONFIG_CMD_NAND
 147
 148 /*
 149  * GPIO
 150  */
 151
 152 #define CONFIG_LPC32XX_GPIO
 153
 154 /*
 155  * SSP/SPI/DISPLAY
 156  */
 157
 158 #define CONFIG_LPC32XX_SSP
 159 #define CONFIG_LPC32XX_SSP_TIMEOUT 100000
 160 #define CONFIG_CMD_MAX6957
 161 #define CONFIG_CMD_HD44760
 162 /*
 163  * Environment
 164  */
 165
 166 #define CONFIG_ENV_IS_IN_NAND           1
 167 #define CONFIG_ENV_SIZE                 0x00020000
 168 #define CONFIG_ENV_OFFSET               0x00100000
 169 #define CONFIG_ENV_OFFSET_REDUND        0x00120000
 170 #define CONFIG_ENV_ADDR                 0x80000100
 171
 172 /*
 173  * Boot Linux
 174  */
 175 #define CONFIG_CMDLINE_TAG
 176 #define CONFIG_SETUP_MEMORY_TAGS
 177 #define CONFIG_INITRD_TAG
 178
 179 #define CONFIG_ZERO_BOOTDELAY_CHECK
 180 #define CONFIG_BOOTDELAY                3
 181
 182 #define CONFIG_BOOTFILE                 "uImage"
 183 #define CONFIG_BOOTARGS                 "console=ttyS2,115200n8"
 184 #define CONFIG_LOADADDR                 0x80008000
 185
 186 /*
 187  * SPL
 188  */
 189
 190 /* SPL will be executed at offset 0 */
 191 #define CONFIG_SPL_TEXT_BASE 0x00000000
 192 /* SPL will use SRAM as stack */
 193 #define CONFIG_SPL_STACK     0x0000FFF8
 194 #define CONFIG_SPL_BOARD_INIT
 195 /* Use the framework and generic lib */
 196 #define CONFIG_SPL_FRAMEWORK
 197 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 198 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 199 /* SPL will use serial */
 200 #define CONFIG_SPL_SERIAL_SUPPORT
 201 /* SPL will load U-Boot from NAND offset 0x40000 */
 202 #define CONFIG_SPL_NAND_SUPPORT
 203 #define CONFIG_SPL_NAND_DRIVERS
 204 #define CONFIG_SPL_NAND_BASE
 205 #define CONFIG_SPL_NAND_BOOT
 206 #define CONFIG_SYS_NAND_U_BOOT_OFFS  0x00040000
 207 #define CONFIG_SPL_PAD_TO 0x20000
 208 /* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
 209 #define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */
 210 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
 211 #define CONFIG_SYS_NAND_U_BOOT_DST   CONFIG_SYS_TEXT_BASE
 212
 213 /*
 214  * Include SoC specific configuration
 215  */
 216 #include <asm/arch/config.h>
 217
 218 #endif  /* __CONFIG_WORK_92105_H__*/