include/configs/work_92105.h

   1 /*
   2  * WORK Microwave work_92105 board configuration file
   3  *
   4  * (C) Copyright 2014  DENX Software Engineering GmbH
   5  * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __CONFIG_WORK_92105_H__
  11 #define __CONFIG_WORK_92105_H__
  12
  13 /* SoC and board defines */
  14 #include <linux/sizes.h>
  15 #include <asm/arch/cpu.h>
  16
  17 /*
  18  * Define work_92105 machine type by hand -- done only for compatibility
  19  * with original board code
  20  */
  21 #define MACH_TYPE_WORK_92105            736
  22 #define CONFIG_MACH_TYPE                MACH_TYPE_WORK_92105
  23
  24 #define CONFIG_SYS_ICACHE_OFF
  25 #define CONFIG_SYS_DCACHE_OFF
  26 #if !defined(CONFIG_SPL_BUILD)
  27 #define CONFIG_SKIP_LOWLEVEL_INIT
  28 #endif
  29 #define CONFIG_BOARD_EARLY_INIT_F
  30 #define CONFIG_BOARD_EARLY_INIT_R
  31
  32 /* generate LPC32XX-specific SPL image */
  33 #define CONFIG_LPC32XX_SPL
  34
  35 /*
  36  * Memory configurations
  37  */
  38 #define CONFIG_NR_DRAM_BANKS            1
  39 #define CONFIG_SYS_MALLOC_LEN           SZ_1M
  40 #define CONFIG_SYS_SDRAM_BASE           EMC_DYCS0_BASE
  41 #define CONFIG_SYS_SDRAM_SIZE           SZ_128M
  42 #define CONFIG_SYS_TEXT_BASE            0x80100000
  43 #define CONFIG_SYS_MEMTEST_START        (CONFIG_SYS_SDRAM_BASE + SZ_32K)
  44 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_TEXT_BASE - SZ_1M)
  45
  46 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + SZ_32K)
  47
  48 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + SZ_512K \
  49                                          - GENERATED_GBL_DATA_SIZE)
  50
  51 /*
  52  * Serial Driver
  53  */
  54 #define CONFIG_SYS_LPC32XX_UART         5   /* UART5 - NS16550 */
  55 #define CONFIG_BAUDRATE                 115200
  56
  57 /*
  58  * Ethernet Driver
  59  */
  60
  61 #define CONFIG_PHY_SMSC
  62 #define CONFIG_LPC32XX_ETH
  63 #define CONFIG_PHYLIB
  64 #define CONFIG_PHY_ADDR 0
  65 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  66 #define CONFIG_CMD_MII
  67 #define CONFIG_CMD_PING
  68 #define CONFIG_CMD_DHCP
  69 /* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */
  70
  71 /*
  72  * I2C driver
  73  */
  74
  75 #define CONFIG_SYS_I2C_LPC32XX
  76 #define CONFIG_SYS_I2C
  77 #define CONFIG_CMD_I2C
  78 #define CONFIG_SYS_I2C_SPEED 350000
  79
  80 /*
  81  * I2C EEPROM
  82  */
  83
  84 #define CONFIG_CMD_EEPROM
  85 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x56
  86 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  87
  88 /*
  89  * I2C RTC
  90  */
  91
  92 #define CONFIG_CMD_DATE
  93 #define CONFIG_RTC_DS1374
  94
  95 /*
  96  * I2C Temperature Sensor (DTT)
  97  */
  98
  99 #define CONFIG_CMD_DTT
 100 #define CONFIG_DTT_SENSORS { 0, 1 }
 101 #define CONFIG_DTT_DS620
 102
 103 /*
 104  * U-Boot General Configurations
 105  */
 106 #define CONFIG_SYS_LONGHELP
 107 #define CONFIG_SYS_CBSIZE               1024
 108 #define CONFIG_SYS_PBSIZE               \
 109         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 110 #define CONFIG_SYS_MAXARGS              16
 111 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 112
 113 #define CONFIG_SYS_HUSH_PARSER
 114
 115 #define CONFIG_AUTO_COMPLETE
 116 #define CONFIG_CMDLINE_EDITING
 117 #define CONFIG_VERSION_VARIABLE
 118 #define CONFIG_DISPLAY_CPUINFO
 119 #define CONFIG_DOS_PARTITION
 120
 121 /*
 122  * No NOR
 123  */
 124
 125 #define CONFIG_SYS_NO_FLASH
 126
 127 /*
 128  * NAND chip timings for FIXME: which one?
 129  */
 130
 131 #define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY  333333333
 132 #define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY   10000000
 133 #define CONFIG_LPC32XX_NAND_MLC_NAND_TA      18181818
 134 #define CONFIG_LPC32XX_NAND_MLC_RD_HIGH      31250000
 135 #define CONFIG_LPC32XX_NAND_MLC_RD_LOW       45454545
 136 #define CONFIG_LPC32XX_NAND_MLC_WR_HIGH      40000000
 137 #define CONFIG_LPC32XX_NAND_MLC_WR_LOW       83333333
 138
 139 /*
 140  * NAND
 141  */
 142
 143 /* driver configuration */
 144 #define CONFIG_SYS_NAND_SELF_INIT
 145 #define CONFIG_SYS_MAX_NAND_DEVICE 1
 146 #define CONFIG_SYS_MAX_NAND_CHIPS 1
 147 #define CONFIG_SYS_NAND_BASE MLC_NAND_BASE
 148 #define CONFIG_NAND_LPC32XX_MLC
 149
 150 #define CONFIG_CMD_NAND
 151
 152 /*
 153  * GPIO
 154  */
 155
 156 #define CONFIG_LPC32XX_GPIO
 157
 158 /*
 159  * SSP/SPI/DISPLAY
 160  */
 161
 162 #define CONFIG_CMD_SPI
 163 #define CONFIG_LPC32XX_SSP
 164 #define CONFIG_LPC32XX_SSP_TIMEOUT 100000
 165 #define CONFIG_CMD_MAX6957
 166 #define CONFIG_CMD_HD44760
 167 /*
 168  * Environment
 169  */
 170
 171 #define CONFIG_ENV_IS_IN_NAND           1
 172 #define CONFIG_ENV_SIZE                 0x00020000
 173 #define CONFIG_ENV_OFFSET               0x00100000
 174 #define CONFIG_ENV_OFFSET_REDUND        0x00120000
 175 #define CONFIG_ENV_ADDR                 0x80000100
 176
 177 /*
 178  * Boot Linux
 179  */
 180 #define CONFIG_CMDLINE_TAG
 181 #define CONFIG_SETUP_MEMORY_TAGS
 182 #define CONFIG_INITRD_TAG
 183
 184 #define CONFIG_ZERO_BOOTDELAY_CHECK
 185 #define CONFIG_BOOTDELAY                3
 186
 187 #define CONFIG_BOOTFILE                 "uImage"
 188 #define CONFIG_BOOTARGS                 "console=ttyS2,115200n8"
 189 #define CONFIG_LOADADDR                 0x80008000
 190
 191 /*
 192  * SPL
 193  */
 194
 195 /* SPL will be executed at offset 0 */
 196 #define CONFIG_SPL_TEXT_BASE 0x00000000
 197 /* SPL will use SRAM as stack */
 198 #define CONFIG_SPL_STACK     0x0000FFF8
 199 #define CONFIG_SPL_BOARD_INIT
 200 /* Use the framework and generic lib */
 201 #define CONFIG_SPL_FRAMEWORK
 202 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 203 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 204 /* SPL will use serial */
 205 #define CONFIG_SPL_SERIAL_SUPPORT
 206 /* SPL will load U-Boot from NAND offset 0x40000 */
 207 #define CONFIG_SPL_NAND_SUPPORT
 208 #define CONFIG_SPL_NAND_DRIVERS
 209 #define CONFIG_SPL_NAND_BASE
 210 #define CONFIG_SPL_NAND_BOOT
 211 #define CONFIG_SYS_NAND_U_BOOT_OFFS  0x00040000
 212 #define CONFIG_SPL_PAD_TO 0x20000
 213 /* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
 214 #define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */
 215 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
 216 #define CONFIG_SYS_NAND_U_BOOT_DST   CONFIG_SYS_TEXT_BASE
 217
 218 /*
 219  * Include SoC specific configuration
 220  */
 221 #include <asm/arch/config.h>
 222
 223 #endif  /* __CONFIG_WORK_92105_H__*/