include/configs/xaeniax.h

   1 /*
   2  * (C) Copyright 2004-2005
   3  * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
   4  *
   5  * (C) Copyright 2004
   6  * Vincent Dubey, Xa SA, vincent.dubey@xa-ch.com
   7  *
   8  * (C) Copyright 2002
   9  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.ne
  10  *
  11  * (C) Copyright 2002
  12  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  13  * Marius Groeger <mgroeger@sysgo.de>
  14  *
  15  * Configuation settings for the xaeniax board.
  16  *
  17  * SPDX-License-Identifier:     GPL-2.0+
  18  */
  19
  20 #ifndef __CONFIG_H
  21 #define __CONFIG_H
  22
  23 /*
  24  * High Level Configuration Options
  25  * (easy to change)
  26  */
  27 #define CONFIG_CPU_PXA25X               1       /* This is an PXA255 CPU    */
  28 #define CONFIG_XAENIAX          1       /* on a xaeniax board       */
  29 #define CONFIG_SYS_TEXT_BASE    0x0
  30
  31 #define CONFIG_BOARD_LATE_INIT
  32
  33 /* we will never enable dcache, because we have to setup MMU first */
  34 #define CONFIG_SYS_DCACHE_OFF
  35
  36 /*
  37  * select serial console configuration
  38  */
  39 #define CONFIG_PXA_SERIAL
  40 #define CONFIG_BTUART          1       /* we use BTUART on XAENIAX */
  41 #define CONFIG_CONS_INDEX       4
  42
  43 /* allow to overwrite serial and ethaddr */
  44 #define CONFIG_ENV_OVERWRITE
  45
  46 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  47
  48 #define CONFIG_BAUDRATE         115200
  49
  50 /*
  51  * BOOTP options
  52  */
  53 #define CONFIG_BOOTP_BOOTFILESIZE
  54 #define CONFIG_BOOTP_BOOTPATH
  55 #define CONFIG_BOOTP_GATEWAY
  56 #define CONFIG_BOOTP_HOSTNAME
  57
  58
  59 /*
  60  * Command line configuration.
  61  */
  62 #define CONFIG_CMD_DHCP
  63 #define CONFIG_CMD_DIAG
  64 #define CONFIG_CMD_SDRAM
  65 #define CONFIG_CMD_SNTP
  66
  67 #undef CONFIG_CMD_DTT
  68
  69
  70 #define CONFIG_NETMASK          255.255.255.0
  71 #define CONFIG_IPADDR           192.168.68.201
  72 #define CONFIG_SERVERIP         192.168.68.62
  73
  74 #define CONFIG_BOOTDELAY        3
  75 #define CONFIG_BOOTCOMMAND      "bootm 0x00100000"
  76 #define CONFIG_BOOTARGS         "console=ttyS1,115200"
  77 #define CONFIG_CMDLINE_TAG              1       /* enable passing of ATAGs */
  78 #define CONFIG_SETUP_MEMORY_TAGS        1
  79 #define CONFIG_INITRD_TAG               1
  80
  81 #if defined(CONFIG_CMD_KGDB)
  82 #define CONFIG_KGDB_BAUDRATE    115200                  /* speed to run kgdb serial port */
  83 #endif
  84
  85 /*
  86  * Size of malloc() pool; this lives below the uppermost 128 KiB which are
  87  * used for the RAM copy of the uboot code
  88  */
  89 #define CONFIG_SYS_MALLOC_LEN       (CONFIG_ENV_SIZE + 128*1024)
  90
  91 /*
  92  * Miscellaneous configurable options
  93  */
  94 #define CONFIG_SYS_LONGHELP                             /* undef to save memory */
  95 #define CONFIG_SYS_HUSH_PARSER          1
  96
  97
  98 #ifdef CONFIG_SYS_HUSH_PARSER
  99 #define CONFIG_SYS_PROMPT               "u-boot$ "      /* Monitor Command Prompt */
 100 #else
 101 #define CONFIG_SYS_PROMPT               "u-boot=> "     /* Monitor Command Prompt */
 102 #endif
 103 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
 104 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 105 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
 106 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 107 #define CONFIG_SYS_DEVICE_NULLDEV       1
 108
 109 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on     */
 110 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM   */
 111
 112 #define CONFIG_SYS_LOAD_ADDR            0xa1000000      /* default load address */
 113
 114 #define CONFIG_SYS_CPUSPEED             0x141           /* set core clock to 400/200/100 MHz */
 115
 116 /*
 117  * Physical Memory Map
 118  */
 119 #define CONFIG_NR_DRAM_BANKS    1          /* we have 1 banks (partition) of DRAM */
 120 #define PHYS_SDRAM_1            0xa0000000 /* SDRAM Bank #1 */
 121 #define PHYS_SDRAM_1_SIZE       0x04000000 /* 64 MB */
 122 #define PHYS_SDRAM_2            0xa4000000 /* SDRAM Bank #2 */
 123 #define PHYS_SDRAM_2_SIZE       0x00000000 /* 0 MB */
 124 #define PHYS_SDRAM_3            0xa8000000 /* SDRAM Bank #3 */
 125 #define PHYS_SDRAM_3_SIZE       0x00000000 /* 0 MB */
 126 #define PHYS_SDRAM_4            0xac000000 /* SDRAM Bank #4 */
 127 #define PHYS_SDRAM_4_SIZE       0x00000000 /* 0 MB */
 128
 129 #define PHYS_FLASH_1            0x00000000 /* Flash Bank #1 */
 130 #define PHYS_FLASH_2            0x04000000 /* Flash Bank #2 */
 131 #define PHYS_FLASH_SIZE         0x02000000 /* 32 MB */
 132 #define PHYS_FLASH_BANK_SIZE    0x02000000 /* 32 MB Banks */
 133 #define PHYS_FLASH_SECT_SIZE    0x00040000 /* 256 KB sectors (x2) */
 134
 135 #define CONFIG_SYS_DRAM_BASE            0xa0000000
 136 #define CONFIG_SYS_DRAM_SIZE            0x04000000
 137
 138 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 139
 140 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 141 #define CONFIG_SYS_INIT_SP_ADDR         0xfffff800
 142
 143 /*
 144  * FLASH and environment organization
 145  */
 146 #define CONFIG_SYS_MAX_FLASH_BANKS      1    /* max number of memory banks              */
 147 #define CONFIG_SYS_MAX_FLASH_SECT       128  /* max number of sectors on one chip    */
 148
 149 /* timeout values are in ticks */
 150 #define CONFIG_SYS_FLASH_ERASE_TOUT     (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
 151 #define CONFIG_SYS_FLASH_WRITE_TOUT     (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 152
 153 /* FIXME */
 154 #define CONFIG_ENV_IS_IN_FLASH  1
 155 #define CONFIG_ENV_ADDR         (PHYS_FLASH_1 + 0x40000)/* Addr of Environment Sector   */
 156 #define CONFIG_ENV_SIZE         0x40000                 /* Total Size of Environment Sector     */
 157
 158 /*
 159  * SMSC91C111 Network Card
 160  */
 161 #define CONFIG_SMC91111         1
 162 #define CONFIG_SMC91111_BASE            0x10000300  /* chip select 3         */
 163 #define CONFIG_SMC_USE_32_BIT           1          /* 32 bit bus  */
 164 #undef  CONFIG_SMC_91111_EXT_PHY                   /* we use internal phy   */
 165 #undef  CONFIG_SHOW_ACTIVITY
 166 #define CONFIG_NET_RETRY_COUNT          10         /* # of retries          */
 167
 168 /*
 169  * GPIO settings
 170  */
 171
 172 /*
 173  * GP05 == nUSBReset  is 1
 174  * GP10 == CFReset   is 1
 175  * GP13 == nCFDataEnable is 1
 176  * GP14 == nCFAddrEnable is 1
 177  * GP15 == nCS1      is 1
 178  * GP21 == ComBrdReset is 1
 179  * GP24 == SFRM      is 1
 180  * GP25 == TXD       is 1
 181  * GP31 == SYNC      is 1
 182  * GP33 == nCS5      is 1
 183  * GP39 == FFTXD     is 1
 184  * GP41 == RTS       is 1
 185  * GP43 == BTTXD     is 1
 186  * GP45 == BTRTS     is 1
 187  * GP47 == TXD       is 1
 188  * GP48 == nPOE      is 1
 189  * GP49 == nPWE      is 1
 190  * GP50 == nPIOR     is 1
 191  * GP51 == nPIOW     is 1
 192  * GP52 == nPCE[1]   is 1
 193  * GP53 == nPCE[2]   is 1
 194  * GP54 == nPSKTSEL  is 1
 195  * GP55 == nPREG     is 1
 196  * GP78 == nCS2      is 1
 197  * GP79 == nCS3      is 1
 198  * GP80 == nCS4      is 1
 199  * GP82 == NSSPSFRM  is 1
 200  * GP83 == NSSPTXD   is 1
 201  */
 202 #define CONFIG_SYS_GPSR0_VAL            0x8320E420
 203 #define CONFIG_SYS_GPSR1_VAL            0x00FFAA82
 204 #define CONFIG_SYS_GPSR2_VAL            0x000DC000
 205
 206 /*
 207  * GP03 == LANReset  is 0
 208  * GP06 == USBWakeUp  is 0
 209  * GP11 == USBControl is 0
 210  * GP12 == Buzzer     is 0
 211  * GP16 == PWM0       is 0
 212  * GP17 == PWM1       is 0
 213  * GP23 == SCLK      is 0
 214  * GP30 == SDATA_OUT is 0
 215  * GP81 == NSSPCLK   is 0
 216  */
 217 #define CONFIG_SYS_GPCR0_VAL            0x40C31848
 218 #define CONFIG_SYS_GPCR1_VAL            0x00000000
 219 #define CONFIG_SYS_GPCR2_VAL            0x00020000
 220
 221 /*
 222  * GP00 == CPUWakeUpUSB is input
 223  * GP01 == GP reset is input
 224  * GP02 == LANInterrupt is input
 225  * GP03 == LANReset     is output
 226  * GP04 == USBInterrupt is input
 227  * GP05 == nUSBReset    is output
 228  * GP06 == USBWakeUp    is output
 229  * GP07 == CFReady/nBusy is input
 230  * GP08 == nCFCardDetect1 is input
 231  * GP09 == nCFCardDetect2 is input
 232  * GP10 == nCFReset   is output
 233  * GP11 == USBControl is output
 234  * GP12 == Buzzer     is output
 235  * GP13 == CFDataEnable is output
 236  * GP14 == CFAddressEnable is output
 237  * GP15 == nCS1      is output
 238  * GP16 == PWM0      is output
 239  * GP17 == PWM1      is output
 240  * GP18 == RDY       is input
 241  * GP19 == ReaderReady is input
 242  * GP20 == ReaderReset is input
 243  * GP21 == ComBrdReset is output
 244  * GP23 == SCLK      is output
 245  * GP24 == SFRM      is output
 246  * GP25 == TXD       is output
 247  * GP26 == RXD       is input
 248  * GP27 == EXTCLK    is input
 249  * GP28 == BITCLK    is output
 250  * GP29 == SDATA_IN0 is input
 251  * GP30 == SDATA_OUT is output
 252  * GP31 == SYNC      is output
 253  * GP32 == SYSSCLK   is output
 254  * GP33 == nCS5      is output
 255  * GP34 == FFRXD     is input
 256  * GP35 == CTS       is input
 257  * GP36 == DCD       is input
 258  * GP37 == DSR       is input
 259  * GP38 == RI        is input
 260  * GP39 == FFTXD     is output
 261  * GP40 == DTR       is output
 262  * GP41 == RTS       is output
 263  * GP42 == BTRXD     is input
 264  * GP43 == BTTXD     is output
 265  * GP44 == BTCTS     is input
 266  * GP45 == BTRTS     is output
 267  * GP46 == RXD       is input
 268  * GP47 == TXD       is output
 269  * GP48 == nPOE      is output
 270  * GP49 == nPWE      is output
 271  * GP50 == nPIOR     is output
 272  * GP51 == nPIOW     is output
 273  * GP52 == nPCE[1]   is output
 274  * GP53 == nPCE[2]   is output
 275  * GP54 == nPSKTSEL  is output
 276  * GP55 == nPREG     is output
 277  * GP56 == nPWAIT    is input
 278  * GP57 == nPIOS16   is input
 279  * GP58 == LDD[0]    is output
 280  * GP59 == LDD[1]    is output
 281  * GP60 == LDD[2]    is output
 282  * GP61 == LDD[3]    is output
 283  * GP62 == LDD[4]    is output
 284  * GP63 == LDD[5]    is output
 285  * GP64 == LDD[6]    is output
 286  * GP65 == LDD[7]    is output
 287  * GP66 == LDD[8]    is output
 288  * GP67 == LDD[9]    is output
 289  * GP68 == LDD[10]   is output
 290  * GP69 == LDD[11]   is output
 291  * GP70 == LDD[12]   is output
 292  * GP71 == LDD[13]   is output
 293  * GP72 == LDD[14]   is output
 294  * GP73 == LDD[15]   is output
 295  * GP74 == LCD_FCLK  is output
 296  * GP75 == LCD_LCLK  is output
 297  * GP76 == LCD_PCLK  is output
 298  * GP77 == LCD_ACBIAS is output
 299  * GP78 == nCS2      is output
 300  * GP79 == nCS3      is output
 301  * GP80 == nCS4      is output
 302  * GP81 == NSSPCLK   is output
 303  * GP82 == NSSPSFRM  is output
 304  * GP83 == NSSPTXD   is output
 305  * GP84 == NSSPRXD   is input
 306  */
 307 #define CONFIG_SYS_GPDR0_VAL            0xD3E3FC68
 308 #define CONFIG_SYS_GPDR1_VAL            0xFCFFAB83
 309 #define CONFIG_SYS_GPDR2_VAL            0x000FFFFF
 310
 311 /*
 312  * GP01 == GP reset is AF01
 313  * GP15 == nCS1     is AF10
 314  * GP16 == PWM0     is AF10
 315  * GP17 == PWM1     is AF10
 316  * GP18 == RDY      is AF01
 317  * GP23 == SCLK     is AF10
 318  * GP24 == SFRM     is AF10
 319  * GP25 == TXD      is AF10
 320  * GP26 == RXD      is AF01
 321  * GP27 == EXTCLK   is AF01
 322  * GP28 == BITCLK   is AF01
 323  * GP29 == SDATA_IN0 is AF10
 324  * GP30 == SDATA_OUT is AF01
 325  * GP31 == SYNC     is AF01
 326  * GP32 == SYSCLK   is AF01
 327  * GP33 == nCS5  is AF10
 328  * GP34 == FFRXD is AF01
 329  * GP35 == CTS   is AF01
 330  * GP36 == DCD   is AF01
 331  * GP37 == DSR   is AF01
 332  * GP38 == RI    is AF01
 333  * GP39 == FFTXD is AF10
 334  * GP40 == DTR   is AF10
 335  * GP41 == RTS   is AF10
 336  * GP42 == BTRXD is AF01
 337  * GP43 == BTTXD is AF10
 338  * GP44 == BTCTS is AF01
 339  * GP45 == BTRTS is AF10
 340  * GP46 == RXD   is AF10
 341  * GP47 == TXD   is AF01
 342  * GP48 == nPOE  is AF10
 343  * GP49 == nPWE  is AF10
 344  * GP50 == nPIOR is AF10
 345  * GP51 == nPIOW is AF10
 346  * GP52 == nPCE[1] is AF10
 347  * GP53 == nPCE[2] is AF10
 348  * GP54 == nPSKTSEL is AF10
 349  * GP55 == nPREG   is AF10
 350  * GP56 == nPWAIT  is AF01
 351  * GP57 == nPIOS16 is AF01
 352  * GP58 == LDD[0]  is AF10
 353  * GP59 == LDD[1]  is AF10
 354  * GP60 == LDD[2]  is AF10
 355  * GP61 == LDD[3]  is AF10
 356  * GP62 == LDD[4]  is AF10
 357  * GP63 == LDD[5]  is AF10
 358  * GP64 == LDD[6]  is AF10
 359  * GP65 == LDD[7]  is AF10
 360  * GP66 == LDD[8]  is AF10
 361  * GP67 == LDD[9]  is AF10
 362  * GP68 == LDD[10] is AF10
 363  * GP69 == LDD[11] is AF10
 364  * GP70 == LDD[12] is AF10
 365  * GP71 == LDD[13] is AF10
 366  * GP72 == LDD[14] is AF10
 367  * GP73 == LDD[15] is AF10
 368  * GP74 == LCD_FCLK is AF10
 369  * GP75 == LCD_LCLK is AF10
 370  * GP76 == LCD_PCLK is AF10
 371  * GP77 == LCD_ACBIAS is AF10
 372  * GP78 == nCS2     is AF10
 373  * GP79 == nCS3     is AF10
 374  * GP80 == nCS4     is AF10
 375  * GP81 == NSSPCLK  is AF01
 376  * GP82 == NSSPSFRM is AF01
 377  * GP83 == NSSPTXD  is AF01
 378  * GP84 == NSSPRXD  is AF10
 379  */
 380 #define CONFIG_SYS_GAFR0_L_VAL          0x80000004
 381 #define CONFIG_SYS_GAFR0_U_VAL          0x595A801A
 382 #define CONFIG_SYS_GAFR1_L_VAL          0x699A9559
 383 #define CONFIG_SYS_GAFR1_U_VAL          0xAAA5AAAA
 384 #define CONFIG_SYS_GAFR2_L_VAL          0xAAAAAAAA
 385 #define CONFIG_SYS_GAFR2_U_VAL          0x00000256
 386
 387 /*
 388  * clock settings
 389  */
 390 /* RDH = 1
 391  * PH  = 0
 392  * VFS = 0
 393  * BFS = 0
 394  * SSS = 0
 395  */
 396 #define CONFIG_SYS_PSSR_VAL             0x00000030
 397
 398 #define CONFIG_SYS_CKEN                 0x00000080  /*  */
 399 #define CONFIG_SYS_ICMR                 0x00000000  /* No interrupts enabled        */
 400 #define CONFIG_SYS_CCCR                 CCCR_L27|CCCR_M2|CCCR_N10
 401
 402
 403 /*
 404  * Memory settings
 405  *
 406  * This is the configuration for nCS0/1 -> flash banks
 407  * configuration for nCS1 :
 408  * [31]    0    -
 409  * [30:28] 000  -
 410  * [27:24] 0000 -
 411  * [23:20] 0000 -
 412  * [19]    0    -
 413  * [18:16] 000  -
 414  * configuration for nCS0:
 415  * [15]    0    - Slower Device
 416  * [14:12] 010  - CS deselect to CS time: 2*(2*MemClk) = 40 ns
 417  * [11:08] 0011 - Address to data valid in bursts: (3+1)*MemClk = 40 ns
 418  * [07:04] 1111 - " for first access: (23+2)*MemClk = 250 ns (fixme 12+2?)
 419  * [03]    0    - 32 Bit bus width
 420  * [02:00] 010  - burst OF 4 ROM or FLASH
 421 */
 422 #define CONFIG_SYS_MSC0_VAL             0x000023D2
 423
 424 /* This is the configuration for nCS2/3 -> USB controller, LAN
 425  * configuration for nCS3: LAN
 426  * [31]    0    - Slower Device
 427  * [30:28] 001  - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
 428  * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
 429  * [23:20] 0010 - RDF3: Address for first access: (2+1)*MemClk = 30 ns
 430  * [19]    0    - 32 Bit bus width
 431  * [18:16] 100  - variable latency I/O
 432  * configuration for nCS2: USB
 433  * [15]    1    - Faster Device
 434  * [14:12] 010  - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns
 435  * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns
 436  * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns
 437  * [03]    1    - 16 Bit bus width
 438  * [02:00] 100  - variable latency I/O
 439  */
 440 #define CONFIG_SYS_MSC1_VAL             0x1224A26C
 441
 442 /* This is the configuration for nCS4/5 -> LAN
 443  * configuration for nCS5:
 444  * [31]    0    -
 445  * [30:28] 000  -
 446  * [27:24] 0000 -
 447  * [23:20] 0000 -
 448  * [19]    0    -
 449  * [18:16] 000  -
 450  * configuration for nCS4: LAN
 451  * [15]    1    - Faster Device
 452  * [14:12] 010  - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns
 453  * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns
 454  * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns
 455  * [03]    0    - 32 Bit bus width
 456  * [02:00] 100  - variable latency I/O
 457  */
 458 #define CONFIG_SYS_MSC2_VAL             0x00001224
 459
 460 /* MDCNFG: SDRAM Configuration Register
 461  *
 462  * [31:29]   000 - reserved
 463  * [28]      0   - no SA1111 compatiblity mode
 464  * [27]      0   - latch return data with return clock
 465  * [26]      0   - alternate addressing for pair 2/3
 466  * [25:24]   00  - timings
 467  * [23]      0   - internal banks in lower partition 2/3 (not used)
 468  * [22:21]   00  - row address bits for partition 2/3 (not used)
 469  * [20:19]   00  - column address bits for partition 2/3 (not used)
 470  * [18]      0   - SDRAM partition 2/3 width is 32 bit
 471  * [17]      0   - SDRAM partition 3 disabled
 472  * [16]      0   - SDRAM partition 2 disabled
 473  * [15:13]   000 - reserved
 474  * [12]      0   - no SA1111 compatiblity mode
 475  * [11]      1   - latch return data with return clock
 476  * [10]      0   - no alternate addressing for pair 0/1
 477  * [09:08]   10  - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
 478  * [7]       1   - 4 internal banks in lower partition pair
 479  * [06:05]   10  - 13 row address bits for partition 0/1
 480  * [04:03]   01  - 9 column address bits for partition 0/1
 481  * [02]      0   - SDRAM partition 0/1 width is 32 bit
 482  * [01]      0   - disable SDRAM partition 1
 483  * [00]      1   - enable  SDRAM partition 0
 484  */
 485 /* use the configuration above but disable partition 0 */
 486 #define CONFIG_SYS_MDCNFG_VAL           0x00000AC9
 487
 488 /* MDREFR: SDRAM Refresh Control Register
 489  *
 490  * [32:26] 0     - reserved
 491  * [25]    0     - K2FREE: not free running
 492  * [24]    0     - K1FREE: not free running
 493  * [23]    0     - K0FREE: not free running
 494  * [22]    0     - SLFRSH: self refresh disabled
 495  * [21]    0     - reserved
 496  * [20]    1     - APD: auto power down
 497  * [19]    0     - K2DB2: SDCLK2 is MemClk
 498  * [18]    0     - K2RUN: disable SDCLK2
 499  * [17]    0     - K1DB2: SDCLK1 is MemClk
 500  * [16]    1     - K1RUN: enable SDCLK1
 501  * [15]    1     - E1PIN: SDRAM clock enable
 502  * [14]    0     - K0DB2: SDCLK0 is MemClk
 503  * [13]    0     - K0RUN: disable SDCLK0
 504  * [12]    0     - E0PIN: disable SDCKE0
 505  * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
 506  */
 507 #define CONFIG_SYS_MDREFR_VAL           0x00138018 /* mh: was 0x00118018 */
 508
 509 /* MDMRS: Mode Register Set Configuration Register
 510  *
 511  * [31]      0       - reserved
 512  * [30:23]   00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
 513  * [22:20]   011     - MDCL2:  SDRAM2/3 Cas Latency.  (not used)
 514  * [19]      0       - MDADD2: SDRAM2/3 burst Type. Fixed to sequential.  (not used)
 515  * [18:16]   010     - MDBL2:  SDRAM2/3 burst Length. Fixed to 4.  (not used)
 516  * [15]      0       - reserved
 517  * [14:07]   00000000- MDMRS0: SDRAM0/1 MRS Value.
 518  * [06:04]   011     - MDCL0:  SDRAM0/1 Cas Latency.
 519  * [03]      0       - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
 520  * [02:00]   010     - MDBL0:  SDRAM0/1 burst Length. Fixed to 4.
 521  */
 522 #define CONFIG_SYS_MDMRS_VAL            0x00320032
 523
 524 #define CONFIG_SYS_FLYCNFG_VAL          0x00000000
 525 #define CONFIG_SYS_SXCNFG_VAL           0x00000000
 526
 527 /*
 528  * PCMCIA and CF Interfaces
 529  */
 530 #define CONFIG_SYS_MECR_VAL             0x00000000
 531 #define CONFIG_SYS_MCMEM0_VAL           0x00010504
 532 #define CONFIG_SYS_MCMEM1_VAL           0x00010504
 533 #define CONFIG_SYS_MCATT0_VAL           0x00010504
 534 #define CONFIG_SYS_MCATT1_VAL           0x00010504
 535 #define CONFIG_SYS_MCIO0_VAL            0x00004715
 536 #define CONFIG_SYS_MCIO1_VAL            0x00004715
 537
 538
 539 #endif  /* __CONFIG_H */