include/configs/xm250.h

   1 /*
   2  * (C) Copyright 2002
   3  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
   4  *
   5  * (C) Copyright 2002
   6  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   7  * Marius Groeger <mgroeger@sysgo.de>
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35 #define CONFIG_PXA250          1        /* This is an PXA250 CPU        */
  36 #define CONFIG_XM250           1        /* on a MicroSys XM250 Board    */
  37 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff  */
  38
  39 /* we will never enable dcache, because we have to setup MMU first */
  40 #define CONFIG_SYS_NO_DCACHE
  41
  42 /*
  43  * Size of malloc() pool; this lives below the uppermost 128 KiB which are
  44  * used for the RAM copy of the uboot code
  45  *
  46  */
  47 #define CONFIG_SYS_MALLOC_LEN           (256*1024)
  48 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* size in bytes reserved for initial data */
  49
  50 /*
  51  * Hardware drivers
  52  */
  53 #define CONFIG_NET_MULTI
  54 #define CONFIG_SMC91111
  55 #define CONFIG_SMC91111_BASE            0x04000300
  56 #undef  CONFIG_SMC91111_EXT_PHY
  57 #define CONFIG_SMC_USE_32_BIT
  58 #undef  CONFIG_SHOW_ACTIVITY
  59 #define CONFIG_NET_RETRY_COUNT          10         /* # of retries              */
  60
  61 /*
  62  * I2C bus
  63  */
  64 #define CONFIG_HARD_I2C                 1
  65 #define CONFIG_SYS_I2C_SPEED                    50000
  66 #define CONFIG_SYS_I2C_SLAVE                    0xfe
  67
  68 #define CONFIG_RTC_PCF8563              1
  69 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
  70
  71 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x58    /* A0 = 0 (hardwired)           */
  72 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4       /* 4 bits = 16 octets           */
  73 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* between stop and start       */
  74 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1       /* length of address            */
  75 #define CONFIG_SYS_EEPROM_SIZE                  2048    /* size in bytes                */
  76 #undef  CONFIG_SYS_I2C_INIT_BOARD                       /* board has no own init        */
  77
  78 /*
  79  * select serial console configuration
  80  */
  81 #define CONFIG_PXA_SERIAL
  82 #define CONFIG_FFUART          1       /* we use FFUART */
  83
  84 /* allow to overwrite serial and ethaddr */
  85 #define CONFIG_ENV_OVERWRITE
  86
  87 #define CONFIG_BAUDRATE         115200
  88
  89
  90 /*
  91  * BOOTP options
  92  */
  93 #define CONFIG_BOOTP_BOOTFILESIZE
  94 #define CONFIG_BOOTP_BOOTPATH
  95 #define CONFIG_BOOTP_GATEWAY
  96 #define CONFIG_BOOTP_HOSTNAME
  97
  98
  99 /*
 100  * Command line configuration.
 101  */
 102 #include <config_cmd_default.h>
 103
 104 #define CONFIG_CMD_ELF
 105 #define CONFIG_CMD_EEPROM
 106 #define CONFIG_CMD_DATE
 107 #define CONFIG_CMD_I2C
 108
 109
 110 #define CONFIG_BOOTDELAY        3
 111
 112 /*
 113  * Miscellaneous configurable options
 114  */
 115 #define CONFIG_SYS_LONGHELP                             /* undef to save memory         */
 116 #define CONFIG_SYS_PROMPT               "=> "           /* Monitor Command Prompt       */
 117 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
 118 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 119 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
 120 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 121
 122 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on             */
 123 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM           */
 124
 125 #define CONFIG_SYS_LOAD_ADDR            0xa3000000      /* default load address */
 126
 127 #define CONFIG_SYS_HZ                   1000
 128 #define CONFIG_SYS_CPUSPEED             0x161           /* set core clock to 400/400/100 MHz */
 129
 130                                                 /* valid baudrates */
 131
 132 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 133
 134 /*
 135  * Definitions related to passing arguments to kernel.
 136  */
 137 #define CONFIG_CMDLINE_TAG       1       /* send commandline to Kernel          */
 138 #define CONFIG_SETUP_MEMORY_TAGS 1       /* send memory definition to kernel    */
 139 #define CONFIG_INITRD_TAG        1       /* do not send initrd params           */
 140 #undef  CONFIG_VFD                       /* do not send framebuffer setup       */
 141
 142 /*
 143  * Stack sizes
 144  *
 145  * The stack sizes are set up in start.S using the settings below
 146  */
 147 #define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
 148 #ifdef CONFIG_USE_IRQ
 149 #define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
 150 #define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
 151 #endif
 152
 153 /*
 154  * Physical Memory Map
 155  */
 156 #define CONFIG_NR_DRAM_BANKS    4
 157 #define PHYS_SDRAM_1            0xa0000000 /* SDRAM Bank #1     */
 158 #define PHYS_SDRAM_1_SIZE       0x04000000 /* 64 MB             */
 159 #define PHYS_SDRAM_2            0xa4000000 /* SDRAM Bank #2     */
 160 #define PHYS_SDRAM_2_SIZE       0x00000000 /* 0 MB              */
 161 #define PHYS_SDRAM_3            0xa8000000 /* SDRAM Bank #3     */
 162 #define PHYS_SDRAM_3_SIZE       0x00000000 /* 0 MB              */
 163 #define PHYS_SDRAM_4            0xac000000 /* SDRAM Bank #4     */
 164 #define PHYS_SDRAM_4_SIZE       0x00000000 /* 0 MB              */
 165
 166 #define PHYS_FLASH_1            0x00000000 /* Flash Bank #1     */
 167 #define PHYS_FLASH_2            0x04000000 /* Flash Bank #1     */
 168 #define PHYS_FLASH_SIZE         0x01000000 /* 16 MB             */
 169 #define PHYS_FLASH_BANK_SIZE    0x01000000 /* 16 MB Banks       */
 170 #define PHYS_FLASH_SECT_SIZE    0x00040000 /* 256 KB sectors (x2) */
 171
 172 #define CONFIG_SYS_DRAM_BASE            0xa0000000
 173 #define CONFIG_SYS_DRAM_SIZE            0x04000000
 174
 175 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 176
 177 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 178 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
 179
 180 /*
 181  * FLASH and environment organization
 182  */
 183 #define CONFIG_SYS_MAX_FLASH_BANKS      1     /* max number of memory banks             */
 184 #define CONFIG_SYS_MAX_FLASH_SECT       128   /* max number of sectors on one chip      */
 185
 186 /* timeout values are in ticks */
 187 #define CONFIG_SYS_FLASH_ERASE_TOUT     (2*CONFIG_SYS_HZ)       /* Timeout for Flash Erase      */
 188 #define CONFIG_SYS_FLASH_WRITE_TOUT     (2*CONFIG_SYS_HZ)       /* Timeout for Flash Write      */
 189 #define CONFIG_SYS_FLASH_LOCK_TOUT      (2*CONFIG_SYS_HZ)       /* Timeout for Flash Set Lock Bit */
 190 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    (2*CONFIG_SYS_HZ)       /* Timeout for Flash Clear Lock Bits */
 191 #define CONFIG_SYS_FLASH_PROTECTION                     /* "Real" (hardware) sectors protection */
 192
 193 #define CONFIG_ENV_IS_IN_FLASH  1
 194 #define CONFIG_ENV_ADDR         (PHYS_FLASH_1 + 0x40000)        /* Addr of Environment Sector   */
 195 #define CONFIG_ENV_SIZE         0x4000
 196 #define CONFIG_ENV_SECT_SIZE    0x40000                         /* Size of the Environment Sector       */
 197 #define CONFIG_SYS_MONITOR_LEN          0x20000                         /* 128 KiB */
 198
 199 /******************************************************************************
 200  *
 201  * CPU specific defines
 202  *
 203  ******************************************************************************/
 204
 205 /*
 206  * GPIO settings
 207  *
 208  * GPIO pin assignments
 209  * GPIO     Name        Dir Out AF
 210  * 0        NC
 211  * 1        NC
 212  * 2        SIRQ1       I
 213  * 3        SIRQ2       I
 214  * 4        SIRQ3       I
 215  * 5        DMAACK1     O   0
 216  * 6        DMAACK2     O   0
 217  * 7        DMAACK3     O   0
 218  * 8        TC1         O   0
 219  * 9        TC2         O   0
 220  * 10       TC3         O   0
 221  * 11       nDMAEN      O   1
 222  * 12       AENCTRL     O   0
 223  * 13       PLDTC       O   0
 224  * 14       ETHIRQ      I
 225  * 15       NC
 226  * 16       NC
 227  * 17       NC
 228  * 18       RDY         I
 229  * 19       DMASIO      I
 230  * 20       ETHIRQ      NC
 231  * 21       NC
 232  * 22       PGMEN       O   1    FIXME for debug only enable flash
 233  * 23       NC
 234  * 24       NC
 235  * 25       NC
 236  * 26       NC
 237  * 27       NC
 238  * 28       NC
 239  * 29       NC
 240  * 30       NC
 241  * 31       NC
 242  * 32       NC
 243  * 33       NC
 244  * 34       FFRXD       I       01
 245  * 35       FFCTS       I       01
 246  * 36       FFDCD       I       01
 247  * 37       FFDSR       I       01
 248  * 38       FFRI        I       01
 249  * 39       FFTXD       O   1   10
 250  * 40       FFDTR       O   0   10
 251  * 41       FFRTS       O   0   10
 252  * 42       RS232FOFF   O   0   00
 253  * 43       NC
 254  * 44       NC
 255  * 45       IRSL0       O   0
 256  * 46       IRRX0       I       01
 257  * 47       IRTX0       O   0   10
 258  * 48       NC
 259  * 49       nIOWE       O   0
 260  * 50       NC
 261  * 51       NC
 262  * 52       NC
 263  * 53       NC
 264  * 54       NC
 265  * 55       NC
 266  * 56       NC
 267  * 57       NC
 268  * 58       DKDIRQ      I
 269  * 59       NC
 270  * 60       NC
 271  * 61       NC
 272  * 62       NC
 273  * 63       NC
 274  * 64       COMLED      O   0
 275  * 65       COMLED      O   0
 276  * 66       COMLED      O   0
 277  * 67       COMLED      O   0
 278  * 68       COMLED      O   0
 279  * 69       COMLED      O   0
 280  * 70       COMLED      O   0
 281  * 71       COMLED      O   0
 282  * 72       NC
 283  * 73       NC
 284  * 74       NC
 285  * 75       NC
 286  * 76       NC
 287  * 77       NC
 288  * 78       CSIO        O   1
 289  * 79       NC
 290  * 80       CSETH       O   1
 291  *
 292  * NOTE: All NC's are defined to be outputs
 293  *
 294  */
 295 /* Pin direction control */
 296 #define CONFIG_SYS_GPDR0_VAL        0xd3808000
 297 #define CONFIG_SYS_GPDR1_VAL        0xfcffab83
 298 #define CONFIG_SYS_GPDR2_VAL        0x0001ffff
 299 /* Set and Clear registers */
 300 #define CONFIG_SYS_GPSR0_VAL        0x00008000
 301 #define CONFIG_SYS_GPSR1_VAL        0x00ff0002
 302 #define CONFIG_SYS_GPSR2_VAL        0x0001c000
 303 #define CONFIG_SYS_GPCR0_VAL        0x00000000
 304 #define CONFIG_SYS_GPCR1_VAL        0x00000000
 305 #define CONFIG_SYS_GPCR2_VAL        0x00000000
 306 /* Edge detect registers (these are set by the kernel) */
 307 #define CONFIG_SYS_GRER0_VAL        0x00002180
 308 #define CONFIG_SYS_GRER1_VAL        0x00000000
 309 #define CONFIG_SYS_GRER2_VAL        0x00000000
 310 #define CONFIG_SYS_GFER0_VAL        0x000043e0
 311 #define CONFIG_SYS_GFER1_VAL        0x00000000
 312 #define CONFIG_SYS_GFER2_VAL        0x00000000
 313 /* Alternate function registers */
 314 #define CONFIG_SYS_GAFR0_L_VAL      0x80000004
 315 #define CONFIG_SYS_GAFR0_U_VAL      0x595a8010
 316 #define CONFIG_SYS_GAFR1_L_VAL      0x699a9559
 317 #define CONFIG_SYS_GAFR1_U_VAL      0xaaa5aaaa
 318 #define CONFIG_SYS_GAFR2_L_VAL      0xaaaaaaaa
 319 #define CONFIG_SYS_GAFR2_U_VAL      0x00000002
 320
 321 /*
 322  * Clocks, power control and interrupts
 323  */
 324 #define CONFIG_SYS_PSSR_VAL         0x00000030
 325 #define CONFIG_SYS_CCCR_VAL         0x00000161  /* 100 MHz memory, 400 MHz CPU, 400 Turbo  */
 326 #define CONFIG_SYS_CKEN_VAL         0x000141ec  /* FFUART and STUART enabled    */
 327 #define CONFIG_SYS_ICMR_VAL         0x00000000  /* No interrupts enabled        */
 328
 329 /* FIXME
 330  *
 331  * RTC settings
 332  * Watchdog
 333  *
 334  */
 335
 336 /*
 337  * Memory settings
 338  *
 339  */
 340 #define CONFIG_SYS_MSC0_VAL         0x122423f0  /* FLASH   / LAN            (cs0)/(cS1)   */
 341 #define CONFIG_SYS_MSC1_VAL         0x35f4aa4c  /* USB     / ST3+ST5        (cs2)/(cS3)   */
 342 #define CONFIG_SYS_MSC2_VAL         0x35f435fc  /* IDE     / BCR + WatchDog (cs4)/(cS5)   */
 343 #define CONFIG_SYS_MDCNFG_VAL       0x000009c9
 344 #define CONFIG_SYS_MDMRS_VAL        0x00220022
 345 #define CONFIG_SYS_MDREFR_VAL       0x000da018  /* Initial setting, individual bits set in lowlevel_init.S */
 346
 347 /*
 348  * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
 349  */
 350 #define CONFIG_SYS_MECR_VAL           0x00000000
 351 #define CONFIG_SYS_MCMEM0_VAL         0x00010504
 352 #define CONFIG_SYS_MCMEM1_VAL         0x00010504
 353 #define CONFIG_SYS_MCATT0_VAL         0x00010504
 354 #define CONFIG_SYS_MCATT1_VAL         0x00010504
 355 #define CONFIG_SYS_MCIO0_VAL          0x00004715
 356 #define CONFIG_SYS_MCIO1_VAL          0x00004715
 357
 358 /* Board specific defines */
 359
 360 #ifndef __ASSEMBLY__
 361
 362 /* global prototypes */
 363 void led_code(int code, int color);
 364
 365 #endif
 366
 367 #endif  /* __CONFIG_H */