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[people/ms/u-boot.git] / include / configs / xpedite517x.h
1 /*
2 * Copyright 2009 Extreme Engineering Solutions, Inc.
3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 /*
9 * xpedite517x board configuration file
10 */
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 /*
15 * High Level Configuration Options
16 */
17 #define CONFIG_SYS_BOARD_NAME "XPedite5170"
18 #define CONFIG_SYS_FORM_3U_VPX 1
19 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
20 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
21 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */
22 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
23 #define CONFIG_ALTIVEC 1
24
25 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
26 #define CONFIG_PCIE1 1 /* PCIE controller 1 */
27 #define CONFIG_PCIE2 1 /* PCIE controller 2 */
28 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
29 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
30 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
31
32 /*
33 * DDR config
34 */
35 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
36 #define CONFIG_DDR_SPD
37 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
38 #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
39 #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
40 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
41 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
42 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
43 #define CONFIG_DDR_ECC
44 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
45 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
46 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
47 #define CONFIG_VERY_BIG_RAM
48 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
49
50 /*
51 * virtual address to be used for temporary mappings. There
52 * should be 128k free at this VA.
53 */
54 #define CONFIG_SYS_SCRATCH_VA 0xe0000000
55
56 #ifndef __ASSEMBLY__
57 extern unsigned long get_board_sys_clk(unsigned long dummy);
58 #endif
59
60 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */
61
62 /*
63 * L2CR setup
64 */
65 #define CONFIG_SYS_L2
66 #define L2_INIT 0
67 #define L2_ENABLE (L2CR_L2E)
68
69 /*
70 * Base addresses -- Note these are effective addresses where the
71 * actual resources get mapped (not physical addresses)
72 */
73 #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
74 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
75 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
76 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
77 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
78
79 /*
80 * Diagnostics
81 */
82 #define CONFIG_SYS_ALT_MEMTEST
83 #define CONFIG_SYS_MEMTEST_START 0x10000000
84 #define CONFIG_SYS_MEMTEST_END 0x20000000
85 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\
86 CONFIG_SYS_POST_I2C)
87 /* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
88 #define I2C_ADDR_IGNORE_LIST {0x50}
89
90 /*
91 * Memory map
92 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
93 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
94 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
95 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
96 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
97 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
98 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
99 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
100 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
101 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
102 */
103
104 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
105
106 /*
107 * NAND flash configuration
108 */
109 #define CONFIG_SYS_NAND_BASE 0xef800000
110 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
111 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
112 #define CONFIG_SYS_MAX_NAND_DEVICE 2
113 #define CONFIG_NAND_ACTL
114 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */
115 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */
116 #define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */
117 #define CONFIG_SYS_NAND_ACTL_DELAY 25
118 #define CONFIG_JFFS2_NAND
119
120 /*
121 * NOR flash configuration
122 */
123 #define CONFIG_SYS_FLASH_BASE 0xf8000000
124 #define CONFIG_SYS_FLASH_BASE2 0xf0000000
125 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
126 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
127 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
128 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
129 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
130 #define CONFIG_FLASH_CFI_DRIVER
131 #define CONFIG_SYS_FLASH_CFI
132 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
133 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \
134 {0xf7f00000, 0xc0000} }
135 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
136 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
137
138 /*
139 * Chip select configuration
140 */
141 /* NOR Flash 0 on CS0 */
142 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
143 BR_PS_16 |\
144 BR_V)
145 #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\
146 OR_GPCM_CSNT |\
147 OR_GPCM_XACS |\
148 OR_GPCM_ACS_DIV2 |\
149 OR_GPCM_SCY_8 |\
150 OR_GPCM_TRLX |\
151 OR_GPCM_EHTR |\
152 OR_GPCM_EAD)
153
154 /* NOR Flash 1 on CS1 */
155 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\
156 BR_PS_16 |\
157 BR_V)
158 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
159
160 /* NAND flash on CS2 */
161 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\
162 BR_PS_8 |\
163 BR_V)
164 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\
165 OR_GPCM_BCTLD |\
166 OR_GPCM_CSNT |\
167 OR_GPCM_ACS_DIV4 |\
168 OR_GPCM_SCY_4 |\
169 OR_GPCM_TRLX |\
170 OR_GPCM_EHTR)
171
172 /* Optional NAND flash on CS3 */
173 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\
174 BR_PS_8 |\
175 BR_V)
176 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
177
178 /*
179 * Use L1 as initial stack
180 */
181 #define CONFIG_SYS_INIT_RAM_LOCK 1
182 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
183 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
184
185 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
186 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
187
188 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
189 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
190
191 /*
192 * Serial Port
193 */
194 #define CONFIG_CONS_INDEX 1
195 #define CONFIG_SYS_NS16550_SERIAL
196 #define CONFIG_SYS_NS16550_REG_SIZE 1
197 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
198 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
199 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
200 #define CONFIG_SYS_BAUDRATE_TABLE \
201 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
202 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
203 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
204
205 /*
206 * I2C
207 */
208 #define CONFIG_SYS_I2C
209 #define CONFIG_SYS_I2C_FSL
210 #define CONFIG_SYS_FSL_I2C_SPEED 100000
211 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
212 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
213 #define CONFIG_SYS_FSL_I2C2_SPEED 100000
214 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
215 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
216
217 /* PEX8518 slave I2C interface */
218 #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
219
220 /* I2C DS1631 temperature sensor */
221 #define CONFIG_SYS_I2C_LM90_ADDR 0x4c
222
223 /* I2C EEPROM - AT24C128B */
224 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
225 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
226 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
227 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
228
229 /* I2C RTC */
230 #define CONFIG_RTC_M41T11 1
231 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
232 #define CONFIG_SYS_M41T11_BASE_YEAR 2000
233
234 /* GPIO */
235 #define CONFIG_PCA953X
236 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
237 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
238 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
239 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
240 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
241 #define CONFIG_SYS_I2C_PCA9553_ADDR 0x62
242
243 /*
244 * PU = pulled high, PD = pulled low
245 * I = input, O = output, IO = input/output
246 */
247 /* PCA9557 @ 0x18*/
248 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
249 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
250 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
251 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
252 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
253 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
254
255 /* PCA9557 @ 0x1c*/
256 #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
257 #define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */
258 #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
259 #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
260 #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
261 #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
262 #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
263 #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
264
265 /* PCA9557 @ 0x1e*/
266 #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
267 #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
268 #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
269 #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
270 #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
271 #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */
272 #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */
273
274 /* PCA9557 @ 0x1f */
275 #define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */
276 #define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */
277 #define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */
278 #define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */
279
280 /*
281 * General PCI
282 * Memory space is mapped 1-1, but I/O space must start from 0.
283 */
284 /* PCIE1 - PEX8518 */
285 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
286 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
287 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
288 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
289 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
290 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
291
292 /* PCIE2 - VPX P1 */
293 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
294 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
295 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
296 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
297 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
298 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
299
300 /*
301 * Networking options
302 */
303 #define CONFIG_TSEC_ENET /* tsec ethernet support */
304 #define CONFIG_MII 1 /* MII PHY management */
305 #define CONFIG_ETHPRIME "eTSEC1"
306
307 #define CONFIG_TSEC1 1
308 #define CONFIG_TSEC1_NAME "eTSEC1"
309 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
310 #define TSEC1_PHY_ADDR 1
311 #define TSEC1_PHYIDX 0
312 #define CONFIG_HAS_ETH0
313
314 #define CONFIG_TSEC2 1
315 #define CONFIG_TSEC2_NAME "eTSEC2"
316 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
317 #define TSEC2_PHY_ADDR 2
318 #define TSEC2_PHYIDX 0
319 #define CONFIG_HAS_ETH1
320
321 /*
322 * BAT mappings
323 */
324 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
325 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
326 BATL_PP_RW |\
327 BATL_CACHEINHIBIT |\
328 BATL_GUARDEDSTORAGE)
329 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\
330 BATU_BL_1M |\
331 BATU_VS |\
332 BATU_VP)
333 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
334 BATL_PP_RW |\
335 BATL_CACHEINHIBIT)
336 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
337 #endif
338
339 /*
340 * BAT0 2G Cacheable, non-guarded
341 * 0x0000_0000 2G DDR
342 */
343 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
344 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
345 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
346 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
347
348 /*
349 * BAT1 1G Cache-inhibited, guarded
350 * 0x8000_0000 1G PCI-Express 1 Memory
351 */
352 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
353 BATL_PP_RW |\
354 BATL_CACHEINHIBIT |\
355 BATL_GUARDEDSTORAGE)
356 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\
357 BATU_BL_1G |\
358 BATU_VS |\
359 BATU_VP)
360 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
361 BATL_PP_RW |\
362 BATL_CACHEINHIBIT)
363 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
364
365 /*
366 * BAT2 512M Cache-inhibited, guarded
367 * 0xc000_0000 512M PCI-Express 2 Memory
368 */
369 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
370 BATL_PP_RW |\
371 BATL_CACHEINHIBIT |\
372 BATL_GUARDEDSTORAGE)
373 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\
374 BATU_BL_512M |\
375 BATU_VS |\
376 BATU_VP)
377 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
378 BATL_PP_RW |\
379 BATL_CACHEINHIBIT)
380 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
381
382 /*
383 * BAT3 1M Cache-inhibited, guarded
384 * 0xe000_0000 1M CCSR
385 */
386 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\
387 BATL_PP_RW |\
388 BATL_CACHEINHIBIT |\
389 BATL_GUARDEDSTORAGE)
390 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\
391 BATU_BL_1M |\
392 BATU_VS |\
393 BATU_VP)
394 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\
395 BATL_PP_RW |\
396 BATL_CACHEINHIBIT)
397 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
398
399 /*
400 * BAT4 32M Cache-inhibited, guarded
401 * 0xe200_0000 16M PCI-Express 1 I/O
402 * 0xe300_0000 16M PCI-Express 2 I/0
403 */
404 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
405 BATL_PP_RW |\
406 BATL_CACHEINHIBIT |\
407 BATL_GUARDEDSTORAGE)
408 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\
409 BATU_BL_32M |\
410 BATU_VS |\
411 BATU_VP)
412 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
413 BATL_PP_RW |\
414 BATL_CACHEINHIBIT)
415 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
416
417 /*
418 * BAT5 128K Cacheable, non-guarded
419 * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory)
420 */
421 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\
422 BATL_PP_RW |\
423 BATL_MEMCOHERENCE)
424 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\
425 BATU_BL_128K |\
426 BATU_VS |\
427 BATU_VP)
428 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
429 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
430
431 /*
432 * BAT6 256M Cache-inhibited, guarded
433 * 0xf000_0000 256M FLASH
434 */
435 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\
436 BATL_PP_RW |\
437 BATL_CACHEINHIBIT |\
438 BATL_GUARDEDSTORAGE)
439 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\
440 BATU_BL_256M |\
441 BATU_VS |\
442 BATU_VP)
443 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\
444 BATL_PP_RW |\
445 BATL_MEMCOHERENCE)
446 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
447
448 /* Map the last 1M of flash where we're running from reset */
449 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
450 BATL_PP_RW |\
451 BATL_CACHEINHIBIT |\
452 BATL_GUARDEDSTORAGE)
453 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE |\
454 BATU_BL_1M |\
455 BATU_VS |\
456 BATU_VP)
457 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
458 BATL_PP_RW |\
459 BATL_MEMCOHERENCE)
460 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
461
462 /*
463 * BAT7 64M Cache-inhibited, guarded
464 * 0xe800_0000 64K NAND FLASH
465 * 0xe804_0000 128K DUART Registers
466 */
467 #define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\
468 BATL_PP_RW |\
469 BATL_CACHEINHIBIT |\
470 BATL_GUARDEDSTORAGE)
471 #define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\
472 BATU_BL_512K |\
473 BATU_VS |\
474 BATU_VP)
475 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\
476 BATL_PP_RW |\
477 BATL_CACHEINHIBIT)
478 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
479
480 /*
481 * Miscellaneous configurable options
482 */
483 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
484 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
485 #define CONFIG_PREBOOT /* enable preboot variable */
486 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
487
488 /*
489 * For booting Linux, the board info and command line data
490 * have to be in the first 16 MB of memory, since this is
491 * the maximum mapped by the Linux kernel during initialization.
492 */
493 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
494 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
495
496 /*
497 * Environment Configuration
498 */
499 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
500 #define CONFIG_ENV_SIZE 0x8000
501 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
502
503 /*
504 * Flash memory map:
505 * fffc0000 - ffffffff Pri FDT (256KB)
506 * fff80000 - fffbffff Pri U-Boot Environment (256 KB)
507 * fff00000 - fff7ffff Pri U-Boot (512 KB)
508 * fef00000 - ffefffff Pri OS image (16MB)
509 * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
510 *
511 * f7fc0000 - f7ffffff Sec FDT (256KB)
512 * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB)
513 * f7f00000 - f7f7ffff Sec U-Boot (512 KB)
514 * f6f00000 - f7efffff Sec OS image (16MB)
515 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
516 */
517 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff00000)
518 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f00000)
519 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfffc0000)
520 #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7fc0000)
521 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
522 #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
523
524 #define CONFIG_PROG_UBOOT1 \
525 "$download_cmd $loadaddr $ubootfile; " \
526 "if test $? -eq 0; then " \
527 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
528 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
529 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
530 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
531 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
532 "if test $? -ne 0; then " \
533 "echo PROGRAM FAILED; " \
534 "else; " \
535 "echo PROGRAM SUCCEEDED; " \
536 "fi; " \
537 "else; " \
538 "echo DOWNLOAD FAILED; " \
539 "fi;"
540
541 #define CONFIG_PROG_UBOOT2 \
542 "$download_cmd $loadaddr $ubootfile; " \
543 "if test $? -eq 0; then " \
544 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
545 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
546 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
547 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
548 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
549 "if test $? -ne 0; then " \
550 "echo PROGRAM FAILED; " \
551 "else; " \
552 "echo PROGRAM SUCCEEDED; " \
553 "fi; " \
554 "else; " \
555 "echo DOWNLOAD FAILED; " \
556 "fi;"
557
558 #define CONFIG_BOOT_OS_NET \
559 "$download_cmd $osaddr $osfile; " \
560 "if test $? -eq 0; then " \
561 "if test -n $fdtaddr; then " \
562 "$download_cmd $fdtaddr $fdtfile; " \
563 "if test $? -eq 0; then " \
564 "bootm $osaddr - $fdtaddr; " \
565 "else; " \
566 "echo FDT DOWNLOAD FAILED; " \
567 "fi; " \
568 "else; " \
569 "bootm $osaddr; " \
570 "fi; " \
571 "else; " \
572 "echo OS DOWNLOAD FAILED; " \
573 "fi;"
574
575 #define CONFIG_PROG_OS1 \
576 "$download_cmd $osaddr $osfile; " \
577 "if test $? -eq 0; then " \
578 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
579 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
580 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
581 "if test $? -ne 0; then " \
582 "echo OS PROGRAM FAILED; " \
583 "else; " \
584 "echo OS PROGRAM SUCCEEDED; " \
585 "fi; " \
586 "else; " \
587 "echo OS DOWNLOAD FAILED; " \
588 "fi;"
589
590 #define CONFIG_PROG_OS2 \
591 "$download_cmd $osaddr $osfile; " \
592 "if test $? -eq 0; then " \
593 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
594 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
595 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
596 "if test $? -ne 0; then " \
597 "echo OS PROGRAM FAILED; " \
598 "else; " \
599 "echo OS PROGRAM SUCCEEDED; " \
600 "fi; " \
601 "else; " \
602 "echo OS DOWNLOAD FAILED; " \
603 "fi;"
604
605 #define CONFIG_PROG_FDT1 \
606 "$download_cmd $fdtaddr $fdtfile; " \
607 "if test $? -eq 0; then " \
608 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
609 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
610 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
611 "if test $? -ne 0; then " \
612 "echo FDT PROGRAM FAILED; " \
613 "else; " \
614 "echo FDT PROGRAM SUCCEEDED; " \
615 "fi; " \
616 "else; " \
617 "echo FDT DOWNLOAD FAILED; " \
618 "fi;"
619
620 #define CONFIG_PROG_FDT2 \
621 "$download_cmd $fdtaddr $fdtfile; " \
622 "if test $? -eq 0; then " \
623 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
624 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
625 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
626 "if test $? -ne 0; then " \
627 "echo FDT PROGRAM FAILED; " \
628 "else; " \
629 "echo FDT PROGRAM SUCCEEDED; " \
630 "fi; " \
631 "else; " \
632 "echo FDT DOWNLOAD FAILED; " \
633 "fi;"
634
635 #define CONFIG_EXTRA_ENV_SETTINGS \
636 "autoload=yes\0" \
637 "download_cmd=tftp\0" \
638 "console_args=console=ttyS0,115200\0" \
639 "root_args=root=/dev/nfs rw\0" \
640 "misc_args=ip=on\0" \
641 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
642 "bootfile=/home/user/file\0" \
643 "osfile=/home/user/board.uImage\0" \
644 "fdtfile=/home/user/board.dtb\0" \
645 "ubootfile=/home/user/u-boot.bin\0" \
646 "fdtaddr=0x1e00000\0" \
647 "osaddr=0x1000000\0" \
648 "loadaddr=0x1000000\0" \
649 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
650 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
651 "prog_os1="CONFIG_PROG_OS1"\0" \
652 "prog_os2="CONFIG_PROG_OS2"\0" \
653 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
654 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
655 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
656 "bootcmd_flash1=run set_bootargs; " \
657 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
658 "bootcmd_flash2=run set_bootargs; " \
659 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
660 "bootcmd=run bootcmd_flash1\0"
661 #endif /* __CONFIG_H */
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