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Kconfig: Drop CONFIG_CMD_DS4510
[people/ms/u-boot.git] / include / configs / xpedite517x.h
1 /*
2 * Copyright 2009 Extreme Engineering Solutions, Inc.
3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 /*
9 * xpedite517x board configuration file
10 */
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 /*
15 * High Level Configuration Options
16 */
17 #define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */
18 #define CONFIG_SYS_BOARD_NAME "XPedite5170"
19 #define CONFIG_SYS_FORM_3U_VPX 1
20 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
21 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
22 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */
23 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
24 #define CONFIG_ALTIVEC 1
25
26 #define CONFIG_SYS_TEXT_BASE 0xfff00000
27
28 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
29 #define CONFIG_PCIE1 1 /* PCIE controller 1 */
30 #define CONFIG_PCIE2 1 /* PCIE controller 2 */
31 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
32 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
33 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
34
35 /*
36 * DDR config
37 */
38 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
39 #define CONFIG_DDR_SPD
40 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
41 #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
42 #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
43 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
44 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
45 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
46 #define CONFIG_DDR_ECC
47 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
48 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
49 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
50 #define CONFIG_VERY_BIG_RAM
51 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
52
53 /*
54 * virtual address to be used for temporary mappings. There
55 * should be 128k free at this VA.
56 */
57 #define CONFIG_SYS_SCRATCH_VA 0xe0000000
58
59 #ifndef __ASSEMBLY__
60 extern unsigned long get_board_sys_clk(unsigned long dummy);
61 #endif
62
63 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */
64
65 /*
66 * L2CR setup
67 */
68 #define CONFIG_SYS_L2
69 #define L2_INIT 0
70 #define L2_ENABLE (L2CR_L2E)
71
72 /*
73 * Base addresses -- Note these are effective addresses where the
74 * actual resources get mapped (not physical addresses)
75 */
76 #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
77 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
78 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
79 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
80 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
81
82 /*
83 * Diagnostics
84 */
85 #define CONFIG_SYS_ALT_MEMTEST
86 #define CONFIG_SYS_MEMTEST_START 0x10000000
87 #define CONFIG_SYS_MEMTEST_END 0x20000000
88 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\
89 CONFIG_SYS_POST_I2C)
90 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_DS1621_ADDR, \
91 CONFIG_SYS_I2C_DS4510_ADDR, \
92 CONFIG_SYS_I2C_EEPROM_ADDR, \
93 CONFIG_SYS_I2C_LM90_ADDR, \
94 CONFIG_SYS_I2C_PCA9553_ADDR, \
95 CONFIG_SYS_I2C_PCA953X_ADDR0, \
96 CONFIG_SYS_I2C_PCA953X_ADDR1, \
97 CONFIG_SYS_I2C_PCA953X_ADDR2, \
98 CONFIG_SYS_I2C_PCA953X_ADDR3, \
99 CONFIG_SYS_I2C_PEX8518_ADDR, \
100 CONFIG_SYS_I2C_RTC_ADDR}
101 /* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
102 #define I2C_ADDR_IGNORE_LIST {0x50}
103
104 /*
105 * Memory map
106 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
107 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
108 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
109 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
110 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
111 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
112 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
113 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
114 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
115 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
116 */
117
118 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
119
120 /*
121 * NAND flash configuration
122 */
123 #define CONFIG_SYS_NAND_BASE 0xef800000
124 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
125 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
126 #define CONFIG_SYS_MAX_NAND_DEVICE 2
127 #define CONFIG_NAND_ACTL
128 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */
129 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */
130 #define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */
131 #define CONFIG_SYS_NAND_ACTL_DELAY 25
132 #define CONFIG_JFFS2_NAND
133
134 /*
135 * NOR flash configuration
136 */
137 #define CONFIG_SYS_FLASH_BASE 0xf8000000
138 #define CONFIG_SYS_FLASH_BASE2 0xf0000000
139 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
140 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
141 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
142 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
143 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
144 #define CONFIG_FLASH_CFI_DRIVER
145 #define CONFIG_SYS_FLASH_CFI
146 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
147 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \
148 {0xf7f00000, 0xc0000} }
149 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
150 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
151
152 /*
153 * Chip select configuration
154 */
155 /* NOR Flash 0 on CS0 */
156 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
157 BR_PS_16 |\
158 BR_V)
159 #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\
160 OR_GPCM_CSNT |\
161 OR_GPCM_XACS |\
162 OR_GPCM_ACS_DIV2 |\
163 OR_GPCM_SCY_8 |\
164 OR_GPCM_TRLX |\
165 OR_GPCM_EHTR |\
166 OR_GPCM_EAD)
167
168 /* NOR Flash 1 on CS1 */
169 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\
170 BR_PS_16 |\
171 BR_V)
172 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
173
174 /* NAND flash on CS2 */
175 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\
176 BR_PS_8 |\
177 BR_V)
178 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\
179 OR_GPCM_BCTLD |\
180 OR_GPCM_CSNT |\
181 OR_GPCM_ACS_DIV4 |\
182 OR_GPCM_SCY_4 |\
183 OR_GPCM_TRLX |\
184 OR_GPCM_EHTR)
185
186 /* Optional NAND flash on CS3 */
187 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\
188 BR_PS_8 |\
189 BR_V)
190 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
191
192 /*
193 * Use L1 as initial stack
194 */
195 #define CONFIG_SYS_INIT_RAM_LOCK 1
196 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
197 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
198
199 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
200 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
201
202 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
203 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
204
205 /*
206 * Serial Port
207 */
208 #define CONFIG_CONS_INDEX 1
209 #define CONFIG_SYS_NS16550_SERIAL
210 #define CONFIG_SYS_NS16550_REG_SIZE 1
211 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
212 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
213 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
214 #define CONFIG_SYS_BAUDRATE_TABLE \
215 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
216 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
217 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
218
219 /*
220 * I2C
221 */
222 #define CONFIG_SYS_I2C
223 #define CONFIG_SYS_I2C_FSL
224 #define CONFIG_SYS_FSL_I2C_SPEED 100000
225 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
226 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
227 #define CONFIG_SYS_FSL_I2C2_SPEED 100000
228 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
229 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
230
231 /* PEX8518 slave I2C interface */
232 #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
233
234 /* I2C DS1631 temperature sensor */
235 #define CONFIG_SYS_I2C_DS1621_ADDR 0x48
236 #define CONFIG_DTT_DS1621
237 #define CONFIG_DTT_SENSORS { 0 }
238 #define CONFIG_SYS_I2C_LM90_ADDR 0x4c
239
240 /* I2C EEPROM - AT24C128B */
241 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
242 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
243 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
244 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
245
246 /* I2C RTC */
247 #define CONFIG_RTC_M41T11 1
248 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
249 #define CONFIG_SYS_M41T11_BASE_YEAR 2000
250
251 /* GPIO/EEPROM/SRAM */
252 #define CONFIG_DS4510
253 #define CONFIG_SYS_I2C_DS4510_ADDR 0x51
254
255 /* GPIO */
256 #define CONFIG_PCA953X
257 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
258 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
259 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
260 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
261 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
262 #define CONFIG_SYS_I2C_PCA9553_ADDR 0x62
263
264 /*
265 * PU = pulled high, PD = pulled low
266 * I = input, O = output, IO = input/output
267 */
268 /* PCA9557 @ 0x18*/
269 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
270 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
271 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
272 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
273 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
274 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
275
276 /* PCA9557 @ 0x1c*/
277 #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
278 #define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */
279 #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
280 #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
281 #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
282 #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
283 #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
284 #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
285
286 /* PCA9557 @ 0x1e*/
287 #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
288 #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
289 #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
290 #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
291 #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
292 #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */
293 #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */
294
295 /* PCA9557 @ 0x1f */
296 #define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */
297 #define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */
298 #define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */
299 #define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */
300
301 /*
302 * General PCI
303 * Memory space is mapped 1-1, but I/O space must start from 0.
304 */
305 /* PCIE1 - PEX8518 */
306 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
307 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
308 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
309 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
310 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
311 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
312
313 /* PCIE2 - VPX P1 */
314 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
315 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
316 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
317 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
318 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
319 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
320
321 /*
322 * Networking options
323 */
324 #define CONFIG_TSEC_ENET /* tsec ethernet support */
325 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
326 #define CONFIG_MII 1 /* MII PHY management */
327 #define CONFIG_ETHPRIME "eTSEC1"
328
329 #define CONFIG_TSEC1 1
330 #define CONFIG_TSEC1_NAME "eTSEC1"
331 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
332 #define TSEC1_PHY_ADDR 1
333 #define TSEC1_PHYIDX 0
334 #define CONFIG_HAS_ETH0
335
336 #define CONFIG_TSEC2 1
337 #define CONFIG_TSEC2_NAME "eTSEC2"
338 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
339 #define TSEC2_PHY_ADDR 2
340 #define TSEC2_PHYIDX 0
341 #define CONFIG_HAS_ETH1
342
343 /*
344 * BAT mappings
345 */
346 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
347 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
348 BATL_PP_RW |\
349 BATL_CACHEINHIBIT |\
350 BATL_GUARDEDSTORAGE)
351 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\
352 BATU_BL_1M |\
353 BATU_VS |\
354 BATU_VP)
355 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
356 BATL_PP_RW |\
357 BATL_CACHEINHIBIT)
358 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
359 #endif
360
361 /*
362 * BAT0 2G Cacheable, non-guarded
363 * 0x0000_0000 2G DDR
364 */
365 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
366 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
367 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
368 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
369
370 /*
371 * BAT1 1G Cache-inhibited, guarded
372 * 0x8000_0000 1G PCI-Express 1 Memory
373 */
374 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
375 BATL_PP_RW |\
376 BATL_CACHEINHIBIT |\
377 BATL_GUARDEDSTORAGE)
378 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\
379 BATU_BL_1G |\
380 BATU_VS |\
381 BATU_VP)
382 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
383 BATL_PP_RW |\
384 BATL_CACHEINHIBIT)
385 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
386
387 /*
388 * BAT2 512M Cache-inhibited, guarded
389 * 0xc000_0000 512M PCI-Express 2 Memory
390 */
391 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
392 BATL_PP_RW |\
393 BATL_CACHEINHIBIT |\
394 BATL_GUARDEDSTORAGE)
395 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\
396 BATU_BL_512M |\
397 BATU_VS |\
398 BATU_VP)
399 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
400 BATL_PP_RW |\
401 BATL_CACHEINHIBIT)
402 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
403
404 /*
405 * BAT3 1M Cache-inhibited, guarded
406 * 0xe000_0000 1M CCSR
407 */
408 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\
409 BATL_PP_RW |\
410 BATL_CACHEINHIBIT |\
411 BATL_GUARDEDSTORAGE)
412 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\
413 BATU_BL_1M |\
414 BATU_VS |\
415 BATU_VP)
416 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\
417 BATL_PP_RW |\
418 BATL_CACHEINHIBIT)
419 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
420
421 /*
422 * BAT4 32M Cache-inhibited, guarded
423 * 0xe200_0000 16M PCI-Express 1 I/O
424 * 0xe300_0000 16M PCI-Express 2 I/0
425 */
426 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
427 BATL_PP_RW |\
428 BATL_CACHEINHIBIT |\
429 BATL_GUARDEDSTORAGE)
430 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\
431 BATU_BL_32M |\
432 BATU_VS |\
433 BATU_VP)
434 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
435 BATL_PP_RW |\
436 BATL_CACHEINHIBIT)
437 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
438
439 /*
440 * BAT5 128K Cacheable, non-guarded
441 * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory)
442 */
443 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\
444 BATL_PP_RW |\
445 BATL_MEMCOHERENCE)
446 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\
447 BATU_BL_128K |\
448 BATU_VS |\
449 BATU_VP)
450 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
451 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
452
453 /*
454 * BAT6 256M Cache-inhibited, guarded
455 * 0xf000_0000 256M FLASH
456 */
457 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\
458 BATL_PP_RW |\
459 BATL_CACHEINHIBIT |\
460 BATL_GUARDEDSTORAGE)
461 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\
462 BATU_BL_256M |\
463 BATU_VS |\
464 BATU_VP)
465 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\
466 BATL_PP_RW |\
467 BATL_MEMCOHERENCE)
468 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
469
470 /* Map the last 1M of flash where we're running from reset */
471 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
472 BATL_PP_RW |\
473 BATL_CACHEINHIBIT |\
474 BATL_GUARDEDSTORAGE)
475 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE |\
476 BATU_BL_1M |\
477 BATU_VS |\
478 BATU_VP)
479 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
480 BATL_PP_RW |\
481 BATL_MEMCOHERENCE)
482 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
483
484 /*
485 * BAT7 64M Cache-inhibited, guarded
486 * 0xe800_0000 64K NAND FLASH
487 * 0xe804_0000 128K DUART Registers
488 */
489 #define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\
490 BATL_PP_RW |\
491 BATL_CACHEINHIBIT |\
492 BATL_GUARDEDSTORAGE)
493 #define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\
494 BATU_BL_512K |\
495 BATU_VS |\
496 BATU_VP)
497 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\
498 BATL_PP_RW |\
499 BATL_CACHEINHIBIT)
500 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
501
502 /*
503 * Command configuration.
504 */
505 #define CONFIG_CMD_DTT
506 #define CONFIG_CMD_EEPROM
507 #define CONFIG_CMD_IRQ
508 #define CONFIG_CMD_JFFS2
509 #define CONFIG_CMD_NAND
510 #define CONFIG_CMD_PCA953X
511 #define CONFIG_CMD_PCA953X_INFO
512 #define CONFIG_CMD_PCI
513 #define CONFIG_CMD_PCI_ENUM
514 #define CONFIG_CMD_REGINFO
515
516 /*
517 * Miscellaneous configurable options
518 */
519 #define CONFIG_SYS_LONGHELP /* undef to save memory */
520 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
521 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
522 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
523 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
524 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
525 #define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */
526 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
527 #define CONFIG_PANIC_HANG /* do not reset board on panic */
528 #define CONFIG_PREBOOT /* enable preboot variable */
529 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
530
531 /*
532 * For booting Linux, the board info and command line data
533 * have to be in the first 16 MB of memory, since this is
534 * the maximum mapped by the Linux kernel during initialization.
535 */
536 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
537 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
538
539 /*
540 * Environment Configuration
541 */
542 #define CONFIG_ENV_IS_IN_FLASH 1
543 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
544 #define CONFIG_ENV_SIZE 0x8000
545 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
546
547 /*
548 * Flash memory map:
549 * fffc0000 - ffffffff Pri FDT (256KB)
550 * fff80000 - fffbffff Pri U-Boot Environment (256 KB)
551 * fff00000 - fff7ffff Pri U-Boot (512 KB)
552 * fef00000 - ffefffff Pri OS image (16MB)
553 * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
554 *
555 * f7fc0000 - f7ffffff Sec FDT (256KB)
556 * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB)
557 * f7f00000 - f7f7ffff Sec U-Boot (512 KB)
558 * f6f00000 - f7efffff Sec OS image (16MB)
559 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
560 */
561 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff00000)
562 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f00000)
563 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfffc0000)
564 #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7fc0000)
565 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
566 #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
567
568 #define CONFIG_PROG_UBOOT1 \
569 "$download_cmd $loadaddr $ubootfile; " \
570 "if test $? -eq 0; then " \
571 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
572 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
573 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
574 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
575 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
576 "if test $? -ne 0; then " \
577 "echo PROGRAM FAILED; " \
578 "else; " \
579 "echo PROGRAM SUCCEEDED; " \
580 "fi; " \
581 "else; " \
582 "echo DOWNLOAD FAILED; " \
583 "fi;"
584
585 #define CONFIG_PROG_UBOOT2 \
586 "$download_cmd $loadaddr $ubootfile; " \
587 "if test $? -eq 0; then " \
588 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
589 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
590 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
591 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
592 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
593 "if test $? -ne 0; then " \
594 "echo PROGRAM FAILED; " \
595 "else; " \
596 "echo PROGRAM SUCCEEDED; " \
597 "fi; " \
598 "else; " \
599 "echo DOWNLOAD FAILED; " \
600 "fi;"
601
602 #define CONFIG_BOOT_OS_NET \
603 "$download_cmd $osaddr $osfile; " \
604 "if test $? -eq 0; then " \
605 "if test -n $fdtaddr; then " \
606 "$download_cmd $fdtaddr $fdtfile; " \
607 "if test $? -eq 0; then " \
608 "bootm $osaddr - $fdtaddr; " \
609 "else; " \
610 "echo FDT DOWNLOAD FAILED; " \
611 "fi; " \
612 "else; " \
613 "bootm $osaddr; " \
614 "fi; " \
615 "else; " \
616 "echo OS DOWNLOAD FAILED; " \
617 "fi;"
618
619 #define CONFIG_PROG_OS1 \
620 "$download_cmd $osaddr $osfile; " \
621 "if test $? -eq 0; then " \
622 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
623 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
624 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
625 "if test $? -ne 0; then " \
626 "echo OS PROGRAM FAILED; " \
627 "else; " \
628 "echo OS PROGRAM SUCCEEDED; " \
629 "fi; " \
630 "else; " \
631 "echo OS DOWNLOAD FAILED; " \
632 "fi;"
633
634 #define CONFIG_PROG_OS2 \
635 "$download_cmd $osaddr $osfile; " \
636 "if test $? -eq 0; then " \
637 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
638 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
639 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
640 "if test $? -ne 0; then " \
641 "echo OS PROGRAM FAILED; " \
642 "else; " \
643 "echo OS PROGRAM SUCCEEDED; " \
644 "fi; " \
645 "else; " \
646 "echo OS DOWNLOAD FAILED; " \
647 "fi;"
648
649 #define CONFIG_PROG_FDT1 \
650 "$download_cmd $fdtaddr $fdtfile; " \
651 "if test $? -eq 0; then " \
652 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
653 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
654 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
655 "if test $? -ne 0; then " \
656 "echo FDT PROGRAM FAILED; " \
657 "else; " \
658 "echo FDT PROGRAM SUCCEEDED; " \
659 "fi; " \
660 "else; " \
661 "echo FDT DOWNLOAD FAILED; " \
662 "fi;"
663
664 #define CONFIG_PROG_FDT2 \
665 "$download_cmd $fdtaddr $fdtfile; " \
666 "if test $? -eq 0; then " \
667 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
668 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
669 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
670 "if test $? -ne 0; then " \
671 "echo FDT PROGRAM FAILED; " \
672 "else; " \
673 "echo FDT PROGRAM SUCCEEDED; " \
674 "fi; " \
675 "else; " \
676 "echo FDT DOWNLOAD FAILED; " \
677 "fi;"
678
679 #define CONFIG_EXTRA_ENV_SETTINGS \
680 "autoload=yes\0" \
681 "download_cmd=tftp\0" \
682 "console_args=console=ttyS0,115200\0" \
683 "root_args=root=/dev/nfs rw\0" \
684 "misc_args=ip=on\0" \
685 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
686 "bootfile=/home/user/file\0" \
687 "osfile=/home/user/board.uImage\0" \
688 "fdtfile=/home/user/board.dtb\0" \
689 "ubootfile=/home/user/u-boot.bin\0" \
690 "fdtaddr=0x1e00000\0" \
691 "osaddr=0x1000000\0" \
692 "loadaddr=0x1000000\0" \
693 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
694 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
695 "prog_os1="CONFIG_PROG_OS1"\0" \
696 "prog_os2="CONFIG_PROG_OS2"\0" \
697 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
698 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
699 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
700 "bootcmd_flash1=run set_bootargs; " \
701 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
702 "bootcmd_flash2=run set_bootargs; " \
703 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
704 "bootcmd=run bootcmd_flash1\0"
705 #endif /* __CONFIG_H */
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