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[people/ms/u-boot.git] / include / configs / xpedite517x.h
1 /*
2 * Copyright 2009 Extreme Engineering Solutions, Inc.
3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 /*
9 * xpedite517x board configuration file
10 */
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 /*
15 * High Level Configuration Options
16 */
17 #define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */
18 #define CONFIG_SYS_BOARD_NAME "XPedite5170"
19 #define CONFIG_SYS_FORM_3U_VPX 1
20 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
21 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
22 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */
23 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
24 #define CONFIG_ALTIVEC 1
25
26 #define CONFIG_SYS_TEXT_BASE 0xfff00000
27
28 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
29 #define CONFIG_PCIE1 1 /* PCIE controller 1 */
30 #define CONFIG_PCIE2 1 /* PCIE controller 2 */
31 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
32 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
33 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
34
35 /*
36 * DDR config
37 */
38 #define CONFIG_SYS_FSL_DDR2
39 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
40 #define CONFIG_DDR_SPD
41 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
42 #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
43 #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
44 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
45 #define CONFIG_NUM_DDR_CONTROLLERS 2
46 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
47 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
48 #define CONFIG_DDR_ECC
49 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
50 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
51 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
52 #define CONFIG_VERY_BIG_RAM
53 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
54
55 /*
56 * virtual address to be used for temporary mappings. There
57 * should be 128k free at this VA.
58 */
59 #define CONFIG_SYS_SCRATCH_VA 0xe0000000
60
61 #ifndef __ASSEMBLY__
62 extern unsigned long get_board_sys_clk(unsigned long dummy);
63 #endif
64
65 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */
66
67 /*
68 * L2CR setup
69 */
70 #define CONFIG_SYS_L2
71 #define L2_INIT 0
72 #define L2_ENABLE (L2CR_L2E)
73
74 /*
75 * Base addresses -- Note these are effective addresses where the
76 * actual resources get mapped (not physical addresses)
77 */
78 #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
79 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
80 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
81 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
82 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
83
84 /*
85 * Diagnostics
86 */
87 #define CONFIG_SYS_ALT_MEMTEST
88 #define CONFIG_SYS_MEMTEST_START 0x10000000
89 #define CONFIG_SYS_MEMTEST_END 0x20000000
90 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\
91 CONFIG_SYS_POST_I2C)
92 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_DS1621_ADDR, \
93 CONFIG_SYS_I2C_DS4510_ADDR, \
94 CONFIG_SYS_I2C_EEPROM_ADDR, \
95 CONFIG_SYS_I2C_LM90_ADDR, \
96 CONFIG_SYS_I2C_PCA9553_ADDR, \
97 CONFIG_SYS_I2C_PCA953X_ADDR0, \
98 CONFIG_SYS_I2C_PCA953X_ADDR1, \
99 CONFIG_SYS_I2C_PCA953X_ADDR2, \
100 CONFIG_SYS_I2C_PCA953X_ADDR3, \
101 CONFIG_SYS_I2C_PEX8518_ADDR, \
102 CONFIG_SYS_I2C_RTC_ADDR}
103 /* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
104 #define I2C_ADDR_IGNORE_LIST {0x50}
105
106 /*
107 * Memory map
108 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
109 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
110 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
111 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
112 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
113 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
114 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
115 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
116 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
117 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
118 */
119
120 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
121
122 /*
123 * NAND flash configuration
124 */
125 #define CONFIG_SYS_NAND_BASE 0xef800000
126 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
127 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
128 #define CONFIG_SYS_MAX_NAND_DEVICE 2
129 #define CONFIG_NAND_ACTL
130 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */
131 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */
132 #define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */
133 #define CONFIG_SYS_NAND_ACTL_DELAY 25
134 #define CONFIG_JFFS2_NAND
135
136 /*
137 * NOR flash configuration
138 */
139 #define CONFIG_SYS_FLASH_BASE 0xf8000000
140 #define CONFIG_SYS_FLASH_BASE2 0xf0000000
141 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
142 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
143 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
144 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
145 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
146 #define CONFIG_FLASH_CFI_DRIVER
147 #define CONFIG_SYS_FLASH_CFI
148 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
149 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \
150 {0xf7f00000, 0xc0000} }
151 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
152 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
153
154 /*
155 * Chip select configuration
156 */
157 /* NOR Flash 0 on CS0 */
158 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
159 BR_PS_16 |\
160 BR_V)
161 #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\
162 OR_GPCM_CSNT |\
163 OR_GPCM_XACS |\
164 OR_GPCM_ACS_DIV2 |\
165 OR_GPCM_SCY_8 |\
166 OR_GPCM_TRLX |\
167 OR_GPCM_EHTR |\
168 OR_GPCM_EAD)
169
170 /* NOR Flash 1 on CS1 */
171 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\
172 BR_PS_16 |\
173 BR_V)
174 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
175
176 /* NAND flash on CS2 */
177 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\
178 BR_PS_8 |\
179 BR_V)
180 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\
181 OR_GPCM_BCTLD |\
182 OR_GPCM_CSNT |\
183 OR_GPCM_ACS_DIV4 |\
184 OR_GPCM_SCY_4 |\
185 OR_GPCM_TRLX |\
186 OR_GPCM_EHTR)
187
188 /* Optional NAND flash on CS3 */
189 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\
190 BR_PS_8 |\
191 BR_V)
192 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
193
194 /*
195 * Use L1 as initial stack
196 */
197 #define CONFIG_SYS_INIT_RAM_LOCK 1
198 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
199 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
200
201 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
202 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
203
204 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
205 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
206
207 /*
208 * Serial Port
209 */
210 #define CONFIG_CONS_INDEX 1
211 #define CONFIG_SYS_NS16550_SERIAL
212 #define CONFIG_SYS_NS16550_REG_SIZE 1
213 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
214 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
215 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
216 #define CONFIG_SYS_BAUDRATE_TABLE \
217 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
218 #define CONFIG_BAUDRATE 115200
219 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
220 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
221
222 /*
223 * I2C
224 */
225 #define CONFIG_SYS_I2C
226 #define CONFIG_SYS_I2C_FSL
227 #define CONFIG_SYS_FSL_I2C_SPEED 100000
228 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
229 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
230 #define CONFIG_SYS_FSL_I2C2_SPEED 100000
231 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
232 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
233
234 /* PEX8518 slave I2C interface */
235 #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
236
237 /* I2C DS1631 temperature sensor */
238 #define CONFIG_SYS_I2C_DS1621_ADDR 0x48
239 #define CONFIG_DTT_DS1621
240 #define CONFIG_DTT_SENSORS { 0 }
241 #define CONFIG_SYS_I2C_LM90_ADDR 0x4c
242
243 /* I2C EEPROM - AT24C128B */
244 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
245 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
246 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
247 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
248
249 /* I2C RTC */
250 #define CONFIG_RTC_M41T11 1
251 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
252 #define CONFIG_SYS_M41T11_BASE_YEAR 2000
253
254 /* GPIO/EEPROM/SRAM */
255 #define CONFIG_DS4510
256 #define CONFIG_SYS_I2C_DS4510_ADDR 0x51
257
258 /* GPIO */
259 #define CONFIG_PCA953X
260 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
261 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
262 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
263 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
264 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
265 #define CONFIG_SYS_I2C_PCA9553_ADDR 0x62
266
267 /*
268 * PU = pulled high, PD = pulled low
269 * I = input, O = output, IO = input/output
270 */
271 /* PCA9557 @ 0x18*/
272 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
273 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
274 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
275 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
276 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
277 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
278
279 /* PCA9557 @ 0x1c*/
280 #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
281 #define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */
282 #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
283 #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
284 #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
285 #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
286 #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
287 #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
288
289 /* PCA9557 @ 0x1e*/
290 #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
291 #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
292 #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
293 #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
294 #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
295 #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */
296 #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */
297
298 /* PCA9557 @ 0x1f */
299 #define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */
300 #define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */
301 #define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */
302 #define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */
303
304 /*
305 * General PCI
306 * Memory space is mapped 1-1, but I/O space must start from 0.
307 */
308 /* PCIE1 - PEX8518 */
309 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
310 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
311 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
312 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
313 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
314 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
315
316 /* PCIE2 - VPX P1 */
317 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
318 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
319 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
320 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
321 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
322 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
323
324 /*
325 * Networking options
326 */
327 #define CONFIG_TSEC_ENET /* tsec ethernet support */
328 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
329 #define CONFIG_MII 1 /* MII PHY management */
330 #define CONFIG_ETHPRIME "eTSEC1"
331
332 #define CONFIG_TSEC1 1
333 #define CONFIG_TSEC1_NAME "eTSEC1"
334 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
335 #define TSEC1_PHY_ADDR 1
336 #define TSEC1_PHYIDX 0
337 #define CONFIG_HAS_ETH0
338
339 #define CONFIG_TSEC2 1
340 #define CONFIG_TSEC2_NAME "eTSEC2"
341 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
342 #define TSEC2_PHY_ADDR 2
343 #define TSEC2_PHYIDX 0
344 #define CONFIG_HAS_ETH1
345
346 /*
347 * BAT mappings
348 */
349 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
350 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
351 BATL_PP_RW |\
352 BATL_CACHEINHIBIT |\
353 BATL_GUARDEDSTORAGE)
354 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\
355 BATU_BL_1M |\
356 BATU_VS |\
357 BATU_VP)
358 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
359 BATL_PP_RW |\
360 BATL_CACHEINHIBIT)
361 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
362 #endif
363
364 /*
365 * BAT0 2G Cacheable, non-guarded
366 * 0x0000_0000 2G DDR
367 */
368 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
369 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
370 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
371 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
372
373 /*
374 * BAT1 1G Cache-inhibited, guarded
375 * 0x8000_0000 1G PCI-Express 1 Memory
376 */
377 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
378 BATL_PP_RW |\
379 BATL_CACHEINHIBIT |\
380 BATL_GUARDEDSTORAGE)
381 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\
382 BATU_BL_1G |\
383 BATU_VS |\
384 BATU_VP)
385 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
386 BATL_PP_RW |\
387 BATL_CACHEINHIBIT)
388 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
389
390 /*
391 * BAT2 512M Cache-inhibited, guarded
392 * 0xc000_0000 512M PCI-Express 2 Memory
393 */
394 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
395 BATL_PP_RW |\
396 BATL_CACHEINHIBIT |\
397 BATL_GUARDEDSTORAGE)
398 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\
399 BATU_BL_512M |\
400 BATU_VS |\
401 BATU_VP)
402 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
403 BATL_PP_RW |\
404 BATL_CACHEINHIBIT)
405 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
406
407 /*
408 * BAT3 1M Cache-inhibited, guarded
409 * 0xe000_0000 1M CCSR
410 */
411 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\
412 BATL_PP_RW |\
413 BATL_CACHEINHIBIT |\
414 BATL_GUARDEDSTORAGE)
415 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\
416 BATU_BL_1M |\
417 BATU_VS |\
418 BATU_VP)
419 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\
420 BATL_PP_RW |\
421 BATL_CACHEINHIBIT)
422 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
423
424 /*
425 * BAT4 32M Cache-inhibited, guarded
426 * 0xe200_0000 16M PCI-Express 1 I/O
427 * 0xe300_0000 16M PCI-Express 2 I/0
428 */
429 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
430 BATL_PP_RW |\
431 BATL_CACHEINHIBIT |\
432 BATL_GUARDEDSTORAGE)
433 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\
434 BATU_BL_32M |\
435 BATU_VS |\
436 BATU_VP)
437 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
438 BATL_PP_RW |\
439 BATL_CACHEINHIBIT)
440 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
441
442 /*
443 * BAT5 128K Cacheable, non-guarded
444 * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory)
445 */
446 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\
447 BATL_PP_RW |\
448 BATL_MEMCOHERENCE)
449 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\
450 BATU_BL_128K |\
451 BATU_VS |\
452 BATU_VP)
453 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
454 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
455
456 /*
457 * BAT6 256M Cache-inhibited, guarded
458 * 0xf000_0000 256M FLASH
459 */
460 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\
461 BATL_PP_RW |\
462 BATL_CACHEINHIBIT |\
463 BATL_GUARDEDSTORAGE)
464 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\
465 BATU_BL_256M |\
466 BATU_VS |\
467 BATU_VP)
468 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\
469 BATL_PP_RW |\
470 BATL_MEMCOHERENCE)
471 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
472
473 /* Map the last 1M of flash where we're running from reset */
474 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
475 BATL_PP_RW |\
476 BATL_CACHEINHIBIT |\
477 BATL_GUARDEDSTORAGE)
478 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE |\
479 BATU_BL_1M |\
480 BATU_VS |\
481 BATU_VP)
482 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
483 BATL_PP_RW |\
484 BATL_MEMCOHERENCE)
485 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
486
487 /*
488 * BAT7 64M Cache-inhibited, guarded
489 * 0xe800_0000 64K NAND FLASH
490 * 0xe804_0000 128K DUART Registers
491 */
492 #define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\
493 BATL_PP_RW |\
494 BATL_CACHEINHIBIT |\
495 BATL_GUARDEDSTORAGE)
496 #define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\
497 BATU_BL_512K |\
498 BATU_VS |\
499 BATU_VP)
500 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\
501 BATL_PP_RW |\
502 BATL_CACHEINHIBIT)
503 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
504
505 /*
506 * Command configuration.
507 */
508 #define CONFIG_CMD_DATE
509 #define CONFIG_CMD_DS4510
510 #define CONFIG_CMD_DS4510_INFO
511 #define CONFIG_CMD_DTT
512 #define CONFIG_CMD_EEPROM
513 #define CONFIG_CMD_IRQ
514 #define CONFIG_CMD_JFFS2
515 #define CONFIG_CMD_NAND
516 #define CONFIG_CMD_PCA953X
517 #define CONFIG_CMD_PCA953X_INFO
518 #define CONFIG_CMD_PCI
519 #define CONFIG_CMD_PCI_ENUM
520 #define CONFIG_CMD_REGINFO
521
522 /*
523 * Miscellaneous configurable options
524 */
525 #define CONFIG_SYS_LONGHELP /* undef to save memory */
526 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
527 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
528 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
529 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
530 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
531 #define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */
532 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
533 #define CONFIG_PANIC_HANG /* do not reset board on panic */
534 #define CONFIG_PREBOOT /* enable preboot variable */
535 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
536
537 /*
538 * For booting Linux, the board info and command line data
539 * have to be in the first 16 MB of memory, since this is
540 * the maximum mapped by the Linux kernel during initialization.
541 */
542 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
543 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
544
545 /*
546 * Environment Configuration
547 */
548 #define CONFIG_ENV_IS_IN_FLASH 1
549 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
550 #define CONFIG_ENV_SIZE 0x8000
551 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
552
553 /*
554 * Flash memory map:
555 * fffc0000 - ffffffff Pri FDT (256KB)
556 * fff80000 - fffbffff Pri U-Boot Environment (256 KB)
557 * fff00000 - fff7ffff Pri U-Boot (512 KB)
558 * fef00000 - ffefffff Pri OS image (16MB)
559 * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
560 *
561 * f7fc0000 - f7ffffff Sec FDT (256KB)
562 * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB)
563 * f7f00000 - f7f7ffff Sec U-Boot (512 KB)
564 * f6f00000 - f7efffff Sec OS image (16MB)
565 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
566 */
567 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff00000)
568 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f00000)
569 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfffc0000)
570 #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7fc0000)
571 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
572 #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
573
574 #define CONFIG_PROG_UBOOT1 \
575 "$download_cmd $loadaddr $ubootfile; " \
576 "if test $? -eq 0; then " \
577 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
578 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
579 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
580 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
581 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
582 "if test $? -ne 0; then " \
583 "echo PROGRAM FAILED; " \
584 "else; " \
585 "echo PROGRAM SUCCEEDED; " \
586 "fi; " \
587 "else; " \
588 "echo DOWNLOAD FAILED; " \
589 "fi;"
590
591 #define CONFIG_PROG_UBOOT2 \
592 "$download_cmd $loadaddr $ubootfile; " \
593 "if test $? -eq 0; then " \
594 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
595 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
596 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
597 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
598 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
599 "if test $? -ne 0; then " \
600 "echo PROGRAM FAILED; " \
601 "else; " \
602 "echo PROGRAM SUCCEEDED; " \
603 "fi; " \
604 "else; " \
605 "echo DOWNLOAD FAILED; " \
606 "fi;"
607
608 #define CONFIG_BOOT_OS_NET \
609 "$download_cmd $osaddr $osfile; " \
610 "if test $? -eq 0; then " \
611 "if test -n $fdtaddr; then " \
612 "$download_cmd $fdtaddr $fdtfile; " \
613 "if test $? -eq 0; then " \
614 "bootm $osaddr - $fdtaddr; " \
615 "else; " \
616 "echo FDT DOWNLOAD FAILED; " \
617 "fi; " \
618 "else; " \
619 "bootm $osaddr; " \
620 "fi; " \
621 "else; " \
622 "echo OS DOWNLOAD FAILED; " \
623 "fi;"
624
625 #define CONFIG_PROG_OS1 \
626 "$download_cmd $osaddr $osfile; " \
627 "if test $? -eq 0; then " \
628 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
629 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
630 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
631 "if test $? -ne 0; then " \
632 "echo OS PROGRAM FAILED; " \
633 "else; " \
634 "echo OS PROGRAM SUCCEEDED; " \
635 "fi; " \
636 "else; " \
637 "echo OS DOWNLOAD FAILED; " \
638 "fi;"
639
640 #define CONFIG_PROG_OS2 \
641 "$download_cmd $osaddr $osfile; " \
642 "if test $? -eq 0; then " \
643 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
644 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
645 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
646 "if test $? -ne 0; then " \
647 "echo OS PROGRAM FAILED; " \
648 "else; " \
649 "echo OS PROGRAM SUCCEEDED; " \
650 "fi; " \
651 "else; " \
652 "echo OS DOWNLOAD FAILED; " \
653 "fi;"
654
655 #define CONFIG_PROG_FDT1 \
656 "$download_cmd $fdtaddr $fdtfile; " \
657 "if test $? -eq 0; then " \
658 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
659 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
660 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
661 "if test $? -ne 0; then " \
662 "echo FDT PROGRAM FAILED; " \
663 "else; " \
664 "echo FDT PROGRAM SUCCEEDED; " \
665 "fi; " \
666 "else; " \
667 "echo FDT DOWNLOAD FAILED; " \
668 "fi;"
669
670 #define CONFIG_PROG_FDT2 \
671 "$download_cmd $fdtaddr $fdtfile; " \
672 "if test $? -eq 0; then " \
673 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
674 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
675 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
676 "if test $? -ne 0; then " \
677 "echo FDT PROGRAM FAILED; " \
678 "else; " \
679 "echo FDT PROGRAM SUCCEEDED; " \
680 "fi; " \
681 "else; " \
682 "echo FDT DOWNLOAD FAILED; " \
683 "fi;"
684
685 #define CONFIG_EXTRA_ENV_SETTINGS \
686 "autoload=yes\0" \
687 "download_cmd=tftp\0" \
688 "console_args=console=ttyS0,115200\0" \
689 "root_args=root=/dev/nfs rw\0" \
690 "misc_args=ip=on\0" \
691 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
692 "bootfile=/home/user/file\0" \
693 "osfile=/home/user/board.uImage\0" \
694 "fdtfile=/home/user/board.dtb\0" \
695 "ubootfile=/home/user/u-boot.bin\0" \
696 "fdtaddr=0x1e00000\0" \
697 "osaddr=0x1000000\0" \
698 "loadaddr=0x1000000\0" \
699 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
700 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
701 "prog_os1="CONFIG_PROG_OS1"\0" \
702 "prog_os2="CONFIG_PROG_OS2"\0" \
703 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
704 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
705 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
706 "bootcmd_flash1=run set_bootargs; " \
707 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
708 "bootcmd_flash2=run set_bootargs; " \
709 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
710 "bootcmd=run bootcmd_flash1\0"
711 #endif /* __CONFIG_H */
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