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Merge branch 'master' of git://www.denx.de/git/u-boot-imx
[people/ms/u-boot.git] / include / configs / xpedite517x.h
1 /*
2 * Copyright 2009 Extreme Engineering Solutions, Inc.
3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 /*
9 * xpedite517x board configuration file
10 */
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 /*
15 * High Level Configuration Options
16 */
17 #define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */
18 #define CONFIG_SYS_BOARD_NAME "XPedite5170"
19 #define CONFIG_SYS_FORM_3U_VPX 1
20 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
21 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
22 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */
23 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
24 #define CONFIG_ALTIVEC 1
25
26 #define CONFIG_SYS_TEXT_BASE 0xfff00000
27
28 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
29 #define CONFIG_PCIE1 1 /* PCIE controller 1 */
30 #define CONFIG_PCIE2 1 /* PCIE controller 2 */
31 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
32 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
33 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
34 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
35
36 /*
37 * DDR config
38 */
39 #define CONFIG_SYS_FSL_DDR2
40 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
41 #define CONFIG_DDR_SPD
42 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
43 #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
44 #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
45 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
46 #define CONFIG_NUM_DDR_CONTROLLERS 2
47 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
48 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
49 #define CONFIG_DDR_ECC
50 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
51 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
52 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
53 #define CONFIG_VERY_BIG_RAM
54 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
55
56 /*
57 * virtual address to be used for temporary mappings. There
58 * should be 128k free at this VA.
59 */
60 #define CONFIG_SYS_SCRATCH_VA 0xe0000000
61
62 #ifndef __ASSEMBLY__
63 extern unsigned long get_board_sys_clk(unsigned long dummy);
64 #endif
65
66 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */
67
68 /*
69 * L2CR setup
70 */
71 #define CONFIG_SYS_L2
72 #define L2_INIT 0
73 #define L2_ENABLE (L2CR_L2E)
74
75 /*
76 * Base addresses -- Note these are effective addresses where the
77 * actual resources get mapped (not physical addresses)
78 */
79 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
80 #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
81 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
82 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
83 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
84 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
85
86 /*
87 * Diagnostics
88 */
89 #define CONFIG_SYS_ALT_MEMTEST
90 #define CONFIG_SYS_MEMTEST_START 0x10000000
91 #define CONFIG_SYS_MEMTEST_END 0x20000000
92 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\
93 CONFIG_SYS_POST_I2C)
94 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_DS1621_ADDR, \
95 CONFIG_SYS_I2C_DS4510_ADDR, \
96 CONFIG_SYS_I2C_EEPROM_ADDR, \
97 CONFIG_SYS_I2C_LM90_ADDR, \
98 CONFIG_SYS_I2C_PCA9553_ADDR, \
99 CONFIG_SYS_I2C_PCA953X_ADDR0, \
100 CONFIG_SYS_I2C_PCA953X_ADDR1, \
101 CONFIG_SYS_I2C_PCA953X_ADDR2, \
102 CONFIG_SYS_I2C_PCA953X_ADDR3, \
103 CONFIG_SYS_I2C_PEX8518_ADDR, \
104 CONFIG_SYS_I2C_RTC_ADDR}
105 /* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
106 #define I2C_ADDR_IGNORE_LIST {0x50}
107
108 /*
109 * Memory map
110 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
111 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
112 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
113 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
114 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
115 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
116 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
117 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
118 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
119 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
120 */
121
122 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
123
124 /*
125 * NAND flash configuration
126 */
127 #define CONFIG_SYS_NAND_BASE 0xef800000
128 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
129 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
130 #define CONFIG_SYS_MAX_NAND_DEVICE 2
131 #define CONFIG_NAND_ACTL
132 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */
133 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */
134 #define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */
135 #define CONFIG_SYS_NAND_ACTL_DELAY 25
136 #define CONFIG_JFFS2_NAND
137
138 /*
139 * NOR flash configuration
140 */
141 #define CONFIG_SYS_FLASH_BASE 0xf8000000
142 #define CONFIG_SYS_FLASH_BASE2 0xf0000000
143 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
144 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
145 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
146 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
147 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
148 #define CONFIG_FLASH_CFI_DRIVER
149 #define CONFIG_SYS_FLASH_CFI
150 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
151 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \
152 {0xf7f00000, 0xc0000} }
153 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
154 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
155
156 /*
157 * Chip select configuration
158 */
159 /* NOR Flash 0 on CS0 */
160 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
161 BR_PS_16 |\
162 BR_V)
163 #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\
164 OR_GPCM_CSNT |\
165 OR_GPCM_XACS |\
166 OR_GPCM_ACS_DIV2 |\
167 OR_GPCM_SCY_8 |\
168 OR_GPCM_TRLX |\
169 OR_GPCM_EHTR |\
170 OR_GPCM_EAD)
171
172 /* NOR Flash 1 on CS1 */
173 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\
174 BR_PS_16 |\
175 BR_V)
176 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
177
178 /* NAND flash on CS2 */
179 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\
180 BR_PS_8 |\
181 BR_V)
182 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\
183 OR_GPCM_BCTLD |\
184 OR_GPCM_CSNT |\
185 OR_GPCM_ACS_DIV4 |\
186 OR_GPCM_SCY_4 |\
187 OR_GPCM_TRLX |\
188 OR_GPCM_EHTR)
189
190 /* Optional NAND flash on CS3 */
191 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\
192 BR_PS_8 |\
193 BR_V)
194 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
195
196 /*
197 * Use L1 as initial stack
198 */
199 #define CONFIG_SYS_INIT_RAM_LOCK 1
200 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
201 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
202
203 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
204 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
205
206 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
207 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
208
209 /*
210 * Serial Port
211 */
212 #define CONFIG_CONS_INDEX 1
213 #define CONFIG_SYS_NS16550_SERIAL
214 #define CONFIG_SYS_NS16550_REG_SIZE 1
215 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
216 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
217 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
218 #define CONFIG_SYS_BAUDRATE_TABLE \
219 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
220 #define CONFIG_BAUDRATE 115200
221 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
222 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
223
224 /*
225 * I2C
226 */
227 #define CONFIG_SYS_I2C
228 #define CONFIG_SYS_I2C_FSL
229 #define CONFIG_SYS_FSL_I2C_SPEED 100000
230 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
231 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
232 #define CONFIG_SYS_FSL_I2C2_SPEED 100000
233 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
234 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
235
236 /* PEX8518 slave I2C interface */
237 #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
238
239 /* I2C DS1631 temperature sensor */
240 #define CONFIG_SYS_I2C_DS1621_ADDR 0x48
241 #define CONFIG_DTT_DS1621
242 #define CONFIG_DTT_SENSORS { 0 }
243 #define CONFIG_SYS_I2C_LM90_ADDR 0x4c
244
245 /* I2C EEPROM - AT24C128B */
246 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
247 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
248 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
249 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
250
251 /* I2C RTC */
252 #define CONFIG_RTC_M41T11 1
253 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
254 #define CONFIG_SYS_M41T11_BASE_YEAR 2000
255
256 /* GPIO/EEPROM/SRAM */
257 #define CONFIG_DS4510
258 #define CONFIG_SYS_I2C_DS4510_ADDR 0x51
259
260 /* GPIO */
261 #define CONFIG_PCA953X
262 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
263 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
264 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
265 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
266 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
267 #define CONFIG_SYS_I2C_PCA9553_ADDR 0x62
268
269 /*
270 * PU = pulled high, PD = pulled low
271 * I = input, O = output, IO = input/output
272 */
273 /* PCA9557 @ 0x18*/
274 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
275 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
276 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
277 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
278 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
279 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
280
281 /* PCA9557 @ 0x1c*/
282 #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
283 #define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */
284 #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
285 #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
286 #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
287 #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
288 #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
289 #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
290
291 /* PCA9557 @ 0x1e*/
292 #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
293 #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
294 #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
295 #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
296 #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
297 #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */
298 #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */
299
300 /* PCA9557 @ 0x1f */
301 #define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */
302 #define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */
303 #define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */
304 #define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */
305
306 /*
307 * General PCI
308 * Memory space is mapped 1-1, but I/O space must start from 0.
309 */
310 /* PCIE1 - PEX8518 */
311 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
312 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
313 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
314 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
315 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
316 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
317
318 /* PCIE2 - VPX P1 */
319 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
320 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
321 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
322 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
323 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
324 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
325
326 /*
327 * Networking options
328 */
329 #define CONFIG_TSEC_ENET /* tsec ethernet support */
330 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
331 #define CONFIG_MII 1 /* MII PHY management */
332 #define CONFIG_ETHPRIME "eTSEC1"
333
334 #define CONFIG_TSEC1 1
335 #define CONFIG_TSEC1_NAME "eTSEC1"
336 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
337 #define TSEC1_PHY_ADDR 1
338 #define TSEC1_PHYIDX 0
339 #define CONFIG_HAS_ETH0
340
341 #define CONFIG_TSEC2 1
342 #define CONFIG_TSEC2_NAME "eTSEC2"
343 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
344 #define TSEC2_PHY_ADDR 2
345 #define TSEC2_PHYIDX 0
346 #define CONFIG_HAS_ETH1
347
348 /*
349 * BAT mappings
350 */
351 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
352 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
353 BATL_PP_RW |\
354 BATL_CACHEINHIBIT |\
355 BATL_GUARDEDSTORAGE)
356 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\
357 BATU_BL_1M |\
358 BATU_VS |\
359 BATU_VP)
360 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
361 BATL_PP_RW |\
362 BATL_CACHEINHIBIT)
363 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
364 #endif
365
366 /*
367 * BAT0 2G Cacheable, non-guarded
368 * 0x0000_0000 2G DDR
369 */
370 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
371 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
372 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
373 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
374
375 /*
376 * BAT1 1G Cache-inhibited, guarded
377 * 0x8000_0000 1G PCI-Express 1 Memory
378 */
379 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
380 BATL_PP_RW |\
381 BATL_CACHEINHIBIT |\
382 BATL_GUARDEDSTORAGE)
383 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\
384 BATU_BL_1G |\
385 BATU_VS |\
386 BATU_VP)
387 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
388 BATL_PP_RW |\
389 BATL_CACHEINHIBIT)
390 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
391
392 /*
393 * BAT2 512M Cache-inhibited, guarded
394 * 0xc000_0000 512M PCI-Express 2 Memory
395 */
396 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
397 BATL_PP_RW |\
398 BATL_CACHEINHIBIT |\
399 BATL_GUARDEDSTORAGE)
400 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\
401 BATU_BL_512M |\
402 BATU_VS |\
403 BATU_VP)
404 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
405 BATL_PP_RW |\
406 BATL_CACHEINHIBIT)
407 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
408
409 /*
410 * BAT3 1M Cache-inhibited, guarded
411 * 0xe000_0000 1M CCSR
412 */
413 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\
414 BATL_PP_RW |\
415 BATL_CACHEINHIBIT |\
416 BATL_GUARDEDSTORAGE)
417 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\
418 BATU_BL_1M |\
419 BATU_VS |\
420 BATU_VP)
421 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\
422 BATL_PP_RW |\
423 BATL_CACHEINHIBIT)
424 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
425
426 /*
427 * BAT4 32M Cache-inhibited, guarded
428 * 0xe200_0000 16M PCI-Express 1 I/O
429 * 0xe300_0000 16M PCI-Express 2 I/0
430 */
431 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
432 BATL_PP_RW |\
433 BATL_CACHEINHIBIT |\
434 BATL_GUARDEDSTORAGE)
435 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\
436 BATU_BL_32M |\
437 BATU_VS |\
438 BATU_VP)
439 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
440 BATL_PP_RW |\
441 BATL_CACHEINHIBIT)
442 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
443
444 /*
445 * BAT5 128K Cacheable, non-guarded
446 * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory)
447 */
448 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\
449 BATL_PP_RW |\
450 BATL_MEMCOHERENCE)
451 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\
452 BATU_BL_128K |\
453 BATU_VS |\
454 BATU_VP)
455 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
456 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
457
458 /*
459 * BAT6 256M Cache-inhibited, guarded
460 * 0xf000_0000 256M FLASH
461 */
462 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\
463 BATL_PP_RW |\
464 BATL_CACHEINHIBIT |\
465 BATL_GUARDEDSTORAGE)
466 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\
467 BATU_BL_256M |\
468 BATU_VS |\
469 BATU_VP)
470 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\
471 BATL_PP_RW |\
472 BATL_MEMCOHERENCE)
473 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
474
475 /* Map the last 1M of flash where we're running from reset */
476 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
477 BATL_PP_RW |\
478 BATL_CACHEINHIBIT |\
479 BATL_GUARDEDSTORAGE)
480 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE |\
481 BATU_BL_1M |\
482 BATU_VS |\
483 BATU_VP)
484 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
485 BATL_PP_RW |\
486 BATL_MEMCOHERENCE)
487 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
488
489 /*
490 * BAT7 64M Cache-inhibited, guarded
491 * 0xe800_0000 64K NAND FLASH
492 * 0xe804_0000 128K DUART Registers
493 */
494 #define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\
495 BATL_PP_RW |\
496 BATL_CACHEINHIBIT |\
497 BATL_GUARDEDSTORAGE)
498 #define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\
499 BATU_BL_512K |\
500 BATU_VS |\
501 BATU_VP)
502 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\
503 BATL_PP_RW |\
504 BATL_CACHEINHIBIT)
505 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
506
507 /*
508 * Command configuration.
509 */
510 #define CONFIG_CMD_DATE
511 #define CONFIG_CMD_DS4510
512 #define CONFIG_CMD_DS4510_INFO
513 #define CONFIG_CMD_DTT
514 #define CONFIG_CMD_EEPROM
515 #define CONFIG_CMD_IRQ
516 #define CONFIG_CMD_JFFS2
517 #define CONFIG_CMD_NAND
518 #define CONFIG_CMD_PCA953X
519 #define CONFIG_CMD_PCA953X_INFO
520 #define CONFIG_CMD_PCI
521 #define CONFIG_CMD_PCI_ENUM
522 #define CONFIG_CMD_REGINFO
523
524 /*
525 * Miscellaneous configurable options
526 */
527 #define CONFIG_SYS_LONGHELP /* undef to save memory */
528 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
529 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
530 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
531 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
532 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
533 #define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */
534 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
535 #define CONFIG_PANIC_HANG /* do not reset board on panic */
536 #define CONFIG_PREBOOT /* enable preboot variable */
537 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
538
539 /*
540 * For booting Linux, the board info and command line data
541 * have to be in the first 16 MB of memory, since this is
542 * the maximum mapped by the Linux kernel during initialization.
543 */
544 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
545 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
546
547 /*
548 * Environment Configuration
549 */
550 #define CONFIG_ENV_IS_IN_FLASH 1
551 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
552 #define CONFIG_ENV_SIZE 0x8000
553 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
554
555 /*
556 * Flash memory map:
557 * fffc0000 - ffffffff Pri FDT (256KB)
558 * fff80000 - fffbffff Pri U-Boot Environment (256 KB)
559 * fff00000 - fff7ffff Pri U-Boot (512 KB)
560 * fef00000 - ffefffff Pri OS image (16MB)
561 * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
562 *
563 * f7fc0000 - f7ffffff Sec FDT (256KB)
564 * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB)
565 * f7f00000 - f7f7ffff Sec U-Boot (512 KB)
566 * f6f00000 - f7efffff Sec OS image (16MB)
567 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
568 */
569 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff00000)
570 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f00000)
571 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfffc0000)
572 #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7fc0000)
573 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
574 #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
575
576 #define CONFIG_PROG_UBOOT1 \
577 "$download_cmd $loadaddr $ubootfile; " \
578 "if test $? -eq 0; then " \
579 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
580 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
581 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
582 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
583 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
584 "if test $? -ne 0; then " \
585 "echo PROGRAM FAILED; " \
586 "else; " \
587 "echo PROGRAM SUCCEEDED; " \
588 "fi; " \
589 "else; " \
590 "echo DOWNLOAD FAILED; " \
591 "fi;"
592
593 #define CONFIG_PROG_UBOOT2 \
594 "$download_cmd $loadaddr $ubootfile; " \
595 "if test $? -eq 0; then " \
596 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
597 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
598 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
599 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
600 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
601 "if test $? -ne 0; then " \
602 "echo PROGRAM FAILED; " \
603 "else; " \
604 "echo PROGRAM SUCCEEDED; " \
605 "fi; " \
606 "else; " \
607 "echo DOWNLOAD FAILED; " \
608 "fi;"
609
610 #define CONFIG_BOOT_OS_NET \
611 "$download_cmd $osaddr $osfile; " \
612 "if test $? -eq 0; then " \
613 "if test -n $fdtaddr; then " \
614 "$download_cmd $fdtaddr $fdtfile; " \
615 "if test $? -eq 0; then " \
616 "bootm $osaddr - $fdtaddr; " \
617 "else; " \
618 "echo FDT DOWNLOAD FAILED; " \
619 "fi; " \
620 "else; " \
621 "bootm $osaddr; " \
622 "fi; " \
623 "else; " \
624 "echo OS DOWNLOAD FAILED; " \
625 "fi;"
626
627 #define CONFIG_PROG_OS1 \
628 "$download_cmd $osaddr $osfile; " \
629 "if test $? -eq 0; then " \
630 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
631 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
632 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
633 "if test $? -ne 0; then " \
634 "echo OS PROGRAM FAILED; " \
635 "else; " \
636 "echo OS PROGRAM SUCCEEDED; " \
637 "fi; " \
638 "else; " \
639 "echo OS DOWNLOAD FAILED; " \
640 "fi;"
641
642 #define CONFIG_PROG_OS2 \
643 "$download_cmd $osaddr $osfile; " \
644 "if test $? -eq 0; then " \
645 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
646 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
647 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
648 "if test $? -ne 0; then " \
649 "echo OS PROGRAM FAILED; " \
650 "else; " \
651 "echo OS PROGRAM SUCCEEDED; " \
652 "fi; " \
653 "else; " \
654 "echo OS DOWNLOAD FAILED; " \
655 "fi;"
656
657 #define CONFIG_PROG_FDT1 \
658 "$download_cmd $fdtaddr $fdtfile; " \
659 "if test $? -eq 0; then " \
660 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
661 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
662 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
663 "if test $? -ne 0; then " \
664 "echo FDT PROGRAM FAILED; " \
665 "else; " \
666 "echo FDT PROGRAM SUCCEEDED; " \
667 "fi; " \
668 "else; " \
669 "echo FDT DOWNLOAD FAILED; " \
670 "fi;"
671
672 #define CONFIG_PROG_FDT2 \
673 "$download_cmd $fdtaddr $fdtfile; " \
674 "if test $? -eq 0; then " \
675 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
676 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
677 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
678 "if test $? -ne 0; then " \
679 "echo FDT PROGRAM FAILED; " \
680 "else; " \
681 "echo FDT PROGRAM SUCCEEDED; " \
682 "fi; " \
683 "else; " \
684 "echo FDT DOWNLOAD FAILED; " \
685 "fi;"
686
687 #define CONFIG_EXTRA_ENV_SETTINGS \
688 "autoload=yes\0" \
689 "download_cmd=tftp\0" \
690 "console_args=console=ttyS0,115200\0" \
691 "root_args=root=/dev/nfs rw\0" \
692 "misc_args=ip=on\0" \
693 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
694 "bootfile=/home/user/file\0" \
695 "osfile=/home/user/board.uImage\0" \
696 "fdtfile=/home/user/board.dtb\0" \
697 "ubootfile=/home/user/u-boot.bin\0" \
698 "fdtaddr=0x1e00000\0" \
699 "osaddr=0x1000000\0" \
700 "loadaddr=0x1000000\0" \
701 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
702 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
703 "prog_os1="CONFIG_PROG_OS1"\0" \
704 "prog_os2="CONFIG_PROG_OS2"\0" \
705 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
706 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
707 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
708 "bootcmd_flash1=run set_bootargs; " \
709 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
710 "bootcmd_flash2=run set_bootargs; " \
711 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
712 "bootcmd=run bootcmd_flash1\0"
713 #endif /* __CONFIG_H */
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