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Drop digital thermometer and thermostat (DTT) drivers
[people/ms/u-boot.git] / include / configs / xpedite517x.h
1 /*
2 * Copyright 2009 Extreme Engineering Solutions, Inc.
3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 /*
9 * xpedite517x board configuration file
10 */
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 /*
15 * High Level Configuration Options
16 */
17 #define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */
18 #define CONFIG_SYS_BOARD_NAME "XPedite5170"
19 #define CONFIG_SYS_FORM_3U_VPX 1
20 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
21 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
22 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */
23 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
24 #define CONFIG_ALTIVEC 1
25
26 #define CONFIG_SYS_TEXT_BASE 0xfff00000
27
28 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
29 #define CONFIG_PCIE1 1 /* PCIE controller 1 */
30 #define CONFIG_PCIE2 1 /* PCIE controller 2 */
31 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
32 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
33 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
34
35 /*
36 * DDR config
37 */
38 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
39 #define CONFIG_DDR_SPD
40 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
41 #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
42 #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
43 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
44 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
45 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
46 #define CONFIG_DDR_ECC
47 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
48 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
49 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
50 #define CONFIG_VERY_BIG_RAM
51 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
52
53 /*
54 * virtual address to be used for temporary mappings. There
55 * should be 128k free at this VA.
56 */
57 #define CONFIG_SYS_SCRATCH_VA 0xe0000000
58
59 #ifndef __ASSEMBLY__
60 extern unsigned long get_board_sys_clk(unsigned long dummy);
61 #endif
62
63 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */
64
65 /*
66 * L2CR setup
67 */
68 #define CONFIG_SYS_L2
69 #define L2_INIT 0
70 #define L2_ENABLE (L2CR_L2E)
71
72 /*
73 * Base addresses -- Note these are effective addresses where the
74 * actual resources get mapped (not physical addresses)
75 */
76 #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
77 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
78 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
79 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
80 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
81
82 /*
83 * Diagnostics
84 */
85 #define CONFIG_SYS_ALT_MEMTEST
86 #define CONFIG_SYS_MEMTEST_START 0x10000000
87 #define CONFIG_SYS_MEMTEST_END 0x20000000
88 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\
89 CONFIG_SYS_POST_I2C)
90 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_DS1621_ADDR, \
91 CONFIG_SYS_I2C_DS4510_ADDR, \
92 CONFIG_SYS_I2C_EEPROM_ADDR, \
93 CONFIG_SYS_I2C_LM90_ADDR, \
94 CONFIG_SYS_I2C_PCA9553_ADDR, \
95 CONFIG_SYS_I2C_PCA953X_ADDR0, \
96 CONFIG_SYS_I2C_PCA953X_ADDR1, \
97 CONFIG_SYS_I2C_PCA953X_ADDR2, \
98 CONFIG_SYS_I2C_PCA953X_ADDR3, \
99 CONFIG_SYS_I2C_PEX8518_ADDR, \
100 CONFIG_SYS_I2C_RTC_ADDR}
101 /* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
102 #define I2C_ADDR_IGNORE_LIST {0x50}
103
104 /*
105 * Memory map
106 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
107 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
108 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
109 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
110 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
111 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
112 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
113 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
114 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
115 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
116 */
117
118 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
119
120 /*
121 * NAND flash configuration
122 */
123 #define CONFIG_SYS_NAND_BASE 0xef800000
124 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
125 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
126 #define CONFIG_SYS_MAX_NAND_DEVICE 2
127 #define CONFIG_NAND_ACTL
128 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */
129 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */
130 #define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */
131 #define CONFIG_SYS_NAND_ACTL_DELAY 25
132 #define CONFIG_JFFS2_NAND
133
134 /*
135 * NOR flash configuration
136 */
137 #define CONFIG_SYS_FLASH_BASE 0xf8000000
138 #define CONFIG_SYS_FLASH_BASE2 0xf0000000
139 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
140 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
141 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
142 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
143 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
144 #define CONFIG_FLASH_CFI_DRIVER
145 #define CONFIG_SYS_FLASH_CFI
146 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
147 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \
148 {0xf7f00000, 0xc0000} }
149 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
150 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
151
152 /*
153 * Chip select configuration
154 */
155 /* NOR Flash 0 on CS0 */
156 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
157 BR_PS_16 |\
158 BR_V)
159 #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\
160 OR_GPCM_CSNT |\
161 OR_GPCM_XACS |\
162 OR_GPCM_ACS_DIV2 |\
163 OR_GPCM_SCY_8 |\
164 OR_GPCM_TRLX |\
165 OR_GPCM_EHTR |\
166 OR_GPCM_EAD)
167
168 /* NOR Flash 1 on CS1 */
169 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\
170 BR_PS_16 |\
171 BR_V)
172 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
173
174 /* NAND flash on CS2 */
175 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\
176 BR_PS_8 |\
177 BR_V)
178 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\
179 OR_GPCM_BCTLD |\
180 OR_GPCM_CSNT |\
181 OR_GPCM_ACS_DIV4 |\
182 OR_GPCM_SCY_4 |\
183 OR_GPCM_TRLX |\
184 OR_GPCM_EHTR)
185
186 /* Optional NAND flash on CS3 */
187 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\
188 BR_PS_8 |\
189 BR_V)
190 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
191
192 /*
193 * Use L1 as initial stack
194 */
195 #define CONFIG_SYS_INIT_RAM_LOCK 1
196 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
197 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
198
199 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
200 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
201
202 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
203 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
204
205 /*
206 * Serial Port
207 */
208 #define CONFIG_CONS_INDEX 1
209 #define CONFIG_SYS_NS16550_SERIAL
210 #define CONFIG_SYS_NS16550_REG_SIZE 1
211 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
212 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
213 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
214 #define CONFIG_SYS_BAUDRATE_TABLE \
215 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
216 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
217 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
218
219 /*
220 * I2C
221 */
222 #define CONFIG_SYS_I2C
223 #define CONFIG_SYS_I2C_FSL
224 #define CONFIG_SYS_FSL_I2C_SPEED 100000
225 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
226 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
227 #define CONFIG_SYS_FSL_I2C2_SPEED 100000
228 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
229 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
230
231 /* PEX8518 slave I2C interface */
232 #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
233
234 /* I2C DS1631 temperature sensor */
235 #define CONFIG_SYS_I2C_DS1621_ADDR 0x48
236 #define CONFIG_SYS_I2C_LM90_ADDR 0x4c
237
238 /* I2C EEPROM - AT24C128B */
239 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
240 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
241 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
242 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
243
244 /* I2C RTC */
245 #define CONFIG_RTC_M41T11 1
246 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
247 #define CONFIG_SYS_M41T11_BASE_YEAR 2000
248
249 /* GPIO/EEPROM/SRAM */
250 #define CONFIG_SYS_I2C_DS4510_ADDR 0x51
251
252 /* GPIO */
253 #define CONFIG_PCA953X
254 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
255 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
256 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
257 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
258 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
259 #define CONFIG_SYS_I2C_PCA9553_ADDR 0x62
260
261 /*
262 * PU = pulled high, PD = pulled low
263 * I = input, O = output, IO = input/output
264 */
265 /* PCA9557 @ 0x18*/
266 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
267 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
268 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
269 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
270 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
271 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
272
273 /* PCA9557 @ 0x1c*/
274 #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
275 #define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */
276 #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
277 #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
278 #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
279 #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
280 #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
281 #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
282
283 /* PCA9557 @ 0x1e*/
284 #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
285 #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
286 #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
287 #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
288 #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
289 #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */
290 #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */
291
292 /* PCA9557 @ 0x1f */
293 #define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */
294 #define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */
295 #define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */
296 #define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */
297
298 /*
299 * General PCI
300 * Memory space is mapped 1-1, but I/O space must start from 0.
301 */
302 /* PCIE1 - PEX8518 */
303 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
304 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
305 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
306 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
307 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
308 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
309
310 /* PCIE2 - VPX P1 */
311 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
312 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
313 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
314 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
315 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
316 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
317
318 /*
319 * Networking options
320 */
321 #define CONFIG_TSEC_ENET /* tsec ethernet support */
322 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
323 #define CONFIG_MII 1 /* MII PHY management */
324 #define CONFIG_ETHPRIME "eTSEC1"
325
326 #define CONFIG_TSEC1 1
327 #define CONFIG_TSEC1_NAME "eTSEC1"
328 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
329 #define TSEC1_PHY_ADDR 1
330 #define TSEC1_PHYIDX 0
331 #define CONFIG_HAS_ETH0
332
333 #define CONFIG_TSEC2 1
334 #define CONFIG_TSEC2_NAME "eTSEC2"
335 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
336 #define TSEC2_PHY_ADDR 2
337 #define TSEC2_PHYIDX 0
338 #define CONFIG_HAS_ETH1
339
340 /*
341 * BAT mappings
342 */
343 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
344 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
345 BATL_PP_RW |\
346 BATL_CACHEINHIBIT |\
347 BATL_GUARDEDSTORAGE)
348 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\
349 BATU_BL_1M |\
350 BATU_VS |\
351 BATU_VP)
352 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
353 BATL_PP_RW |\
354 BATL_CACHEINHIBIT)
355 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
356 #endif
357
358 /*
359 * BAT0 2G Cacheable, non-guarded
360 * 0x0000_0000 2G DDR
361 */
362 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
363 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
364 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
365 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
366
367 /*
368 * BAT1 1G Cache-inhibited, guarded
369 * 0x8000_0000 1G PCI-Express 1 Memory
370 */
371 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
372 BATL_PP_RW |\
373 BATL_CACHEINHIBIT |\
374 BATL_GUARDEDSTORAGE)
375 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\
376 BATU_BL_1G |\
377 BATU_VS |\
378 BATU_VP)
379 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
380 BATL_PP_RW |\
381 BATL_CACHEINHIBIT)
382 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
383
384 /*
385 * BAT2 512M Cache-inhibited, guarded
386 * 0xc000_0000 512M PCI-Express 2 Memory
387 */
388 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
389 BATL_PP_RW |\
390 BATL_CACHEINHIBIT |\
391 BATL_GUARDEDSTORAGE)
392 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\
393 BATU_BL_512M |\
394 BATU_VS |\
395 BATU_VP)
396 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
397 BATL_PP_RW |\
398 BATL_CACHEINHIBIT)
399 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
400
401 /*
402 * BAT3 1M Cache-inhibited, guarded
403 * 0xe000_0000 1M CCSR
404 */
405 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\
406 BATL_PP_RW |\
407 BATL_CACHEINHIBIT |\
408 BATL_GUARDEDSTORAGE)
409 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\
410 BATU_BL_1M |\
411 BATU_VS |\
412 BATU_VP)
413 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\
414 BATL_PP_RW |\
415 BATL_CACHEINHIBIT)
416 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
417
418 /*
419 * BAT4 32M Cache-inhibited, guarded
420 * 0xe200_0000 16M PCI-Express 1 I/O
421 * 0xe300_0000 16M PCI-Express 2 I/0
422 */
423 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
424 BATL_PP_RW |\
425 BATL_CACHEINHIBIT |\
426 BATL_GUARDEDSTORAGE)
427 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\
428 BATU_BL_32M |\
429 BATU_VS |\
430 BATU_VP)
431 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
432 BATL_PP_RW |\
433 BATL_CACHEINHIBIT)
434 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
435
436 /*
437 * BAT5 128K Cacheable, non-guarded
438 * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory)
439 */
440 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\
441 BATL_PP_RW |\
442 BATL_MEMCOHERENCE)
443 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\
444 BATU_BL_128K |\
445 BATU_VS |\
446 BATU_VP)
447 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
448 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
449
450 /*
451 * BAT6 256M Cache-inhibited, guarded
452 * 0xf000_0000 256M FLASH
453 */
454 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\
455 BATL_PP_RW |\
456 BATL_CACHEINHIBIT |\
457 BATL_GUARDEDSTORAGE)
458 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\
459 BATU_BL_256M |\
460 BATU_VS |\
461 BATU_VP)
462 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\
463 BATL_PP_RW |\
464 BATL_MEMCOHERENCE)
465 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
466
467 /* Map the last 1M of flash where we're running from reset */
468 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
469 BATL_PP_RW |\
470 BATL_CACHEINHIBIT |\
471 BATL_GUARDEDSTORAGE)
472 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE |\
473 BATU_BL_1M |\
474 BATU_VS |\
475 BATU_VP)
476 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
477 BATL_PP_RW |\
478 BATL_MEMCOHERENCE)
479 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
480
481 /*
482 * BAT7 64M Cache-inhibited, guarded
483 * 0xe800_0000 64K NAND FLASH
484 * 0xe804_0000 128K DUART Registers
485 */
486 #define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\
487 BATL_PP_RW |\
488 BATL_CACHEINHIBIT |\
489 BATL_GUARDEDSTORAGE)
490 #define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\
491 BATU_BL_512K |\
492 BATU_VS |\
493 BATU_VP)
494 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\
495 BATL_PP_RW |\
496 BATL_CACHEINHIBIT)
497 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
498
499 /*
500 * Command configuration.
501 */
502 #define CONFIG_CMD_EEPROM
503 #define CONFIG_CMD_IRQ
504 #define CONFIG_CMD_JFFS2
505 #define CONFIG_CMD_NAND
506 #define CONFIG_CMD_PCA953X
507 #define CONFIG_CMD_PCA953X_INFO
508 #define CONFIG_CMD_PCI
509 #define CONFIG_CMD_PCI_ENUM
510 #define CONFIG_CMD_REGINFO
511
512 /*
513 * Miscellaneous configurable options
514 */
515 #define CONFIG_SYS_LONGHELP /* undef to save memory */
516 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
517 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
518 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
519 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
520 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
521 #define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */
522 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
523 #define CONFIG_PANIC_HANG /* do not reset board on panic */
524 #define CONFIG_PREBOOT /* enable preboot variable */
525 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
526
527 /*
528 * For booting Linux, the board info and command line data
529 * have to be in the first 16 MB of memory, since this is
530 * the maximum mapped by the Linux kernel during initialization.
531 */
532 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
533 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
534
535 /*
536 * Environment Configuration
537 */
538 #define CONFIG_ENV_IS_IN_FLASH 1
539 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
540 #define CONFIG_ENV_SIZE 0x8000
541 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
542
543 /*
544 * Flash memory map:
545 * fffc0000 - ffffffff Pri FDT (256KB)
546 * fff80000 - fffbffff Pri U-Boot Environment (256 KB)
547 * fff00000 - fff7ffff Pri U-Boot (512 KB)
548 * fef00000 - ffefffff Pri OS image (16MB)
549 * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
550 *
551 * f7fc0000 - f7ffffff Sec FDT (256KB)
552 * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB)
553 * f7f00000 - f7f7ffff Sec U-Boot (512 KB)
554 * f6f00000 - f7efffff Sec OS image (16MB)
555 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
556 */
557 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff00000)
558 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f00000)
559 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfffc0000)
560 #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7fc0000)
561 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
562 #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
563
564 #define CONFIG_PROG_UBOOT1 \
565 "$download_cmd $loadaddr $ubootfile; " \
566 "if test $? -eq 0; then " \
567 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
568 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
569 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
570 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
571 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
572 "if test $? -ne 0; then " \
573 "echo PROGRAM FAILED; " \
574 "else; " \
575 "echo PROGRAM SUCCEEDED; " \
576 "fi; " \
577 "else; " \
578 "echo DOWNLOAD FAILED; " \
579 "fi;"
580
581 #define CONFIG_PROG_UBOOT2 \
582 "$download_cmd $loadaddr $ubootfile; " \
583 "if test $? -eq 0; then " \
584 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
585 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
586 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
587 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
588 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
589 "if test $? -ne 0; then " \
590 "echo PROGRAM FAILED; " \
591 "else; " \
592 "echo PROGRAM SUCCEEDED; " \
593 "fi; " \
594 "else; " \
595 "echo DOWNLOAD FAILED; " \
596 "fi;"
597
598 #define CONFIG_BOOT_OS_NET \
599 "$download_cmd $osaddr $osfile; " \
600 "if test $? -eq 0; then " \
601 "if test -n $fdtaddr; then " \
602 "$download_cmd $fdtaddr $fdtfile; " \
603 "if test $? -eq 0; then " \
604 "bootm $osaddr - $fdtaddr; " \
605 "else; " \
606 "echo FDT DOWNLOAD FAILED; " \
607 "fi; " \
608 "else; " \
609 "bootm $osaddr; " \
610 "fi; " \
611 "else; " \
612 "echo OS DOWNLOAD FAILED; " \
613 "fi;"
614
615 #define CONFIG_PROG_OS1 \
616 "$download_cmd $osaddr $osfile; " \
617 "if test $? -eq 0; then " \
618 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
619 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
620 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
621 "if test $? -ne 0; then " \
622 "echo OS PROGRAM FAILED; " \
623 "else; " \
624 "echo OS PROGRAM SUCCEEDED; " \
625 "fi; " \
626 "else; " \
627 "echo OS DOWNLOAD FAILED; " \
628 "fi;"
629
630 #define CONFIG_PROG_OS2 \
631 "$download_cmd $osaddr $osfile; " \
632 "if test $? -eq 0; then " \
633 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
634 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
635 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
636 "if test $? -ne 0; then " \
637 "echo OS PROGRAM FAILED; " \
638 "else; " \
639 "echo OS PROGRAM SUCCEEDED; " \
640 "fi; " \
641 "else; " \
642 "echo OS DOWNLOAD FAILED; " \
643 "fi;"
644
645 #define CONFIG_PROG_FDT1 \
646 "$download_cmd $fdtaddr $fdtfile; " \
647 "if test $? -eq 0; then " \
648 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
649 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
650 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
651 "if test $? -ne 0; then " \
652 "echo FDT PROGRAM FAILED; " \
653 "else; " \
654 "echo FDT PROGRAM SUCCEEDED; " \
655 "fi; " \
656 "else; " \
657 "echo FDT DOWNLOAD FAILED; " \
658 "fi;"
659
660 #define CONFIG_PROG_FDT2 \
661 "$download_cmd $fdtaddr $fdtfile; " \
662 "if test $? -eq 0; then " \
663 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
664 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
665 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
666 "if test $? -ne 0; then " \
667 "echo FDT PROGRAM FAILED; " \
668 "else; " \
669 "echo FDT PROGRAM SUCCEEDED; " \
670 "fi; " \
671 "else; " \
672 "echo FDT DOWNLOAD FAILED; " \
673 "fi;"
674
675 #define CONFIG_EXTRA_ENV_SETTINGS \
676 "autoload=yes\0" \
677 "download_cmd=tftp\0" \
678 "console_args=console=ttyS0,115200\0" \
679 "root_args=root=/dev/nfs rw\0" \
680 "misc_args=ip=on\0" \
681 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
682 "bootfile=/home/user/file\0" \
683 "osfile=/home/user/board.uImage\0" \
684 "fdtfile=/home/user/board.dtb\0" \
685 "ubootfile=/home/user/u-boot.bin\0" \
686 "fdtaddr=0x1e00000\0" \
687 "osaddr=0x1000000\0" \
688 "loadaddr=0x1000000\0" \
689 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
690 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
691 "prog_os1="CONFIG_PROG_OS1"\0" \
692 "prog_os2="CONFIG_PROG_OS2"\0" \
693 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
694 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
695 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
696 "bootcmd_flash1=run set_bootargs; " \
697 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
698 "bootcmd_flash2=run set_bootargs; " \
699 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
700 "bootcmd=run bootcmd_flash1\0"
701 #endif /* __CONFIG_H */
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