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[people/ms/u-boot.git] / include / configs / xpedite517x.h
1 /*
2 * Copyright 2009 Extreme Engineering Solutions, Inc.
3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 /*
9 * xpedite517x board configuration file
10 */
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 /*
15 * High Level Configuration Options
16 */
17 #define CONFIG_MPC8641 1 /* MPC8641 specific */
18 #define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */
19 #define CONFIG_SYS_BOARD_NAME "XPedite5170"
20 #define CONFIG_SYS_FORM_3U_VPX 1
21 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
22 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
23 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */
24 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
25 #define CONFIG_ALTIVEC 1
26 #define CONFIG_DISPLAY_BOARDINFO
27
28 #define CONFIG_SYS_TEXT_BASE 0xfff00000
29
30 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
31 #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
32 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
33 #define CONFIG_PCIE1 1 /* PCIE controler 1 */
34 #define CONFIG_PCIE2 1 /* PCIE controler 2 */
35 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
36 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
37 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
38 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
39
40 /*
41 * DDR config
42 */
43 #define CONFIG_SYS_FSL_DDR2
44 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
45 #define CONFIG_DDR_SPD
46 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
47 #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
48 #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
49 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
50 #define CONFIG_NUM_DDR_CONTROLLERS 2
51 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
52 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
53 #define CONFIG_DDR_ECC
54 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
55 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
56 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
57 #define CONFIG_VERY_BIG_RAM
58 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
59
60 /*
61 * virtual address to be used for temporary mappings. There
62 * should be 128k free at this VA.
63 */
64 #define CONFIG_SYS_SCRATCH_VA 0xe0000000
65
66 #ifndef __ASSEMBLY__
67 extern unsigned long get_board_sys_clk(unsigned long dummy);
68 #endif
69
70 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */
71
72 /*
73 * L2CR setup
74 */
75 #define CONFIG_SYS_L2
76 #define L2_INIT 0
77 #define L2_ENABLE (L2CR_L2E)
78
79 /*
80 * Base addresses -- Note these are effective addresses where the
81 * actual resources get mapped (not physical addresses)
82 */
83 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
84 #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
85 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
86 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
87 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
88 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
89
90 /*
91 * Diagnostics
92 */
93 #define CONFIG_SYS_ALT_MEMTEST
94 #define CONFIG_SYS_MEMTEST_START 0x10000000
95 #define CONFIG_SYS_MEMTEST_END 0x20000000
96 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\
97 CONFIG_SYS_POST_I2C)
98 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_DS1621_ADDR, \
99 CONFIG_SYS_I2C_DS4510_ADDR, \
100 CONFIG_SYS_I2C_EEPROM_ADDR, \
101 CONFIG_SYS_I2C_LM90_ADDR, \
102 CONFIG_SYS_I2C_PCA9553_ADDR, \
103 CONFIG_SYS_I2C_PCA953X_ADDR0, \
104 CONFIG_SYS_I2C_PCA953X_ADDR1, \
105 CONFIG_SYS_I2C_PCA953X_ADDR2, \
106 CONFIG_SYS_I2C_PCA953X_ADDR3, \
107 CONFIG_SYS_I2C_PEX8518_ADDR, \
108 CONFIG_SYS_I2C_RTC_ADDR}
109 /* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
110 #define I2C_ADDR_IGNORE_LIST {0x50}
111
112 /*
113 * Memory map
114 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
115 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
116 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
117 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
118 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
119 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
120 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
121 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
122 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
123 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
124 */
125
126 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
127
128 /*
129 * NAND flash configuration
130 */
131 #define CONFIG_SYS_NAND_BASE 0xef800000
132 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
133 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
134 #define CONFIG_SYS_MAX_NAND_DEVICE 2
135 #define CONFIG_NAND_ACTL
136 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */
137 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */
138 #define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */
139 #define CONFIG_SYS_NAND_ACTL_DELAY 25
140 #define CONFIG_JFFS2_NAND
141
142 /*
143 * NOR flash configuration
144 */
145 #define CONFIG_SYS_FLASH_BASE 0xf8000000
146 #define CONFIG_SYS_FLASH_BASE2 0xf0000000
147 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
148 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
149 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
150 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
151 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
152 #define CONFIG_FLASH_CFI_DRIVER
153 #define CONFIG_SYS_FLASH_CFI
154 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
155 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \
156 {0xf7f00000, 0xc0000} }
157 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
158 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
159
160 /*
161 * Chip select configuration
162 */
163 /* NOR Flash 0 on CS0 */
164 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
165 BR_PS_16 |\
166 BR_V)
167 #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\
168 OR_GPCM_CSNT |\
169 OR_GPCM_XACS |\
170 OR_GPCM_ACS_DIV2 |\
171 OR_GPCM_SCY_8 |\
172 OR_GPCM_TRLX |\
173 OR_GPCM_EHTR |\
174 OR_GPCM_EAD)
175
176 /* NOR Flash 1 on CS1 */
177 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\
178 BR_PS_16 |\
179 BR_V)
180 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
181
182 /* NAND flash on CS2 */
183 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\
184 BR_PS_8 |\
185 BR_V)
186 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\
187 OR_GPCM_BCTLD |\
188 OR_GPCM_CSNT |\
189 OR_GPCM_ACS_DIV4 |\
190 OR_GPCM_SCY_4 |\
191 OR_GPCM_TRLX |\
192 OR_GPCM_EHTR)
193
194 /* Optional NAND flash on CS3 */
195 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\
196 BR_PS_8 |\
197 BR_V)
198 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
199
200 /*
201 * Use L1 as initial stack
202 */
203 #define CONFIG_SYS_INIT_RAM_LOCK 1
204 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
205 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
206
207 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
208 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
209
210 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
211 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
212
213 /*
214 * Serial Port
215 */
216 #define CONFIG_CONS_INDEX 1
217 #define CONFIG_SYS_NS16550_SERIAL
218 #define CONFIG_SYS_NS16550_REG_SIZE 1
219 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
220 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
221 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
222 #define CONFIG_SYS_BAUDRATE_TABLE \
223 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
224 #define CONFIG_BAUDRATE 115200
225 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
226 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
227
228 /*
229 * Use the HUSH parser
230 */
231 #define CONFIG_SYS_HUSH_PARSER
232
233 /*
234 * I2C
235 */
236 #define CONFIG_SYS_I2C
237 #define CONFIG_SYS_I2C_FSL
238 #define CONFIG_SYS_FSL_I2C_SPEED 100000
239 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
240 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
241 #define CONFIG_SYS_FSL_I2C2_SPEED 100000
242 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
243 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
244
245 /* PEX8518 slave I2C interface */
246 #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
247
248 /* I2C DS1631 temperature sensor */
249 #define CONFIG_SYS_I2C_DS1621_ADDR 0x48
250 #define CONFIG_DTT_DS1621
251 #define CONFIG_DTT_SENSORS { 0 }
252 #define CONFIG_SYS_I2C_LM90_ADDR 0x4c
253
254 /* I2C EEPROM - AT24C128B */
255 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
256 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
257 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
258 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
259
260 /* I2C RTC */
261 #define CONFIG_RTC_M41T11 1
262 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
263 #define CONFIG_SYS_M41T11_BASE_YEAR 2000
264
265 /* GPIO/EEPROM/SRAM */
266 #define CONFIG_DS4510
267 #define CONFIG_SYS_I2C_DS4510_ADDR 0x51
268
269 /* GPIO */
270 #define CONFIG_PCA953X
271 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
272 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
273 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
274 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
275 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
276 #define CONFIG_SYS_I2C_PCA9553_ADDR 0x62
277
278 /*
279 * PU = pulled high, PD = pulled low
280 * I = input, O = output, IO = input/output
281 */
282 /* PCA9557 @ 0x18*/
283 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
284 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
285 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
286 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
287 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
288 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
289
290 /* PCA9557 @ 0x1c*/
291 #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
292 #define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */
293 #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
294 #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
295 #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
296 #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
297 #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
298 #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
299
300 /* PCA9557 @ 0x1e*/
301 #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
302 #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
303 #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
304 #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
305 #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
306 #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */
307 #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */
308
309 /* PCA9557 @ 0x1f */
310 #define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */
311 #define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */
312 #define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */
313 #define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */
314
315 /*
316 * General PCI
317 * Memory space is mapped 1-1, but I/O space must start from 0.
318 */
319 /* PCIE1 - PEX8518 */
320 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
321 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
322 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
323 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
324 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
325 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
326
327 /* PCIE2 - VPX P1 */
328 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
329 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
330 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
331 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
332 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
333 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
334
335 /*
336 * Networking options
337 */
338 #define CONFIG_TSEC_ENET /* tsec ethernet support */
339 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
340 #define CONFIG_MII 1 /* MII PHY management */
341 #define CONFIG_ETHPRIME "eTSEC1"
342
343 #define CONFIG_TSEC1 1
344 #define CONFIG_TSEC1_NAME "eTSEC1"
345 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
346 #define TSEC1_PHY_ADDR 1
347 #define TSEC1_PHYIDX 0
348 #define CONFIG_HAS_ETH0
349
350 #define CONFIG_TSEC2 1
351 #define CONFIG_TSEC2_NAME "eTSEC2"
352 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
353 #define TSEC2_PHY_ADDR 2
354 #define TSEC2_PHYIDX 0
355 #define CONFIG_HAS_ETH1
356
357 /*
358 * BAT mappings
359 */
360 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
361 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
362 BATL_PP_RW |\
363 BATL_CACHEINHIBIT |\
364 BATL_GUARDEDSTORAGE)
365 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\
366 BATU_BL_1M |\
367 BATU_VS |\
368 BATU_VP)
369 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
370 BATL_PP_RW |\
371 BATL_CACHEINHIBIT)
372 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
373 #endif
374
375 /*
376 * BAT0 2G Cacheable, non-guarded
377 * 0x0000_0000 2G DDR
378 */
379 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
380 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
381 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
382 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
383
384 /*
385 * BAT1 1G Cache-inhibited, guarded
386 * 0x8000_0000 1G PCI-Express 1 Memory
387 */
388 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
389 BATL_PP_RW |\
390 BATL_CACHEINHIBIT |\
391 BATL_GUARDEDSTORAGE)
392 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\
393 BATU_BL_1G |\
394 BATU_VS |\
395 BATU_VP)
396 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
397 BATL_PP_RW |\
398 BATL_CACHEINHIBIT)
399 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
400
401 /*
402 * BAT2 512M Cache-inhibited, guarded
403 * 0xc000_0000 512M PCI-Express 2 Memory
404 */
405 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
406 BATL_PP_RW |\
407 BATL_CACHEINHIBIT |\
408 BATL_GUARDEDSTORAGE)
409 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\
410 BATU_BL_512M |\
411 BATU_VS |\
412 BATU_VP)
413 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
414 BATL_PP_RW |\
415 BATL_CACHEINHIBIT)
416 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
417
418 /*
419 * BAT3 1M Cache-inhibited, guarded
420 * 0xe000_0000 1M CCSR
421 */
422 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\
423 BATL_PP_RW |\
424 BATL_CACHEINHIBIT |\
425 BATL_GUARDEDSTORAGE)
426 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\
427 BATU_BL_1M |\
428 BATU_VS |\
429 BATU_VP)
430 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\
431 BATL_PP_RW |\
432 BATL_CACHEINHIBIT)
433 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
434
435 /*
436 * BAT4 32M Cache-inhibited, guarded
437 * 0xe200_0000 16M PCI-Express 1 I/O
438 * 0xe300_0000 16M PCI-Express 2 I/0
439 */
440 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
441 BATL_PP_RW |\
442 BATL_CACHEINHIBIT |\
443 BATL_GUARDEDSTORAGE)
444 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\
445 BATU_BL_32M |\
446 BATU_VS |\
447 BATU_VP)
448 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
449 BATL_PP_RW |\
450 BATL_CACHEINHIBIT)
451 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
452
453 /*
454 * BAT5 128K Cacheable, non-guarded
455 * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory)
456 */
457 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\
458 BATL_PP_RW |\
459 BATL_MEMCOHERENCE)
460 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\
461 BATU_BL_128K |\
462 BATU_VS |\
463 BATU_VP)
464 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
465 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
466
467 /*
468 * BAT6 256M Cache-inhibited, guarded
469 * 0xf000_0000 256M FLASH
470 */
471 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\
472 BATL_PP_RW |\
473 BATL_CACHEINHIBIT |\
474 BATL_GUARDEDSTORAGE)
475 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\
476 BATU_BL_256M |\
477 BATU_VS |\
478 BATU_VP)
479 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\
480 BATL_PP_RW |\
481 BATL_MEMCOHERENCE)
482 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
483
484 /* Map the last 1M of flash where we're running from reset */
485 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
486 BATL_PP_RW |\
487 BATL_CACHEINHIBIT |\
488 BATL_GUARDEDSTORAGE)
489 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE |\
490 BATU_BL_1M |\
491 BATU_VS |\
492 BATU_VP)
493 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
494 BATL_PP_RW |\
495 BATL_MEMCOHERENCE)
496 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
497
498 /*
499 * BAT7 64M Cache-inhibited, guarded
500 * 0xe800_0000 64K NAND FLASH
501 * 0xe804_0000 128K DUART Registers
502 */
503 #define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\
504 BATL_PP_RW |\
505 BATL_CACHEINHIBIT |\
506 BATL_GUARDEDSTORAGE)
507 #define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\
508 BATU_BL_512K |\
509 BATU_VS |\
510 BATU_VP)
511 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\
512 BATL_PP_RW |\
513 BATL_CACHEINHIBIT)
514 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
515
516 /*
517 * Command configuration.
518 */
519 #define CONFIG_CMD_ASKENV
520 #define CONFIG_CMD_DATE
521 #define CONFIG_CMD_DHCP
522 #define CONFIG_CMD_DS4510
523 #define CONFIG_CMD_DS4510_INFO
524 #define CONFIG_CMD_DTT
525 #define CONFIG_CMD_EEPROM
526 #define CONFIG_CMD_I2C
527 #define CONFIG_CMD_IRQ
528 #define CONFIG_CMD_JFFS2
529 #define CONFIG_CMD_MII
530 #define CONFIG_CMD_NAND
531 #define CONFIG_CMD_PCA953X
532 #define CONFIG_CMD_PCA953X_INFO
533 #define CONFIG_CMD_PCI
534 #define CONFIG_CMD_PCI_ENUM
535 #define CONFIG_CMD_PING
536 #define CONFIG_CMD_REGINFO
537 #define CONFIG_CMD_SNTP
538
539 /*
540 * Miscellaneous configurable options
541 */
542 #define CONFIG_SYS_LONGHELP /* undef to save memory */
543 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
544 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
545 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
546 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
547 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
548 #define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */
549 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
550 #define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
551 #define CONFIG_PANIC_HANG /* do not reset board on panic */
552 #define CONFIG_PREBOOT /* enable preboot variable */
553 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
554
555 /*
556 * For booting Linux, the board info and command line data
557 * have to be in the first 16 MB of memory, since this is
558 * the maximum mapped by the Linux kernel during initialization.
559 */
560 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
561 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
562
563 /*
564 * Environment Configuration
565 */
566 #define CONFIG_ENV_IS_IN_FLASH 1
567 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
568 #define CONFIG_ENV_SIZE 0x8000
569 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
570
571 /*
572 * Flash memory map:
573 * fffc0000 - ffffffff Pri FDT (256KB)
574 * fff80000 - fffbffff Pri U-Boot Environment (256 KB)
575 * fff00000 - fff7ffff Pri U-Boot (512 KB)
576 * fef00000 - ffefffff Pri OS image (16MB)
577 * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
578 *
579 * f7fc0000 - f7ffffff Sec FDT (256KB)
580 * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB)
581 * f7f00000 - f7f7ffff Sec U-Boot (512 KB)
582 * f6f00000 - f7efffff Sec OS image (16MB)
583 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
584 */
585 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff00000)
586 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f00000)
587 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfffc0000)
588 #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7fc0000)
589 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
590 #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
591
592 #define CONFIG_PROG_UBOOT1 \
593 "$download_cmd $loadaddr $ubootfile; " \
594 "if test $? -eq 0; then " \
595 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
596 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
597 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
598 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
599 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
600 "if test $? -ne 0; then " \
601 "echo PROGRAM FAILED; " \
602 "else; " \
603 "echo PROGRAM SUCCEEDED; " \
604 "fi; " \
605 "else; " \
606 "echo DOWNLOAD FAILED; " \
607 "fi;"
608
609 #define CONFIG_PROG_UBOOT2 \
610 "$download_cmd $loadaddr $ubootfile; " \
611 "if test $? -eq 0; then " \
612 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
613 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
614 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
615 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
616 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
617 "if test $? -ne 0; then " \
618 "echo PROGRAM FAILED; " \
619 "else; " \
620 "echo PROGRAM SUCCEEDED; " \
621 "fi; " \
622 "else; " \
623 "echo DOWNLOAD FAILED; " \
624 "fi;"
625
626 #define CONFIG_BOOT_OS_NET \
627 "$download_cmd $osaddr $osfile; " \
628 "if test $? -eq 0; then " \
629 "if test -n $fdtaddr; then " \
630 "$download_cmd $fdtaddr $fdtfile; " \
631 "if test $? -eq 0; then " \
632 "bootm $osaddr - $fdtaddr; " \
633 "else; " \
634 "echo FDT DOWNLOAD FAILED; " \
635 "fi; " \
636 "else; " \
637 "bootm $osaddr; " \
638 "fi; " \
639 "else; " \
640 "echo OS DOWNLOAD FAILED; " \
641 "fi;"
642
643 #define CONFIG_PROG_OS1 \
644 "$download_cmd $osaddr $osfile; " \
645 "if test $? -eq 0; then " \
646 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
647 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
648 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
649 "if test $? -ne 0; then " \
650 "echo OS PROGRAM FAILED; " \
651 "else; " \
652 "echo OS PROGRAM SUCCEEDED; " \
653 "fi; " \
654 "else; " \
655 "echo OS DOWNLOAD FAILED; " \
656 "fi;"
657
658 #define CONFIG_PROG_OS2 \
659 "$download_cmd $osaddr $osfile; " \
660 "if test $? -eq 0; then " \
661 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
662 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
663 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
664 "if test $? -ne 0; then " \
665 "echo OS PROGRAM FAILED; " \
666 "else; " \
667 "echo OS PROGRAM SUCCEEDED; " \
668 "fi; " \
669 "else; " \
670 "echo OS DOWNLOAD FAILED; " \
671 "fi;"
672
673 #define CONFIG_PROG_FDT1 \
674 "$download_cmd $fdtaddr $fdtfile; " \
675 "if test $? -eq 0; then " \
676 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
677 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
678 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
679 "if test $? -ne 0; then " \
680 "echo FDT PROGRAM FAILED; " \
681 "else; " \
682 "echo FDT PROGRAM SUCCEEDED; " \
683 "fi; " \
684 "else; " \
685 "echo FDT DOWNLOAD FAILED; " \
686 "fi;"
687
688 #define CONFIG_PROG_FDT2 \
689 "$download_cmd $fdtaddr $fdtfile; " \
690 "if test $? -eq 0; then " \
691 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
692 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
693 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
694 "if test $? -ne 0; then " \
695 "echo FDT PROGRAM FAILED; " \
696 "else; " \
697 "echo FDT PROGRAM SUCCEEDED; " \
698 "fi; " \
699 "else; " \
700 "echo FDT DOWNLOAD FAILED; " \
701 "fi;"
702
703 #define CONFIG_EXTRA_ENV_SETTINGS \
704 "autoload=yes\0" \
705 "download_cmd=tftp\0" \
706 "console_args=console=ttyS0,115200\0" \
707 "root_args=root=/dev/nfs rw\0" \
708 "misc_args=ip=on\0" \
709 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
710 "bootfile=/home/user/file\0" \
711 "osfile=/home/user/board.uImage\0" \
712 "fdtfile=/home/user/board.dtb\0" \
713 "ubootfile=/home/user/u-boot.bin\0" \
714 "fdtaddr=c00000\0" \
715 "osaddr=0x1000000\0" \
716 "loadaddr=0x1000000\0" \
717 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
718 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
719 "prog_os1="CONFIG_PROG_OS1"\0" \
720 "prog_os2="CONFIG_PROG_OS2"\0" \
721 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
722 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
723 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
724 "bootcmd_flash1=run set_bootargs; " \
725 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
726 "bootcmd_flash2=run set_bootargs; " \
727 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
728 "bootcmd=run bootcmd_flash1\0"
729 #endif /* __CONFIG_H */
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