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fsl_ddr: Move DDR config options to driver Kconfig
[people/ms/u-boot.git] / include / configs / xpedite517x.h
1 /*
2 * Copyright 2009 Extreme Engineering Solutions, Inc.
3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 /*
9 * xpedite517x board configuration file
10 */
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 /*
15 * High Level Configuration Options
16 */
17 #define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */
18 #define CONFIG_SYS_BOARD_NAME "XPedite5170"
19 #define CONFIG_SYS_FORM_3U_VPX 1
20 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
21 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
22 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */
23 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
24 #define CONFIG_ALTIVEC 1
25
26 #define CONFIG_SYS_TEXT_BASE 0xfff00000
27
28 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
29 #define CONFIG_PCIE1 1 /* PCIE controller 1 */
30 #define CONFIG_PCIE2 1 /* PCIE controller 2 */
31 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
32 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
33 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
34
35 /*
36 * DDR config
37 */
38 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
39 #define CONFIG_DDR_SPD
40 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
41 #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
42 #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
43 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
44 #define CONFIG_NUM_DDR_CONTROLLERS 2
45 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
46 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
47 #define CONFIG_DDR_ECC
48 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
49 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
50 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
51 #define CONFIG_VERY_BIG_RAM
52 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
53
54 /*
55 * virtual address to be used for temporary mappings. There
56 * should be 128k free at this VA.
57 */
58 #define CONFIG_SYS_SCRATCH_VA 0xe0000000
59
60 #ifndef __ASSEMBLY__
61 extern unsigned long get_board_sys_clk(unsigned long dummy);
62 #endif
63
64 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */
65
66 /*
67 * L2CR setup
68 */
69 #define CONFIG_SYS_L2
70 #define L2_INIT 0
71 #define L2_ENABLE (L2CR_L2E)
72
73 /*
74 * Base addresses -- Note these are effective addresses where the
75 * actual resources get mapped (not physical addresses)
76 */
77 #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
78 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
79 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
80 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
81 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
82
83 /*
84 * Diagnostics
85 */
86 #define CONFIG_SYS_ALT_MEMTEST
87 #define CONFIG_SYS_MEMTEST_START 0x10000000
88 #define CONFIG_SYS_MEMTEST_END 0x20000000
89 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\
90 CONFIG_SYS_POST_I2C)
91 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_DS1621_ADDR, \
92 CONFIG_SYS_I2C_DS4510_ADDR, \
93 CONFIG_SYS_I2C_EEPROM_ADDR, \
94 CONFIG_SYS_I2C_LM90_ADDR, \
95 CONFIG_SYS_I2C_PCA9553_ADDR, \
96 CONFIG_SYS_I2C_PCA953X_ADDR0, \
97 CONFIG_SYS_I2C_PCA953X_ADDR1, \
98 CONFIG_SYS_I2C_PCA953X_ADDR2, \
99 CONFIG_SYS_I2C_PCA953X_ADDR3, \
100 CONFIG_SYS_I2C_PEX8518_ADDR, \
101 CONFIG_SYS_I2C_RTC_ADDR}
102 /* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
103 #define I2C_ADDR_IGNORE_LIST {0x50}
104
105 /*
106 * Memory map
107 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
108 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
109 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
110 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
111 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
112 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
113 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
114 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
115 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
116 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
117 */
118
119 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
120
121 /*
122 * NAND flash configuration
123 */
124 #define CONFIG_SYS_NAND_BASE 0xef800000
125 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
126 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
127 #define CONFIG_SYS_MAX_NAND_DEVICE 2
128 #define CONFIG_NAND_ACTL
129 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */
130 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */
131 #define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */
132 #define CONFIG_SYS_NAND_ACTL_DELAY 25
133 #define CONFIG_JFFS2_NAND
134
135 /*
136 * NOR flash configuration
137 */
138 #define CONFIG_SYS_FLASH_BASE 0xf8000000
139 #define CONFIG_SYS_FLASH_BASE2 0xf0000000
140 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
141 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
142 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
143 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
144 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
145 #define CONFIG_FLASH_CFI_DRIVER
146 #define CONFIG_SYS_FLASH_CFI
147 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
148 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \
149 {0xf7f00000, 0xc0000} }
150 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
151 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
152
153 /*
154 * Chip select configuration
155 */
156 /* NOR Flash 0 on CS0 */
157 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
158 BR_PS_16 |\
159 BR_V)
160 #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\
161 OR_GPCM_CSNT |\
162 OR_GPCM_XACS |\
163 OR_GPCM_ACS_DIV2 |\
164 OR_GPCM_SCY_8 |\
165 OR_GPCM_TRLX |\
166 OR_GPCM_EHTR |\
167 OR_GPCM_EAD)
168
169 /* NOR Flash 1 on CS1 */
170 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\
171 BR_PS_16 |\
172 BR_V)
173 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
174
175 /* NAND flash on CS2 */
176 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\
177 BR_PS_8 |\
178 BR_V)
179 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\
180 OR_GPCM_BCTLD |\
181 OR_GPCM_CSNT |\
182 OR_GPCM_ACS_DIV4 |\
183 OR_GPCM_SCY_4 |\
184 OR_GPCM_TRLX |\
185 OR_GPCM_EHTR)
186
187 /* Optional NAND flash on CS3 */
188 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\
189 BR_PS_8 |\
190 BR_V)
191 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
192
193 /*
194 * Use L1 as initial stack
195 */
196 #define CONFIG_SYS_INIT_RAM_LOCK 1
197 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
198 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
199
200 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
201 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
202
203 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
204 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
205
206 /*
207 * Serial Port
208 */
209 #define CONFIG_CONS_INDEX 1
210 #define CONFIG_SYS_NS16550_SERIAL
211 #define CONFIG_SYS_NS16550_REG_SIZE 1
212 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
213 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
214 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
215 #define CONFIG_SYS_BAUDRATE_TABLE \
216 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
217 #define CONFIG_BAUDRATE 115200
218 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
219 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
220
221 /*
222 * I2C
223 */
224 #define CONFIG_SYS_I2C
225 #define CONFIG_SYS_I2C_FSL
226 #define CONFIG_SYS_FSL_I2C_SPEED 100000
227 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
228 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
229 #define CONFIG_SYS_FSL_I2C2_SPEED 100000
230 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
231 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
232
233 /* PEX8518 slave I2C interface */
234 #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
235
236 /* I2C DS1631 temperature sensor */
237 #define CONFIG_SYS_I2C_DS1621_ADDR 0x48
238 #define CONFIG_DTT_DS1621
239 #define CONFIG_DTT_SENSORS { 0 }
240 #define CONFIG_SYS_I2C_LM90_ADDR 0x4c
241
242 /* I2C EEPROM - AT24C128B */
243 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
244 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
245 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
246 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
247
248 /* I2C RTC */
249 #define CONFIG_RTC_M41T11 1
250 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
251 #define CONFIG_SYS_M41T11_BASE_YEAR 2000
252
253 /* GPIO/EEPROM/SRAM */
254 #define CONFIG_DS4510
255 #define CONFIG_SYS_I2C_DS4510_ADDR 0x51
256
257 /* GPIO */
258 #define CONFIG_PCA953X
259 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
260 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
261 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
262 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
263 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
264 #define CONFIG_SYS_I2C_PCA9553_ADDR 0x62
265
266 /*
267 * PU = pulled high, PD = pulled low
268 * I = input, O = output, IO = input/output
269 */
270 /* PCA9557 @ 0x18*/
271 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
272 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
273 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
274 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
275 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
276 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
277
278 /* PCA9557 @ 0x1c*/
279 #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
280 #define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */
281 #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
282 #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
283 #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
284 #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
285 #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
286 #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
287
288 /* PCA9557 @ 0x1e*/
289 #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
290 #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
291 #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
292 #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
293 #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
294 #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */
295 #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */
296
297 /* PCA9557 @ 0x1f */
298 #define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */
299 #define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */
300 #define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */
301 #define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */
302
303 /*
304 * General PCI
305 * Memory space is mapped 1-1, but I/O space must start from 0.
306 */
307 /* PCIE1 - PEX8518 */
308 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
309 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
310 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
311 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
312 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
313 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
314
315 /* PCIE2 - VPX P1 */
316 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
317 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
318 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
319 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
320 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
321 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
322
323 /*
324 * Networking options
325 */
326 #define CONFIG_TSEC_ENET /* tsec ethernet support */
327 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
328 #define CONFIG_MII 1 /* MII PHY management */
329 #define CONFIG_ETHPRIME "eTSEC1"
330
331 #define CONFIG_TSEC1 1
332 #define CONFIG_TSEC1_NAME "eTSEC1"
333 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
334 #define TSEC1_PHY_ADDR 1
335 #define TSEC1_PHYIDX 0
336 #define CONFIG_HAS_ETH0
337
338 #define CONFIG_TSEC2 1
339 #define CONFIG_TSEC2_NAME "eTSEC2"
340 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
341 #define TSEC2_PHY_ADDR 2
342 #define TSEC2_PHYIDX 0
343 #define CONFIG_HAS_ETH1
344
345 /*
346 * BAT mappings
347 */
348 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
349 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
350 BATL_PP_RW |\
351 BATL_CACHEINHIBIT |\
352 BATL_GUARDEDSTORAGE)
353 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\
354 BATU_BL_1M |\
355 BATU_VS |\
356 BATU_VP)
357 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
358 BATL_PP_RW |\
359 BATL_CACHEINHIBIT)
360 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
361 #endif
362
363 /*
364 * BAT0 2G Cacheable, non-guarded
365 * 0x0000_0000 2G DDR
366 */
367 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
368 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
369 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
370 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
371
372 /*
373 * BAT1 1G Cache-inhibited, guarded
374 * 0x8000_0000 1G PCI-Express 1 Memory
375 */
376 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
377 BATL_PP_RW |\
378 BATL_CACHEINHIBIT |\
379 BATL_GUARDEDSTORAGE)
380 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\
381 BATU_BL_1G |\
382 BATU_VS |\
383 BATU_VP)
384 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
385 BATL_PP_RW |\
386 BATL_CACHEINHIBIT)
387 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
388
389 /*
390 * BAT2 512M Cache-inhibited, guarded
391 * 0xc000_0000 512M PCI-Express 2 Memory
392 */
393 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
394 BATL_PP_RW |\
395 BATL_CACHEINHIBIT |\
396 BATL_GUARDEDSTORAGE)
397 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\
398 BATU_BL_512M |\
399 BATU_VS |\
400 BATU_VP)
401 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
402 BATL_PP_RW |\
403 BATL_CACHEINHIBIT)
404 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
405
406 /*
407 * BAT3 1M Cache-inhibited, guarded
408 * 0xe000_0000 1M CCSR
409 */
410 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\
411 BATL_PP_RW |\
412 BATL_CACHEINHIBIT |\
413 BATL_GUARDEDSTORAGE)
414 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\
415 BATU_BL_1M |\
416 BATU_VS |\
417 BATU_VP)
418 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\
419 BATL_PP_RW |\
420 BATL_CACHEINHIBIT)
421 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
422
423 /*
424 * BAT4 32M Cache-inhibited, guarded
425 * 0xe200_0000 16M PCI-Express 1 I/O
426 * 0xe300_0000 16M PCI-Express 2 I/0
427 */
428 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
429 BATL_PP_RW |\
430 BATL_CACHEINHIBIT |\
431 BATL_GUARDEDSTORAGE)
432 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\
433 BATU_BL_32M |\
434 BATU_VS |\
435 BATU_VP)
436 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
437 BATL_PP_RW |\
438 BATL_CACHEINHIBIT)
439 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
440
441 /*
442 * BAT5 128K Cacheable, non-guarded
443 * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory)
444 */
445 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\
446 BATL_PP_RW |\
447 BATL_MEMCOHERENCE)
448 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\
449 BATU_BL_128K |\
450 BATU_VS |\
451 BATU_VP)
452 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
453 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
454
455 /*
456 * BAT6 256M Cache-inhibited, guarded
457 * 0xf000_0000 256M FLASH
458 */
459 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\
460 BATL_PP_RW |\
461 BATL_CACHEINHIBIT |\
462 BATL_GUARDEDSTORAGE)
463 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\
464 BATU_BL_256M |\
465 BATU_VS |\
466 BATU_VP)
467 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\
468 BATL_PP_RW |\
469 BATL_MEMCOHERENCE)
470 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
471
472 /* Map the last 1M of flash where we're running from reset */
473 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
474 BATL_PP_RW |\
475 BATL_CACHEINHIBIT |\
476 BATL_GUARDEDSTORAGE)
477 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE |\
478 BATU_BL_1M |\
479 BATU_VS |\
480 BATU_VP)
481 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
482 BATL_PP_RW |\
483 BATL_MEMCOHERENCE)
484 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
485
486 /*
487 * BAT7 64M Cache-inhibited, guarded
488 * 0xe800_0000 64K NAND FLASH
489 * 0xe804_0000 128K DUART Registers
490 */
491 #define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\
492 BATL_PP_RW |\
493 BATL_CACHEINHIBIT |\
494 BATL_GUARDEDSTORAGE)
495 #define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\
496 BATU_BL_512K |\
497 BATU_VS |\
498 BATU_VP)
499 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\
500 BATL_PP_RW |\
501 BATL_CACHEINHIBIT)
502 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
503
504 /*
505 * Command configuration.
506 */
507 #define CONFIG_CMD_DATE
508 #define CONFIG_CMD_DS4510
509 #define CONFIG_CMD_DS4510_INFO
510 #define CONFIG_CMD_DTT
511 #define CONFIG_CMD_EEPROM
512 #define CONFIG_CMD_IRQ
513 #define CONFIG_CMD_JFFS2
514 #define CONFIG_CMD_NAND
515 #define CONFIG_CMD_PCA953X
516 #define CONFIG_CMD_PCA953X_INFO
517 #define CONFIG_CMD_PCI
518 #define CONFIG_CMD_PCI_ENUM
519 #define CONFIG_CMD_REGINFO
520
521 /*
522 * Miscellaneous configurable options
523 */
524 #define CONFIG_SYS_LONGHELP /* undef to save memory */
525 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
526 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
527 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
528 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
529 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
530 #define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */
531 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
532 #define CONFIG_PANIC_HANG /* do not reset board on panic */
533 #define CONFIG_PREBOOT /* enable preboot variable */
534 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
535
536 /*
537 * For booting Linux, the board info and command line data
538 * have to be in the first 16 MB of memory, since this is
539 * the maximum mapped by the Linux kernel during initialization.
540 */
541 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
542 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
543
544 /*
545 * Environment Configuration
546 */
547 #define CONFIG_ENV_IS_IN_FLASH 1
548 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
549 #define CONFIG_ENV_SIZE 0x8000
550 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
551
552 /*
553 * Flash memory map:
554 * fffc0000 - ffffffff Pri FDT (256KB)
555 * fff80000 - fffbffff Pri U-Boot Environment (256 KB)
556 * fff00000 - fff7ffff Pri U-Boot (512 KB)
557 * fef00000 - ffefffff Pri OS image (16MB)
558 * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
559 *
560 * f7fc0000 - f7ffffff Sec FDT (256KB)
561 * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB)
562 * f7f00000 - f7f7ffff Sec U-Boot (512 KB)
563 * f6f00000 - f7efffff Sec OS image (16MB)
564 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
565 */
566 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff00000)
567 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f00000)
568 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfffc0000)
569 #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7fc0000)
570 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
571 #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
572
573 #define CONFIG_PROG_UBOOT1 \
574 "$download_cmd $loadaddr $ubootfile; " \
575 "if test $? -eq 0; then " \
576 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
577 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
578 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
579 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
580 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
581 "if test $? -ne 0; then " \
582 "echo PROGRAM FAILED; " \
583 "else; " \
584 "echo PROGRAM SUCCEEDED; " \
585 "fi; " \
586 "else; " \
587 "echo DOWNLOAD FAILED; " \
588 "fi;"
589
590 #define CONFIG_PROG_UBOOT2 \
591 "$download_cmd $loadaddr $ubootfile; " \
592 "if test $? -eq 0; then " \
593 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
594 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
595 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
596 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
597 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
598 "if test $? -ne 0; then " \
599 "echo PROGRAM FAILED; " \
600 "else; " \
601 "echo PROGRAM SUCCEEDED; " \
602 "fi; " \
603 "else; " \
604 "echo DOWNLOAD FAILED; " \
605 "fi;"
606
607 #define CONFIG_BOOT_OS_NET \
608 "$download_cmd $osaddr $osfile; " \
609 "if test $? -eq 0; then " \
610 "if test -n $fdtaddr; then " \
611 "$download_cmd $fdtaddr $fdtfile; " \
612 "if test $? -eq 0; then " \
613 "bootm $osaddr - $fdtaddr; " \
614 "else; " \
615 "echo FDT DOWNLOAD FAILED; " \
616 "fi; " \
617 "else; " \
618 "bootm $osaddr; " \
619 "fi; " \
620 "else; " \
621 "echo OS DOWNLOAD FAILED; " \
622 "fi;"
623
624 #define CONFIG_PROG_OS1 \
625 "$download_cmd $osaddr $osfile; " \
626 "if test $? -eq 0; then " \
627 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
628 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
629 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
630 "if test $? -ne 0; then " \
631 "echo OS PROGRAM FAILED; " \
632 "else; " \
633 "echo OS PROGRAM SUCCEEDED; " \
634 "fi; " \
635 "else; " \
636 "echo OS DOWNLOAD FAILED; " \
637 "fi;"
638
639 #define CONFIG_PROG_OS2 \
640 "$download_cmd $osaddr $osfile; " \
641 "if test $? -eq 0; then " \
642 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
643 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
644 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
645 "if test $? -ne 0; then " \
646 "echo OS PROGRAM FAILED; " \
647 "else; " \
648 "echo OS PROGRAM SUCCEEDED; " \
649 "fi; " \
650 "else; " \
651 "echo OS DOWNLOAD FAILED; " \
652 "fi;"
653
654 #define CONFIG_PROG_FDT1 \
655 "$download_cmd $fdtaddr $fdtfile; " \
656 "if test $? -eq 0; then " \
657 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
658 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
659 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
660 "if test $? -ne 0; then " \
661 "echo FDT PROGRAM FAILED; " \
662 "else; " \
663 "echo FDT PROGRAM SUCCEEDED; " \
664 "fi; " \
665 "else; " \
666 "echo FDT DOWNLOAD FAILED; " \
667 "fi;"
668
669 #define CONFIG_PROG_FDT2 \
670 "$download_cmd $fdtaddr $fdtfile; " \
671 "if test $? -eq 0; then " \
672 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
673 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
674 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
675 "if test $? -ne 0; then " \
676 "echo FDT PROGRAM FAILED; " \
677 "else; " \
678 "echo FDT PROGRAM SUCCEEDED; " \
679 "fi; " \
680 "else; " \
681 "echo FDT DOWNLOAD FAILED; " \
682 "fi;"
683
684 #define CONFIG_EXTRA_ENV_SETTINGS \
685 "autoload=yes\0" \
686 "download_cmd=tftp\0" \
687 "console_args=console=ttyS0,115200\0" \
688 "root_args=root=/dev/nfs rw\0" \
689 "misc_args=ip=on\0" \
690 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
691 "bootfile=/home/user/file\0" \
692 "osfile=/home/user/board.uImage\0" \
693 "fdtfile=/home/user/board.dtb\0" \
694 "ubootfile=/home/user/u-boot.bin\0" \
695 "fdtaddr=0x1e00000\0" \
696 "osaddr=0x1000000\0" \
697 "loadaddr=0x1000000\0" \
698 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
699 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
700 "prog_os1="CONFIG_PROG_OS1"\0" \
701 "prog_os2="CONFIG_PROG_OS2"\0" \
702 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
703 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
704 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
705 "bootcmd_flash1=run set_bootargs; " \
706 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
707 "bootcmd_flash2=run set_bootargs; " \
708 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
709 "bootcmd=run bootcmd_flash1\0"
710 #endif /* __CONFIG_H */
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