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1 /*
2 * Copyright 2008 Extreme Engineering Solutions, Inc.
3 * Copyright 2004-2008 Freescale Semiconductor, Inc.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 /*
9 * xpedite520x board configuration file
10 */
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 /*
15 * High Level Configuration Options
16 */
17 #define CONFIG_BOOKE 1 /* BOOKE */
18 #define CONFIG_E500 1 /* BOOKE e500 family */
19 #define CONFIG_MPC8548 1
20 #define CONFIG_XPEDITE5200 1
21 #define CONFIG_SYS_BOARD_NAME "XPedite5200"
22 #define CONFIG_SYS_FORM_PMC_XMC 1
23 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
24 #define CONFIG_SYS_GENERIC_BOARD
25 #define CONFIG_DISPLAY_BOARDINFO
26
27 #ifndef CONFIG_SYS_TEXT_BASE
28 #define CONFIG_SYS_TEXT_BASE 0xfff80000
29 #endif
30
31 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
32 #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
33 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
34 #define CONFIG_PCI1 1 /* PCI controller 1 */
35 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
36 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
37 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
38 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
39
40 /*
41 * DDR config
42 */
43 #define CONFIG_SYS_FSL_DDR2
44 #undef CONFIG_FSL_DDR_INTERACTIVE
45 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
46 #define CONFIG_DDR_SPD
47 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
48 #define SPD_EEPROM_ADDRESS 0x54
49 #define CONFIG_NUM_DDR_CONTROLLERS 1
50 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
51 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
52 #define CONFIG_DDR_ECC
53 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
54 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
55 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
56 #define CONFIG_VERY_BIG_RAM
57
58 #define CONFIG_SYS_CLK_FREQ 66666666
59
60 /*
61 * These can be toggled for performance analysis, otherwise use default.
62 */
63 #define CONFIG_L2_CACHE /* toggle L2 cache */
64 #define CONFIG_BTB /* toggle branch predition */
65 #define CONFIG_ENABLE_36BIT_PHYS 1
66
67 #define CONFIG_SYS_CCSRBAR 0xef000000
68 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
69
70 /*
71 * Diagnostics
72 */
73 #define CONFIG_SYS_ALT_MEMTEST
74 #define CONFIG_SYS_MEMTEST_START 0x10000000
75 #define CONFIG_SYS_MEMTEST_END 0x20000000
76 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
77 CONFIG_SYS_POST_I2C)
78 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_MAX1237_ADDR, \
79 CONFIG_SYS_I2C_EEPROM_ADDR, \
80 CONFIG_SYS_I2C_PCA953X_ADDR0, \
81 CONFIG_SYS_I2C_PCA953X_ADDR1, \
82 CONFIG_SYS_I2C_RTC_ADDR}
83
84 /*
85 * Memory map
86 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
87 * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable
88 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
89 * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable
90 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
91 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
92 * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable
93 * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable
94 */
95
96 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
97
98 /*
99 * NAND flash configuration
100 */
101 #define CONFIG_SYS_NAND_BASE 0xef800000
102 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
103 #define CONFIG_SYS_MAX_NAND_DEVICE 1
104 #define CONFIG_NAND_ACTL
105 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */
106 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */
107 #define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */
108 #define CONFIG_SYS_NAND_ACTL_DELAY 25
109
110 /*
111 * NOR flash configuration
112 */
113 #define CONFIG_SYS_FLASH_BASE 0xfc000000
114 #define CONFIG_SYS_FLASH_BASE2 0xf8000000
115 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
116 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
117 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
118 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
119 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
120 #define CONFIG_FLASH_CFI_DRIVER
121 #define CONFIG_SYS_FLASH_CFI
122 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
123 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
124 {0xfbf40000, 0xc0000} }
125 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
126
127 /*
128 * Chip select configuration
129 */
130 /* NOR Flash 0 on CS0 */
131 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
132 BR_PS_16 | \
133 BR_V)
134 #define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \
135 OR_GPCM_ACS_DIV4 | \
136 OR_GPCM_SCY_8)
137
138 /* NOR Flash 1 on CS1 */
139 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
140 BR_PS_16 | \
141 BR_V)
142 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
143
144 /* NAND flash on CS2 */
145 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
146 BR_PS_8 | \
147 BR_V)
148
149 /* NAND flash on CS2 */
150 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
151 OR_GPCM_BCTLD | \
152 OR_GPCM_CSNT | \
153 OR_GPCM_ACS_DIV4 | \
154 OR_GPCM_SCY_4 | \
155 OR_GPCM_TRLX | \
156 OR_GPCM_EHTR)
157
158 /* NAND flash on CS3 */
159 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
160 BR_PS_8 | \
161 BR_V)
162 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
163
164 /*
165 * Use L1 as initial stack
166 */
167 #define CONFIG_SYS_INIT_RAM_LOCK 1
168 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
169 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000
170
171 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
172 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
173
174 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
175 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
176
177 /*
178 * Serial Port
179 */
180 #define CONFIG_CONS_INDEX 1
181 #define CONFIG_SYS_NS16550
182 #define CONFIG_SYS_NS16550_SERIAL
183 #define CONFIG_SYS_NS16550_REG_SIZE 1
184 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
185 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
186 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
187 #define CONFIG_SYS_BAUDRATE_TABLE \
188 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
189 #define CONFIG_BAUDRATE 115200
190 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
191 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
192
193 /*
194 * Use the HUSH parser
195 */
196 #define CONFIG_SYS_HUSH_PARSER
197
198 /*
199 * Pass open firmware flat tree
200 */
201 #define CONFIG_OF_LIBFDT 1
202 #define CONFIG_OF_BOARD_SETUP 1
203 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
204
205 /*
206 * I2C
207 */
208 #define CONFIG_SYS_I2C
209 #define CONFIG_SYS_I2C_FSL
210 #define CONFIG_SYS_FSL_I2C_SPEED 400000
211 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
212 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
213 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
214 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
215 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
216
217 /* I2C EEPROM */
218 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
219 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
220 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
221 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
222
223 /* I2C RTC */
224 #define CONFIG_RTC_M41T11 1
225 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
226 #define CONFIG_SYS_M41T11_BASE_YEAR 2000
227
228 /* GPIO */
229 #define CONFIG_PCA953X
230 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
231 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19
232 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
233
234 /* PCA957 @ 0x18 */
235 #define CONFIG_SYS_PCA953X_BRD_CFG0 0x01
236 #define CONFIG_SYS_PCA953X_BRD_CFG1 0x02
237 #define CONFIG_SYS_PCA953X_BRD_CFG2 0x04
238 #define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08
239 #define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10
240 #define CONFIG_SYS_PCA953X_NVM_WP 0x20
241 #define CONFIG_SYS_PCA953X_MONARCH 0x40
242 #define CONFIG_SYS_PCA953X_EREADY 0x80
243
244 /* PCA957 @ 0x19 */
245 #define CONFIG_SYS_PCA953X_P14_IO0 0x01
246 #define CONFIG_SYS_PCA953X_P14_IO1 0x02
247 #define CONFIG_SYS_PCA953X_P14_IO2 0x04
248 #define CONFIG_SYS_PCA953X_P14_IO3 0x08
249 #define CONFIG_SYS_PCA953X_P14_IO4 0x10
250 #define CONFIG_SYS_PCA953X_P14_IO5 0x20
251 #define CONFIG_SYS_PCA953X_P14_IO6 0x40
252 #define CONFIG_SYS_PCA953X_P14_IO7 0x80
253
254 /* 12-bit ADC used to measure CPU diode */
255 #define CONFIG_SYS_I2C_MAX1237_ADDR 0x34
256
257 /*
258 * General PCI
259 * Memory space is mapped 1-1, but I/O space must start from 0.
260 */
261 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
262 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
263 #define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */
264 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
265 #define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000
266 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */
267
268 /*
269 * Networking options
270 */
271 #define CONFIG_TSEC_ENET /* tsec ethernet support */
272 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
273 #define CONFIG_MII 1 /* MII PHY management */
274 #define CONFIG_ETHPRIME "eTSEC1"
275
276 #define CONFIG_TSEC1 1
277 #define CONFIG_TSEC1_NAME "eTSEC1"
278 #define TSEC1_FLAGS TSEC_GIGABIT
279 #define TSEC1_PHY_ADDR 1
280 #define TSEC1_PHYIDX 0
281 #define CONFIG_HAS_ETH0
282
283 #define CONFIG_TSEC2 1
284 #define CONFIG_TSEC2_NAME "eTSEC2"
285 #define TSEC2_FLAGS TSEC_GIGABIT
286 #define TSEC2_PHY_ADDR 2
287 #define TSEC2_PHYIDX 0
288 #define CONFIG_HAS_ETH1
289
290 #define CONFIG_TSEC3 1
291 #define CONFIG_TSEC3_NAME "eTSEC3"
292 #define TSEC3_FLAGS TSEC_GIGABIT
293 #define TSEC3_PHY_ADDR 3
294 #define TSEC3_PHYIDX 0
295 #define CONFIG_HAS_ETH2
296
297 #define CONFIG_TSEC4 1
298 #define CONFIG_TSEC4_NAME "eTSEC4"
299 #define TSEC4_FLAGS TSEC_GIGABIT
300 #define TSEC4_PHY_ADDR 4
301 #define TSEC4_PHYIDX 0
302 #define CONFIG_HAS_ETH3
303
304 /*
305 * BOOTP options
306 */
307 #define CONFIG_BOOTP_BOOTFILESIZE
308 #define CONFIG_BOOTP_BOOTPATH
309 #define CONFIG_BOOTP_GATEWAY
310
311 /*
312 * Command configuration.
313 */
314 #include <config_cmd_default.h>
315
316 #define CONFIG_CMD_ASKENV
317 #define CONFIG_CMD_DATE
318 #define CONFIG_CMD_DHCP
319 #define CONFIG_CMD_EEPROM
320 #define CONFIG_CMD_ELF
321 #define CONFIG_CMD_SAVEENV
322 #define CONFIG_CMD_FLASH
323 #define CONFIG_CMD_I2C
324 #define CONFIG_CMD_JFFS2
325 #define CONFIG_CMD_MII
326 #define CONFIG_CMD_NAND
327 #define CONFIG_CMD_NET
328 #define CONFIG_CMD_PCA953X
329 #define CONFIG_CMD_PCA953X_INFO
330 #define CONFIG_CMD_PCI
331 #define CONFIG_CMD_PCI_ENUM
332 #define CONFIG_CMD_PING
333 #define CONFIG_CMD_SNTP
334 #define CONFIG_CMD_REGINFO
335
336 /*
337 * Miscellaneous configurable options
338 */
339 #define CONFIG_SYS_LONGHELP /* undef to save memory */
340 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
341 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
342 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
343 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
344 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
345 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
346 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
347 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
348 #define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
349 #define CONFIG_PANIC_HANG /* do not reset board on panic */
350 #define CONFIG_PREBOOT /* enable preboot variable */
351 #define CONFIG_FIT 1
352 #define CONFIG_FIT_VERBOSE 1
353 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
354 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
355
356 /*
357 * For booting Linux, the board info and command line data
358 * have to be in the first 16 MB of memory, since this is
359 * the maximum mapped by the Linux kernel during initialization.
360 */
361 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
362 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
363
364 /*
365 * Environment Configuration
366 */
367 #define CONFIG_ENV_IS_IN_FLASH 1
368 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
369 #define CONFIG_ENV_SIZE 0x8000
370 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
371
372 /*
373 * Flash memory map:
374 * fff80000 - ffffffff Pri U-Boot (512 KB)
375 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
376 * fff00000 - fff3ffff Pri FDT (256KB)
377 * fef00000 - ffefffff Pri OS image (16MB)
378 * fc000000 - feefffff Pri OS Use/Filesystem (47MB)
379 *
380 * fbf80000 - fbffffff Sec U-Boot (512 KB)
381 * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB)
382 * fbf00000 - fbf3ffff Sec FDT (256KB)
383 * faf00000 - fbefffff Sec OS image (16MB)
384 * f8000000 - faefffff Sec OS Use/Filesystem (47MB)
385 */
386 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
387 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xfbf80000)
388 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
389 #define CONFIG_FDT2_ENV_ADDR __stringify(0xfbf00000)
390 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
391 #define CONFIG_OS2_ENV_ADDR __stringify(0xfaf00000)
392
393 #define CONFIG_PROG_UBOOT1 \
394 "$download_cmd $loadaddr $ubootfile; " \
395 "if test $? -eq 0; then " \
396 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
397 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
398 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
399 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
400 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
401 "if test $? -ne 0; then " \
402 "echo PROGRAM FAILED; " \
403 "else; " \
404 "echo PROGRAM SUCCEEDED; " \
405 "fi; " \
406 "else; " \
407 "echo DOWNLOAD FAILED; " \
408 "fi;"
409
410 #define CONFIG_PROG_UBOOT2 \
411 "$download_cmd $loadaddr $ubootfile; " \
412 "if test $? -eq 0; then " \
413 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
414 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
415 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
416 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
417 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
418 "if test $? -ne 0; then " \
419 "echo PROGRAM FAILED; " \
420 "else; " \
421 "echo PROGRAM SUCCEEDED; " \
422 "fi; " \
423 "else; " \
424 "echo DOWNLOAD FAILED; " \
425 "fi;"
426
427 #define CONFIG_BOOT_OS_NET \
428 "$download_cmd $osaddr $osfile; " \
429 "if test $? -eq 0; then " \
430 "if test -n $fdtaddr; then " \
431 "$download_cmd $fdtaddr $fdtfile; " \
432 "if test $? -eq 0; then " \
433 "bootm $osaddr - $fdtaddr; " \
434 "else; " \
435 "echo FDT DOWNLOAD FAILED; " \
436 "fi; " \
437 "else; " \
438 "bootm $osaddr; " \
439 "fi; " \
440 "else; " \
441 "echo OS DOWNLOAD FAILED; " \
442 "fi;"
443
444 #define CONFIG_PROG_OS1 \
445 "$download_cmd $osaddr $osfile; " \
446 "if test $? -eq 0; then " \
447 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
448 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
449 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
450 "if test $? -ne 0; then " \
451 "echo OS PROGRAM FAILED; " \
452 "else; " \
453 "echo OS PROGRAM SUCCEEDED; " \
454 "fi; " \
455 "else; " \
456 "echo OS DOWNLOAD FAILED; " \
457 "fi;"
458
459 #define CONFIG_PROG_OS2 \
460 "$download_cmd $osaddr $osfile; " \
461 "if test $? -eq 0; then " \
462 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
463 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
464 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
465 "if test $? -ne 0; then " \
466 "echo OS PROGRAM FAILED; " \
467 "else; " \
468 "echo OS PROGRAM SUCCEEDED; " \
469 "fi; " \
470 "else; " \
471 "echo OS DOWNLOAD FAILED; " \
472 "fi;"
473
474 #define CONFIG_PROG_FDT1 \
475 "$download_cmd $fdtaddr $fdtfile; " \
476 "if test $? -eq 0; then " \
477 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
478 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
479 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
480 "if test $? -ne 0; then " \
481 "echo FDT PROGRAM FAILED; " \
482 "else; " \
483 "echo FDT PROGRAM SUCCEEDED; " \
484 "fi; " \
485 "else; " \
486 "echo FDT DOWNLOAD FAILED; " \
487 "fi;"
488
489 #define CONFIG_PROG_FDT2 \
490 "$download_cmd $fdtaddr $fdtfile; " \
491 "if test $? -eq 0; then " \
492 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
493 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
494 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
495 "if test $? -ne 0; then " \
496 "echo FDT PROGRAM FAILED; " \
497 "else; " \
498 "echo FDT PROGRAM SUCCEEDED; " \
499 "fi; " \
500 "else; " \
501 "echo FDT DOWNLOAD FAILED; " \
502 "fi;"
503
504 #define CONFIG_EXTRA_ENV_SETTINGS \
505 "autoload=yes\0" \
506 "download_cmd=tftp\0" \
507 "console_args=console=ttyS0,115200\0" \
508 "root_args=root=/dev/nfs rw\0" \
509 "misc_args=ip=on\0" \
510 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
511 "bootfile=/home/user/file\0" \
512 "osfile=/home/user/board.uImage\0" \
513 "fdtfile=/home/user/board.dtb\0" \
514 "ubootfile=/home/user/u-boot.bin\0" \
515 "fdtaddr=c00000\0" \
516 "osaddr=0x1000000\0" \
517 "loadaddr=0x1000000\0" \
518 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
519 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
520 "prog_os1="CONFIG_PROG_OS1"\0" \
521 "prog_os2="CONFIG_PROG_OS2"\0" \
522 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
523 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
524 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
525 "bootcmd_flash1=run set_bootargs; " \
526 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
527 "bootcmd_flash2=run set_bootargs; " \
528 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
529 "bootcmd=run bootcmd_flash1\0"
530 #endif /* __CONFIG_H */