include/configs/xpedite537x.h

   1 /*
   2  * Copyright 2008 Extreme Engineering Solutions, Inc.
   3  * Copyright 2007-2008 Freescale Semiconductor, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * xpedite537x board configuration file
  26  */
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /*
  31  * High Level Configuration Options
  32  */
  33 #define CONFIG_BOOKE            1       /* BOOKE */
  34 #define CONFIG_E500             1       /* BOOKE e500 family */
  35 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48 */
  36 #define CONFIG_MPC8572          1
  37 #define CONFIG_XPEDITE5370      1
  38 #define CONFIG_SYS_BOARD_NAME   "XPedite5370"
  39 #define CONFIG_SYS_FORM_3U_VPX  1
  40 #define CONFIG_BOARD_EARLY_INIT_R       /* Call board_pre_init */
  41
  42 #ifndef CONFIG_SYS_TEXT_BASE
  43 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  44 #endif
  45
  46 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  47 #define CONFIG_PCI_PNP          1       /* do pci plug-and-play */
  48 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup */
  49 #define CONFIG_PCIE1            1       /* PCIE controler 1 */
  50 #define CONFIG_PCIE2            1       /* PCIE controler 2 */
  51 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  52 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  53 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  54 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  55 #define CONFIG_FSL_ELBC         1
  56
  57 /*
  58  * Multicore config
  59  */
  60 #define CONFIG_MP
  61 #define CONFIG_BPTR_VIRT_ADDR   0xee000000      /* virt boot page address */
  62 #define CONFIG_MPC8xxx_DISABLE_BPTR             /* Don't leave BPTR enabled */
  63
  64 /*
  65  * DDR config
  66  */
  67 #define CONFIG_FSL_DDR2
  68 #undef CONFIG_FSL_DDR_INTERACTIVE
  69 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  70 #define CONFIG_DDR_SPD
  71 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  72 #define SPD_EEPROM_ADDRESS1             0x54    /* Both channels use the */
  73 #define SPD_EEPROM_ADDRESS2             0x54    /* same SPD data         */
  74 #define SPD_EEPROM_OFFSET               0x200   /* OFFSET of SPD in EEPROM */
  75 #define CONFIG_NUM_DDR_CONTROLLERS      2
  76 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  77 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
  78 #define CONFIG_DDR_ECC
  79 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  80 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000 /* DDR is system memory*/
  81 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  82 #define CONFIG_VERY_BIG_RAM
  83
  84 #ifndef __ASSEMBLY__
  85 extern unsigned long get_board_sys_clk(unsigned long dummy);
  86 extern unsigned long get_board_ddr_clk(unsigned long dummy);
  87 #endif
  88
  89 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /* sysclk for MPC85xx */
  90 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk(0) /* ddrclk for MPC85xx */
  91
  92 /*
  93  * These can be toggled for performance analysis, otherwise use default.
  94  */
  95 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  96 #define CONFIG_BTB                      /* toggle branch predition */
  97 #define CONFIG_ENABLE_36BIT_PHYS        1
  98
  99 /*
 100  * Base addresses -- Note these are effective addresses where the
 101  * actual resources get mapped (not physical addresses)
 102  */
 103 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
 104 #define CONFIG_SYS_CCSRBAR              0xef000000      /* relocated CCSRBAR */
 105 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
 106 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
 107
 108 /*
 109  * Diagnostics
 110  */
 111 #define CONFIG_SYS_ALT_MEMTEST
 112 #define CONFIG_SYS_MEMTEST_START        0x10000000
 113 #define CONFIG_SYS_MEMTEST_END          0x20000000
 114 #define CONFIG_POST                     (CONFIG_SYS_POST_MEMORY | \
 115                                          CONFIG_SYS_POST_I2C)
 116 #define I2C_ADDR_LIST                   {CONFIG_SYS_I2C_DS1621_ADDR,    \
 117                                          CONFIG_SYS_I2C_DS4510_ADDR,    \
 118                                          CONFIG_SYS_I2C_EEPROM_ADDR,    \
 119                                          CONFIG_SYS_I2C_LM90_ADDR,      \
 120                                          CONFIG_SYS_I2C_PCA953X_ADDR0,  \
 121                                          CONFIG_SYS_I2C_PCA953X_ADDR1,  \
 122                                          CONFIG_SYS_I2C_PCA953X_ADDR2,  \
 123                                          CONFIG_SYS_I2C_PCA953X_ADDR3,  \
 124                                          CONFIG_SYS_I2C_PEX8518_ADDR,   \
 125                                          CONFIG_SYS_I2C_RTC_ADDR}
 126 /* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */
 127 #define I2C_ADDR_IGNORE_LIST            {0x50}
 128
 129 /*
 130  * Memory map
 131  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
 132  * 0x8000_0000  0xbfff_ffff     PCIe1 Mem               1G non-cacheable
 133  * 0xc000_0000  0xcfff_ffff     PCIe2 Mem               256M non-cacheable
 134  * 0xe000_0000  0xe7ff_ffff     SRAM/SSRAM/L1 Cache     128M non-cacheable
 135  * 0xe800_0000  0xe87f_ffff     PCIe1 IO                8M non-cacheable
 136  * 0xe880_0000  0xe8ff_ffff     PCIe2 IO                8M non-cacheable
 137  * 0xee00_0000  0xee00_ffff     Boot page translation   4K non-cacheable
 138  * 0xef00_0000  0xef0f_ffff     CCSR/IMMR               1M non-cacheable
 139  * 0xef80_0000  0xef8f_ffff     NAND Flash              1M non-cacheable
 140  * 0xf000_0000  0xf7ff_ffff     NOR Flash 2             128M non-cacheable
 141  * 0xf800_0000  0xffff_ffff     NOR Flash 1             128M non-cacheable
 142  */
 143
 144 #define CONFIG_SYS_LBC_LCRR     (LCRR_CLKDIV_8 | LCRR_EADC_3)
 145
 146 /*
 147  * NAND flash configuration
 148  */
 149 #define CONFIG_SYS_NAND_BASE            0xef800000
 150 #define CONFIG_SYS_NAND_BASE2           0xef840000 /* Unused at this time */
 151 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE, \
 152                                          CONFIG_SYS_NAND_BASE2}
 153 #define CONFIG_SYS_MAX_NAND_DEVICE      2
 154 #define CONFIG_MTD_NAND_VERIFY_WRITE
 155 #define CONFIG_SYS_NAND_QUIET_TEST      /* 2nd NAND flash not always populated */
 156 #define CONFIG_NAND_FSL_ELBC
 157
 158 /*
 159  * NOR flash configuration
 160  */
 161 #define CONFIG_SYS_FLASH_BASE           0xf8000000
 162 #define CONFIG_SYS_FLASH_BASE2          0xf0000000
 163 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
 164 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 165 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 166 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 167 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 168 #define CONFIG_FLASH_CFI_DRIVER
 169 #define CONFIG_SYS_FLASH_CFI
 170 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 171 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST       { {0xfff40000, 0xc0000}, \
 172                                                   {0xf7f40000, 0xc0000} }
 173 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 174
 175 /*
 176  * Chip select configuration
 177  */
 178 /* NOR Flash 0 on CS0 */
 179 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE  | \
 180                                  BR_PS_16               | \
 181                                  BR_V)
 182 #define CONFIG_SYS_OR0_PRELIM   (OR_AM_128MB            | \
 183                                  OR_GPCM_CSNT           | \
 184                                  OR_GPCM_XACS           | \
 185                                  OR_GPCM_ACS_DIV2       | \
 186                                  OR_GPCM_SCY_8          | \
 187                                  OR_GPCM_TRLX           | \
 188                                  OR_GPCM_EHTR           | \
 189                                  OR_GPCM_EAD)
 190
 191 /* NOR Flash 1 on CS1 */
 192 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_FLASH_BASE2 | \
 193                                  BR_PS_16               | \
 194                                  BR_V)
 195 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 196
 197 /* NAND flash on CS2 */
 198 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_NAND_BASE   | \
 199                                  (2<<BR_DECC_SHIFT)     | \
 200                                  BR_PS_8                | \
 201                                  BR_MS_FCM              | \
 202                                  BR_V)
 203
 204 /* NAND flash on CS2 */
 205 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_256KB    | \
 206                                  OR_FCM_PGS     | \
 207                                  OR_FCM_CSCT    | \
 208                                  OR_FCM_CST     | \
 209                                  OR_FCM_CHT     | \
 210                                  OR_FCM_SCY_1   | \
 211                                  OR_FCM_TRLX    | \
 212                                  OR_FCM_EHTR)
 213
 214 /* NAND flash on CS3 */
 215 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_NAND_BASE2  | \
 216                                  (2<<BR_DECC_SHIFT)     | \
 217                                  BR_PS_8                | \
 218                                  BR_MS_FCM              | \
 219                                  BR_V)
 220 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 221
 222 /*
 223  * Use L1 as initial stack
 224  */
 225 #define CONFIG_SYS_INIT_RAM_LOCK        1
 226 #define CONFIG_SYS_INIT_RAM_ADDR        0xe0000000
 227 #define CONFIG_SYS_INIT_RAM_END         0x00004000
 228
 229 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* num bytes initial data */
 230 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 231 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 232
 233 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 KB for Mon */
 234 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 235
 236 /*
 237  * Serial Port
 238  */
 239 #define CONFIG_CONS_INDEX               1
 240 #define CONFIG_SYS_NS16550
 241 #define CONFIG_SYS_NS16550_SERIAL
 242 #define CONFIG_SYS_NS16550_REG_SIZE     1
 243 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 244 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 245 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 246 #define CONFIG_SYS_BAUDRATE_TABLE       \
 247         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 248 #define CONFIG_BAUDRATE                 115200
 249 #define CONFIG_LOADS_ECHO               1       /* echo on for serial download */
 250 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 251
 252 /*
 253  * Use the HUSH parser
 254  */
 255 #define CONFIG_SYS_HUSH_PARSER
 256 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 257
 258 /*
 259  * Pass open firmware flat tree
 260  */
 261 #define CONFIG_OF_LIBFDT                1
 262 #define CONFIG_OF_BOARD_SETUP           1
 263 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 264
 265 /*
 266  * I2C
 267  */
 268 #define CONFIG_FSL_I2C                          /* Use FSL common I2C driver */
 269 #define CONFIG_HARD_I2C                         /* I2C with hardware support */
 270 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 271 #define CONFIG_SYS_I2C_SLAVE            0x7F
 272 #define CONFIG_SYS_I2C_OFFSET           0x3000
 273 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 274 #define CONFIG_I2C_MULTI_BUS
 275
 276 /* PEX8518 slave I2C interface */
 277 #define CONFIG_SYS_I2C_PEX8518_ADDR     0x70
 278
 279 /* I2C DS1631 temperature sensor */
 280 #define CONFIG_SYS_I2C_DS1621_ADDR      0x48
 281 #define CONFIG_DTT_DS1621
 282 #define CONFIG_DTT_SENSORS              { 0 }
 283 #define CONFIG_SYS_I2C_LM90_ADDR        0x4c
 284
 285 /* I2C EEPROM - AT24C128B */
 286 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x54
 287 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 288 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6       /* 64 byte pages */
 289 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* take up to 10 msec */
 290
 291 /* I2C RTC */
 292 #define CONFIG_RTC_M41T11               1
 293 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 294 #define CONFIG_SYS_M41T11_BASE_YEAR     2000
 295
 296 /* GPIO/EEPROM/SRAM */
 297 #define CONFIG_DS4510
 298 #define CONFIG_SYS_I2C_DS4510_ADDR      0x51
 299
 300 /* GPIO */
 301 #define CONFIG_PCA953X
 302 #define CONFIG_SYS_I2C_PCA953X_ADDR0    0x18
 303 #define CONFIG_SYS_I2C_PCA953X_ADDR1    0x1c
 304 #define CONFIG_SYS_I2C_PCA953X_ADDR2    0x1e
 305 #define CONFIG_SYS_I2C_PCA953X_ADDR3    0x1f
 306 #define CONFIG_SYS_I2C_PCA953X_ADDR     CONFIG_SYS_I2C_PCA953X_ADDR0
 307
 308 /*
 309  * PU = pulled high, PD = pulled low
 310  * I = input, O = output, IO = input/output
 311  */
 312 /* PCA9557 @ 0x18*/
 313 #define CONFIG_SYS_PCA953X_C0_SER0_EN           0x01 /* PU; UART0 enable (1: enabled) */
 314 #define CONFIG_SYS_PCA953X_C0_SER0_MODE         0x02 /* PU; UART0 serial mode select */
 315 #define CONFIG_SYS_PCA953X_C0_SER1_EN           0x04 /* PU; UART1 enable (1: enabled) */
 316 #define CONFIG_SYS_PCA953X_C0_SER1_MODE         0x08 /* PU; UART1 serial mode select */
 317 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS     0x10 /* PU; Boot flash CS select */
 318 #define CONFIG_SYS_PCA953X_NVM_WP               0x20 /* PU; Set to 0 to enable NVM writing */
 319 #define CONFIG_SYS_PCA953X_C0_VCORE_VID2        0x40 /* VID2 of ISL6262 */
 320 #define CONFIG_SYS_PCA953X_C0_VCORE_VID3        0x80 /* VID3 of ISL6262 */
 321
 322 /* PCA9557 @ 0x1c*/
 323 #define CONFIG_SYS_PCA953X_XMC0_ROOT0           0x01 /* PU; Low if XMC is RC */
 324 #define CONFIG_SYS_PCA953X_XMC0_MVMR0           0x02 /* XMC EEPROM write protect */
 325 #define CONFIG_SYS_PCA953X_XMC0_WAKE            0x04 /* PU; XMC wake */
 326 #define CONFIG_SYS_PCA953X_XMC0_BIST            0x08 /* PU; XMC built in self test */
 327 #define CONFIG_SYS_PCA953X_XMC_PRESENT          0x10 /* PU; Low if XMC module installed */
 328 #define CONFIG_SYS_PCA953X_PMC_PRESENT          0x20 /* PU; Low if PMC module installed */
 329 #define CONFIG_SYS_PCA953X_PMC0_MONARCH         0x40 /* PMC monarch mode enable */
 330 #define CONFIG_SYS_PCA953X_PMC0_EREADY          0x80 /* PU; PMC PCI eready */
 331
 332 /* PCA9557 @ 0x1e*/
 333 #define CONFIG_SYS_PCA953X_P0_GA0               0x01 /* PU; VPX Geographical address */
 334 #define CONFIG_SYS_PCA953X_P0_GA1               0x02 /* PU; VPX Geographical address */
 335 #define CONFIG_SYS_PCA953X_P0_GA2               0x04 /* PU; VPX Geographical address */
 336 #define CONFIG_SYS_PCA953X_P0_GA3               0x08 /* PU; VPX Geographical address */
 337 #define CONFIG_SYS_PCA953X_P0_GA4               0x10 /* PU; VPX Geographical address */
 338 #define CONFIG_SYS_PCA953X_P0_GAP               0x20 /* PU; tied to VPX P0.GAP */
 339 #define CONFIG_SYS_PCA953X_P1_SYSEN             0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */
 340
 341 /* PCA9557 @ 0x1f */
 342 #define CONFIG_SYS_PCA953X_GPIO_VPX0            0x01 /* PU */
 343 #define CONFIG_SYS_PCA953X_GPIO_VPX1            0x02 /* PU */
 344 #define CONFIG_SYS_PCA953X_GPIO_VPX2            0x04 /* PU */
 345 #define CONFIG_SYS_PCA953X_GPIO_VPX3            0x08 /* PU */
 346 #define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL        0x10 /* PD; I2C master source for FRU SEEPROM */
 347
 348 /*
 349  * General PCI
 350  * Memory space is mapped 1-1, but I/O space must start from 0.
 351  */
 352 /* PCIE1 - VPX P1 */
 353 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 354 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BUS
 355 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x40000000      /* 1G */
 356 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 357 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe8000000
 358 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000      /* 8M */
 359
 360 /* PCIE2 - PEX8518 */
 361 #define CONFIG_SYS_PCIE2_MEM_BUS        0xc0000000
 362 #define CONFIG_SYS_PCIE2_MEM_PHYS       CONFIG_SYS_PCIE2_MEM_BUS
 363 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 364 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 365 #define CONFIG_SYS_PCIE2_IO_PHYS        0xe8800000
 366 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000      /* 8M */
 367
 368 /*
 369  * Networking options
 370  */
 371 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
 372 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 373 #define CONFIG_NET_MULTI        1
 374 #define CONFIG_TSEC_TBI
 375 #define CONFIG_MII              1       /* MII PHY management */
 376 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 377 #define CONFIG_ETHPRIME         "eTSEC2"
 378
 379 #define CONFIG_TSEC1            1
 380 #define CONFIG_TSEC1_NAME       "eTSEC1"
 381 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 382 #define TSEC1_PHY_ADDR          1
 383 #define TSEC1_PHYIDX            0
 384 #define CONFIG_HAS_ETH0
 385
 386 #define CONFIG_TSEC2            1
 387 #define CONFIG_TSEC2_NAME       "eTSEC2"
 388 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 389 #define TSEC2_PHY_ADDR          2
 390 #define TSEC2_PHYIDX            0
 391 #define CONFIG_HAS_ETH1
 392
 393 /*
 394  * Command configuration.
 395  */
 396 #include <config_cmd_default.h>
 397
 398 #define CONFIG_CMD_ASKENV
 399 #define CONFIG_CMD_DATE
 400 #define CONFIG_CMD_DHCP
 401 #define CONFIG_CMD_DS4510
 402 #define CONFIG_CMD_DS4510_INFO
 403 #define CONFIG_CMD_DTT
 404 #define CONFIG_CMD_EEPROM
 405 #define CONFIG_CMD_ELF
 406 #define CONFIG_CMD_FLASH
 407 #define CONFIG_CMD_I2C
 408 #define CONFIG_CMD_JFFS2
 409 #define CONFIG_CMD_MII
 410 #define CONFIG_CMD_NAND
 411 #define CONFIG_CMD_NET
 412 #define CONFIG_CMD_PCA953X
 413 #define CONFIG_CMD_PCA953X_INFO
 414 #define CONFIG_CMD_PCI
 415 #define CONFIG_CMD_PCI_ENUM
 416 #define CONFIG_CMD_PING
 417 #define CONFIG_CMD_SAVEENV
 418 #define CONFIG_CMD_SNTP
 419 #define CONFIG_CMD_REGINFO
 420
 421 /*
 422  * Miscellaneous configurable options
 423  */
 424 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 425 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 426 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 427 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 428 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 429 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 430 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 431 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 432 #define CONFIG_CMDLINE_EDITING  1               /* add command line history     */
 433 #define CONFIG_AUTO_COMPLETE    1               /* add autocompletion support */
 434 #define CONFIG_LOADADDR         0x1000000       /* default location for tftp and bootm */
 435 #define CONFIG_BOOTDELAY        3               /* -1 disables auto-boot */
 436 #define CONFIG_PANIC_HANG                       /* do not reset board on panic */
 437 #define CONFIG_PREBOOT                          /* enable preboot variable */
 438 #define CONFIG_FIT              1
 439 #define CONFIG_FIT_VERBOSE      1
 440 #define CONFIG_INTEGRITY                        /* support booting INTEGRITY OS */
 441
 442 /*
 443  * For booting Linux, the board info and command line data
 444  * have to be in the first 16 MB of memory, since this is
 445  * the maximum mapped by the Linux kernel during initialization.
 446  */
 447 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)      /* Initial Memory map for Linux*/
 448 #define CONFIG_SYS_BOOTM_LEN    (16 << 20)      /* Increase max gunzip size */
 449
 450 /*
 451  * Environment Configuration
 452  */
 453 #define CONFIG_ENV_IS_IN_FLASH  1
 454 #define CONFIG_ENV_SECT_SIZE    0x20000         /* 128k (one sector) for env */
 455 #define CONFIG_ENV_SIZE         0x8000
 456 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
 457
 458 /*
 459  * Flash memory map:
 460  * fff80000 - ffffffff     Pri U-Boot (512 KB)
 461  * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
 462  * fff00000 - fff3ffff     Pri FDT (256KB)
 463  * fef00000 - ffefffff     Pri OS image (16MB)
 464  * f8000000 - feefffff     Pri OS Use/Filesystem (111MB)
 465  *
 466  * f7f80000 - f7ffffff     Sec U-Boot (512 KB)
 467  * f7f40000 - f7f7ffff     Sec U-Boot Environment (256 KB)
 468  * f7f00000 - f7f3ffff     Sec FDT (256KB)
 469  * f6f00000 - f7efffff     Sec OS image (16MB)
 470  * f0000000 - f6efffff     Sec OS Use/Filesystem (111MB)
 471  */
 472 #define CONFIG_UBOOT1_ENV_ADDR  MK_STR(0xfff80000)
 473 #define CONFIG_UBOOT2_ENV_ADDR  MK_STR(0xf7f80000)
 474 #define CONFIG_FDT1_ENV_ADDR    MK_STR(0xfff00000)
 475 #define CONFIG_FDT2_ENV_ADDR    MK_STR(0xf7f00000)
 476 #define CONFIG_OS1_ENV_ADDR     MK_STR(0xfef00000)
 477 #define CONFIG_OS2_ENV_ADDR     MK_STR(0xf6f00000)
 478
 479 #define CONFIG_PROG_UBOOT1                                              \
 480         "$download_cmd $loadaddr $ubootfile; "                          \
 481         "if test $? -eq 0; then "                                       \
 482                 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "         \
 483                 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "               \
 484                 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "       \
 485                 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "          \
 486                 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "      \
 487                 "if test $? -ne 0; then "                               \
 488                         "echo PROGRAM FAILED; "                         \
 489                 "else; "                                                \
 490                         "echo PROGRAM SUCCEEDED; "                      \
 491                 "fi; "                                                  \
 492         "else; "                                                        \
 493                 "echo DOWNLOAD FAILED; "                                \
 494         "fi;"
 495
 496 #define CONFIG_PROG_UBOOT2                                              \
 497         "$download_cmd $loadaddr $ubootfile; "                          \
 498         "if test $? -eq 0; then "                                       \
 499                 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "         \
 500                 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "               \
 501                 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "       \
 502                 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "          \
 503                 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "      \
 504                 "if test $? -ne 0; then "                               \
 505                         "echo PROGRAM FAILED; "                         \
 506                 "else; "                                                \
 507                         "echo PROGRAM SUCCEEDED; "                      \
 508                 "fi; "                                                  \
 509         "else; "                                                        \
 510                 "echo DOWNLOAD FAILED; "                                \
 511         "fi;"
 512
 513 #define CONFIG_BOOT_OS_NET                                              \
 514         "$download_cmd $osaddr $osfile; "                               \
 515         "if test $? -eq 0; then "                                       \
 516                 "if test -n $fdtaddr; then "                            \
 517                         "$download_cmd $fdtaddr $fdtfile; "             \
 518                         "if test $? -eq 0; then "                       \
 519                                 "bootm $osaddr - $fdtaddr; "            \
 520                         "else; "                                        \
 521                                 "echo FDT DOWNLOAD FAILED; "            \
 522                         "fi; "                                          \
 523                 "else; "                                                \
 524                         "bootm $osaddr; "                               \
 525                 "fi; "                                                  \
 526         "else; "                                                        \
 527                 "echo OS DOWNLOAD FAILED; "                             \
 528         "fi;"
 529
 530 #define CONFIG_PROG_OS1                                                 \
 531         "$download_cmd $osaddr $osfile; "                               \
 532         "if test $? -eq 0; then "                                       \
 533                 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; "              \
 534                 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "        \
 535                 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "       \
 536                 "if test $? -ne 0; then "                               \
 537                         "echo OS PROGRAM FAILED; "                      \
 538                 "else; "                                                \
 539                         "echo OS PROGRAM SUCCEEDED; "                   \
 540                 "fi; "                                                  \
 541         "else; "                                                        \
 542                 "echo OS DOWNLOAD FAILED; "                             \
 543         "fi;"
 544
 545 #define CONFIG_PROG_OS2                                                 \
 546         "$download_cmd $osaddr $osfile; "                               \
 547         "if test $? -eq 0; then "                                       \
 548                 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; "              \
 549                 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "        \
 550                 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "       \
 551                 "if test $? -ne 0; then "                               \
 552                         "echo OS PROGRAM FAILED; "                      \
 553                 "else; "                                                \
 554                         "echo OS PROGRAM SUCCEEDED; "                   \
 555                 "fi; "                                                  \
 556         "else; "                                                        \
 557                 "echo OS DOWNLOAD FAILED; "                             \
 558         "fi;"
 559
 560 #define CONFIG_PROG_FDT1                                                \
 561         "$download_cmd $fdtaddr $fdtfile; "                             \
 562         "if test $? -eq 0; then "                                       \
 563                 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"              \
 564                 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "      \
 565                 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "     \
 566                 "if test $? -ne 0; then "                               \
 567                         "echo FDT PROGRAM FAILED; "                     \
 568                 "else; "                                                \
 569                         "echo FDT PROGRAM SUCCEEDED; "                  \
 570                 "fi; "                                                  \
 571         "else; "                                                        \
 572                 "echo FDT DOWNLOAD FAILED; "                            \
 573         "fi;"
 574
 575 #define CONFIG_PROG_FDT2                                                \
 576         "$download_cmd $fdtaddr $fdtfile; "                             \
 577         "if test $? -eq 0; then "                                       \
 578                 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"              \
 579                 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "      \
 580                 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "     \
 581                 "if test $? -ne 0; then "                               \
 582                         "echo FDT PROGRAM FAILED; "                     \
 583                 "else; "                                                \
 584                         "echo FDT PROGRAM SUCCEEDED; "                  \
 585                 "fi; "                                                  \
 586         "else; "                                                        \
 587                 "echo FDT DOWNLOAD FAILED; "                            \
 588         "fi;"
 589
 590 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 591         "autoload=yes\0"                                                \
 592         "download_cmd=tftp\0"                                           \
 593         "console_args=console=ttyS0,115200\0"                           \
 594         "root_args=root=/dev/nfs rw\0"                                  \
 595         "misc_args=ip=on\0"                                             \
 596         "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
 597         "bootfile=/home/user/file\0"                                    \
 598         "osfile=/home/user/board.uImage\0"                              \
 599         "fdtfile=/home/user/board.dtb\0"                                \
 600         "ubootfile=/home/user/u-boot.bin\0"                             \
 601         "fdtaddr=c00000\0"                                              \
 602         "osaddr=0x1000000\0"                                            \
 603         "loadaddr=0x1000000\0"                                          \
 604         "prog_uboot1="CONFIG_PROG_UBOOT1"\0"                            \
 605         "prog_uboot2="CONFIG_PROG_UBOOT2"\0"                            \
 606         "prog_os1="CONFIG_PROG_OS1"\0"                                  \
 607         "prog_os2="CONFIG_PROG_OS2"\0"                                  \
 608         "prog_fdt1="CONFIG_PROG_FDT1"\0"                                \
 609         "prog_fdt2="CONFIG_PROG_FDT2"\0"                                \
 610         "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"          \
 611         "bootcmd_flash1=run set_bootargs; "                             \
 612                 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
 613         "bootcmd_flash2=run set_bootargs; "                             \
 614                 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
 615         "bootcmd=run bootcmd_flash1\0"
 616 #endif  /* __CONFIG_H */