include/configs/yucca.h

   1 /*
   2  * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /************************************************************************
  24  * 1 january 2005       Alain Saurel <asaurel@amcc.com>
  25  * Adapted to current Das U-Boot source
  26  ***********************************************************************/
  27 /************************************************************************
  28  * yucca.h - configuration for AMCC 440SPe Ref (yucca)
  29  ***********************************************************************/
  30
  31 #ifndef __CONFIG_H
  32 #define __CONFIG_H
  33
  34 /*-----------------------------------------------------------------------
  35  * High Level Configuration Options
  36  *----------------------------------------------------------------------*/
  37 #define CONFIG_4xx                      1       /* ... PPC4xx family    */
  38 #define CONFIG_440                      1       /* ... PPC440 family    */
  39 #define CONFIG_440SPE                   1       /* Specifc SPe support  */
  40 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init  */
  41 #define CONFIG_SYS_CLK_FREQ     33333333        /* external freq to pll */
  42 #define EXTCLK_33_33            33333333
  43 #define EXTCLK_66_66            66666666
  44 #define EXTCLK_50               50000000
  45 #define EXTCLK_83               83333333
  46
  47 /*
  48  * Include common defines/options for all AMCC eval boards
  49  */
  50 #define CONFIG_HOSTNAME         yucca
  51 #include "amcc-common.h"
  52
  53 #define CONFIG_MISC_INIT_F      1       /* Use misc_init_f()            */
  54 #undef  CONFIG_SHOW_BOOT_PROGRESS
  55 #undef  CONFIG_STRESS
  56
  57 /*-----------------------------------------------------------------------
  58  * Base addresses -- Note these are effective addresses where the
  59  * actual resources get mapped (not physical addresses)
  60  *----------------------------------------------------------------------*/
  61 #define CFG_FLASH_BASE          0xfff00000      /* start of FLASH       */
  62 #define CFG_PERIPHERAL_BASE     0xa0000000      /* internal peripherals */
  63 #define CFG_ISRAM_BASE          0x90000000      /* internal SRAM        */
  64
  65 #define CFG_PCI_MEMBASE         0x80000000      /* mapped PCI memory    */
  66 #define CFG_PCI_BASE            0xd0000000      /* internal PCI regs    */
  67 #define CFG_PCI_TARGBASE        CFG_PCI_MEMBASE
  68
  69 #define CFG_PCIE_MEMBASE        0xb0000000      /* mapped PCIe memory   */
  70 #define CFG_PCIE_MEMSIZE        0x08000000      /* smallest incr for PCIe port */
  71 #define CFG_PCIE_BASE           0xe0000000      /* PCIe UTL regs */
  72
  73 #define CFG_PCIE0_CFGBASE       0xc0000000
  74 #define CFG_PCIE1_CFGBASE       0xc1000000
  75 #define CFG_PCIE2_CFGBASE       0xc2000000
  76 #define CFG_PCIE0_XCFGBASE      0xc3000000
  77 #define CFG_PCIE1_XCFGBASE      0xc3001000
  78 #define CFG_PCIE2_XCFGBASE      0xc3002000
  79
  80 /* base address of inbound PCIe window */
  81 #define CFG_PCIE_INBOUND_BASE   0x0000000400000000ULL
  82
  83 /* System RAM mapped to PCI space */
  84 #define CONFIG_PCI_SYS_MEM_BUS  CFG_SDRAM_BASE
  85 #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
  86 #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
  87
  88 #define CFG_FPGA_BASE           0xe2000000      /* epld                 */
  89 #define CFG_OPER_FLASH          0xe7000000      /* SRAM - OPER Flash    */
  90
  91 /* #define CFG_NVRAM_BASE_ADDR 0x08000000 */
  92 /*-----------------------------------------------------------------------
  93  * Initial RAM & stack pointer (placed in internal SRAM)
  94  *----------------------------------------------------------------------*/
  95 #define CFG_TEMP_STACK_OCM      1
  96 #define CFG_OCM_DATA_ADDR       CFG_ISRAM_BASE
  97 #define CFG_INIT_RAM_ADDR       CFG_ISRAM_BASE  /* Initial RAM address  */
  98 #define CFG_INIT_RAM_END        0x2000          /* End of used area in RAM */
  99 #define CFG_GBL_DATA_SIZE       128             /* num bytes initial data */
 100
 101 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 102 #define CFG_POST_WORD_ADDR      (CFG_GBL_DATA_OFFSET - 0x4)
 103 #define CFG_INIT_SP_OFFSET      CFG_POST_WORD_ADDR
 104
 105 /*-----------------------------------------------------------------------
 106  * Serial Port
 107  *----------------------------------------------------------------------*/
 108 #undef CONFIG_UART1_CONSOLE
 109
 110 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 111 #undef CFG_EXT_SERIAL_CLOCK
 112 /* #define CFG_EXT_SERIAL_CLOCK (1843200 * 6) */ /* Ext clk @ 11.059 MHz */
 113
 114 /*-----------------------------------------------------------------------
 115  * DDR SDRAM
 116  *----------------------------------------------------------------------*/
 117 #define CONFIG_SPD_EEPROM       1       /* Use SPD EEPROM for setup     */
 118 #define SPD_EEPROM_ADDRESS      {0x53, 0x52}    /* SPD i2c spd addresses*/
 119 #define CONFIG_DDR_ECC          1       /* with ECC support             */
 120
 121 /*-----------------------------------------------------------------------
 122  * I2C
 123  *----------------------------------------------------------------------*/
 124 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 125
 126 #define IIC0_BOOTPROM_ADDR      0x50
 127 #define IIC0_ALT_BOOTPROM_ADDR  0x54
 128
 129 /* Don't probe these addrs */
 130 #define CFG_I2C_NOPROBES        {0x50, 0x52, 0x53, 0x54}
 131
 132 /* #if defined(CONFIG_CMD_EEPROM) */
 133 /* #define CFG_I2C_EEPROM_ADDR  0x50 */ /* I2C boot EEPROM              */
 134 #define CFG_I2C_EEPROM_ADDR_LEN 2       /* Bytes of address             */
 135 /* #endif */
 136
 137 /*-----------------------------------------------------------------------
 138  * Environment
 139  *----------------------------------------------------------------------*/
 140 /* #define CFG_NVRAM_SIZE       (0x2000 - 8) */ /* NVRAM size(8k)- RTC regs */
 141
 142 #undef  CONFIG_ENV_IS_IN_NVRAM          /* ... not in NVRAM             */
 143 #define CONFIG_ENV_IS_IN_FLASH  1       /* Environment uses flash       */
 144 #undef  CONFIG_ENV_IS_IN_EEPROM         /* ... not in EEPROM            */
 145 #define CONFIG_ENV_OVERWRITE    1
 146
 147 /*
 148  * Default environment variables
 149  */
 150 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 151         CONFIG_AMCC_DEF_ENV                                             \
 152         CONFIG_AMCC_DEF_ENV_PPC                                         \
 153         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 154         "kernel_addr=E7F10000\0"                                        \
 155         "ramdisk_addr=E7F20000\0"                                       \
 156         "pciconfighost=1\0"                                             \
 157         "pcie_mode=RP:EP:EP\0"                                          \
 158         ""
 159
 160 /*
 161  * Commands additional to the ones defined in amcc-common.h
 162  */
 163 #define CONFIG_CMD_PCI
 164 #define CONFIG_CMD_SDRAM
 165
 166 #define CONFIG_IBM_EMAC4_V4     1
 167 #define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
 168 #define CONFIG_HAS_ETH0
 169 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 170 #define CONFIG_PHY_RESET_DELAY  1000
 171 #define CONFIG_CIS8201_PHY      1       /* Enable 'special' RGMII mode for Cicada phy */
 172 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 173
 174 /*-----------------------------------------------------------------------
 175  * FLASH related
 176  *----------------------------------------------------------------------*/
 177 #define CFG_MAX_FLASH_BANKS     3       /* number of banks              */
 178 #define CFG_MAX_FLASH_SECT      256     /* sectors per device           */
 179
 180 #undef  CFG_FLASH_CHECKSUM
 181 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms) */
 182 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms) */
 183
 184 #define CFG_FLASH_ADDR0         0x5555
 185 #define CFG_FLASH_ADDR1         0x2aaa
 186 #define CFG_FLASH_WORD_SIZE     unsigned char
 187
 188 #define CFG_FLASH_2ND_16BIT_DEV 1       /* evb440SPe has 8 and 16bit device */
 189 #define CFG_FLASH_2ND_ADDR      0xe7c00000 /* evb440SPe has 8 and 16bit device*/
 190
 191 #ifdef CONFIG_ENV_IS_IN_FLASH
 192 #define CONFIG_ENV_SECT_SIZE    0x10000 /* size of one complete sector  */
 193 #define CONFIG_ENV_ADDR         0xfffa0000
 194 /* #define CONFIG_ENV_ADDR              (CFG_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) */
 195 #define CONFIG_ENV_SIZE         0x10000 /* Size of Environment vars     */
 196 #endif /* CONFIG_ENV_IS_IN_FLASH */
 197 /*-----------------------------------------------------------------------
 198  * PCI stuff
 199  *-----------------------------------------------------------------------
 200  */
 201 /* General PCI */
 202 #define CONFIG_PCI                      /* include pci support          */
 203 #define CONFIG_PCI_PNP          1       /* do pci plug-and-play         */
 204 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
 205 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
 206
 207 /* Board-specific PCI */
 208 #define CFG_PCI_TARGET_INIT             /* let board init pci target    */
 209 #undef  CFG_PCI_MASTER_INIT
 210
 211 #define CFG_PCI_SUBSYS_VENDORID 0x1014  /* IBM                          */
 212 #define CFG_PCI_SUBSYS_DEVICEID 0xcafe  /* Whatever                     */
 213 /* #define CFG_PCI_SUBSYS_ID    CFG_PCI_SUBSYS_DEVICEID */
 214
 215 /*
 216  *  NETWORK Support (PCI):
 217  */
 218 /* Support for Intel 82557/82559/82559ER chips. */
 219 #define CONFIG_EEPRO100
 220
 221 /* FB Divisor selection */
 222 #define FPGA_FB_DIV_6           6
 223 #define FPGA_FB_DIV_10          10
 224 #define FPGA_FB_DIV_12          12
 225 #define FPGA_FB_DIV_20          20
 226
 227 /* VCO Divisor selection */
 228 #define FPGA_VCO_DIV_4          4
 229 #define FPGA_VCO_DIV_6          6
 230 #define FPGA_VCO_DIV_8          8
 231 #define FPGA_VCO_DIV_10         10
 232
 233 /*----------------------------------------------------------------------------+
 234 | FPGA registers and bit definitions
 235 +----------------------------------------------------------------------------*/
 236 /* PowerPC 440SPe Board FPGA is reached with physical address 0x1 E2000000. */
 237 /* TLB initialization makes it correspond to logical address 0xE2000000. */
 238 /* => Done init_chip.s in bootlib */
 239 #define FPGA_REG_BASE_ADDR      0xE2000000
 240 #define FPGA_GPIO_BASE_ADDR     0xE2010000
 241 #define FPGA_INT_BASE_ADDR      0xE2020000
 242
 243 /*----------------------------------------------------------------------------+
 244 | Display
 245 +----------------------------------------------------------------------------*/
 246 #define PPC440SPE_DISPLAY       FPGA_REG_BASE_ADDR
 247
 248 #define PPC440SPE_DISPLAY_D8    (FPGA_REG_BASE_ADDR+0x06)
 249 #define PPC440SPE_DISPLAY_D4    (FPGA_REG_BASE_ADDR+0x04)
 250 #define PPC440SPE_DISPLAY_D2    (FPGA_REG_BASE_ADDR+0x02)
 251 #define PPC440SPE_DISPLAY_D1    (FPGA_REG_BASE_ADDR+0x00)
 252 /*define   WRITE_DISPLAY_DIGIT(n) IOREG8(FPGA_REG_BASE_ADDR + (2*n))*/
 253 /*#define   IOREG8(addr) *((volatile unsigned char *)(addr))*/
 254
 255 /*----------------------------------------------------------------------------+
 256 | ethernet/reset/boot Register 1
 257 +----------------------------------------------------------------------------*/
 258 #define FPGA_REG10      (FPGA_REG_BASE_ADDR+0x10)
 259
 260 #define FPGA_REG10_10MHZ_ENABLE         0x8000
 261 #define FPGA_REG10_100MHZ_ENABLE        0x4000
 262 #define FPGA_REG10_GIGABIT_ENABLE       0x2000
 263 #define FPGA_REG10_FULL_DUPLEX          0x1000  /* force Full Duplex*/
 264 #define FPGA_REG10_RESET_ETH            0x0800
 265 #define FPGA_REG10_AUTO_NEG_DIS         0x0400
 266 #define FPGA_REG10_INTP_ETH             0x0200
 267
 268 #define FPGA_REG10_RESET_HISR           0x0080
 269 #define FPGA_REG10_ENABLE_DISPLAY       0x0040
 270 #define FPGA_REG10_RESET_SDRAM          0x0020
 271 #define FPGA_REG10_OPER_BOOT            0x0010
 272 #define FPGA_REG10_SRAM_BOOT            0x0008
 273 #define FPGA_REG10_SMALL_BOOT           0x0004
 274 #define FPGA_REG10_FORCE_COLA           0x0002
 275 #define FPGA_REG10_COLA_MANUAL          0x0001
 276
 277 #define FPGA_REG10_SDRAM_ENABLE         0x0020
 278
 279 #define FPGA_REG10_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*from ocotea ?*/
 280 #define FPGA_REG10_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*from ocotea ?*/
 281
 282 /*----------------------------------------------------------------------------+
 283 | MUX control
 284 +----------------------------------------------------------------------------*/
 285 #define FPGA_REG12      (FPGA_REG_BASE_ADDR+0x12)
 286
 287 #define FPGA_REG12_EBC_CTL              0x8000
 288 #define FPGA_REG12_UART1_CTS_RTS        0x4000
 289 #define FPGA_REG12_UART0_RX_ENABLE      0x2000
 290 #define FPGA_REG12_UART1_RX_ENABLE      0x1000
 291 #define FPGA_REG12_UART2_RX_ENABLE      0x0800
 292 #define FPGA_REG12_EBC_OUT_ENABLE       0x0400
 293 #define FPGA_REG12_GPIO0_OUT_ENABLE     0x0200
 294 #define FPGA_REG12_GPIO1_OUT_ENABLE     0x0100
 295 #define FPGA_REG12_GPIO_SELECT          0x0010
 296 #define FPGA_REG12_GPIO_CHREG           0x0008
 297 #define FPGA_REG12_GPIO_CLK_CHREG       0x0004
 298 #define FPGA_REG12_GPIO_OETRI           0x0002
 299 #define FPGA_REG12_EBC_ERROR            0x0001
 300
 301 /*----------------------------------------------------------------------------+
 302 | PCI Clock control
 303 +----------------------------------------------------------------------------*/
 304 #define FPGA_REG16      (FPGA_REG_BASE_ADDR+0x16)
 305
 306 #define FPGA_REG16_PCI_CLK_CTL0         0x8000
 307 #define FPGA_REG16_PCI_CLK_CTL1         0x4000
 308 #define FPGA_REG16_PCI_CLK_CTL2         0x2000
 309 #define FPGA_REG16_PCI_CLK_CTL3         0x1000
 310 #define FPGA_REG16_PCI_CLK_CTL4         0x0800
 311 #define FPGA_REG16_PCI_CLK_CTL5         0x0400
 312 #define FPGA_REG16_PCI_CLK_CTL6         0x0200
 313 #define FPGA_REG16_PCI_CLK_CTL7         0x0100
 314 #define FPGA_REG16_PCI_CLK_CTL8         0x0080
 315 #define FPGA_REG16_PCI_CLK_CTL9         0x0040
 316 #define FPGA_REG16_PCI_EXT_ARB0         0x0020
 317 #define FPGA_REG16_PCI_MODE_1           0x0010
 318 #define FPGA_REG16_PCI_TARGET_MODE      0x0008
 319 #define FPGA_REG16_PCI_INTP_MODE        0x0004
 320
 321 /* FB1 Divisor selection */
 322 #define FPGA_REG16_FB2_DIV_MASK         0x1000
 323 #define FPGA_REG16_FB2_DIV_LOW          0x0000
 324 #define FPGA_REG16_FB2_DIV_HIGH         0x1000
 325 /* FB2 Divisor selection */
 326 /* S3 switch on Board */
 327 #define FPGA_REG16_FB1_DIV_MASK         0x2000
 328 #define FPGA_REG16_FB1_DIV_LOW          0x0000
 329 #define FPGA_REG16_FB1_DIV_HIGH         0x2000
 330 /* PCI0 Clock Selection */
 331 /* S3 switch on Board */
 332 #define FPGA_REG16_PCI0_CLK_MASK        0x0c00
 333 #define FPGA_REG16_PCI0_CLK_33_33       0x0000
 334 #define FPGA_REG16_PCI0_CLK_66_66       0x0800
 335 #define FPGA_REG16_PCI0_CLK_100         0x0400
 336 #define FPGA_REG16_PCI0_CLK_133_33      0x0c00
 337 /* VCO Divisor selection */
 338 /* S3 switch on Board */
 339 #define FPGA_REG16_VCO_DIV_MASK         0xc000
 340 #define FPGA_REG16_VCO_DIV_4            0x0000
 341 #define FPGA_REG16_VCO_DIV_8            0x4000
 342 #define FPGA_REG16_VCO_DIV_6            0x8000
 343 #define FPGA_REG16_VCO_DIV_10           0xc000
 344 /* Master Clock Selection */
 345 /* S3, S4 switches on Board */
 346 #define FPGA_REG16_MASTER_CLK_MASK      0x01c0
 347 #define FPGA_REG16_MASTER_CLK_EXT       0x0000
 348 #define FPGA_REG16_MASTER_CLK_66_66     0x0040
 349 #define FPGA_REG16_MASTER_CLK_50        0x0080
 350 #define FPGA_REG16_MASTER_CLK_33_33     0x00c0
 351 #define FPGA_REG16_MASTER_CLK_25        0x0100
 352
 353 /*----------------------------------------------------------------------------+
 354 | PCI Miscellaneous
 355 +----------------------------------------------------------------------------*/
 356 #define FPGA_REG18      (FPGA_REG_BASE_ADDR+0x18)
 357
 358 #define FPGA_REG18_PCI_PRSNT1           0x8000
 359 #define FPGA_REG18_PCI_PRSNT2           0x4000
 360 #define FPGA_REG18_PCI_INTA             0x2000
 361 #define FPGA_REG18_PCI_SLOT0_INTP       0x1000
 362 #define FPGA_REG18_PCI_SLOT1_INTP       0x0800
 363 #define FPGA_REG18_PCI_SLOT2_INTP       0x0400
 364 #define FPGA_REG18_PCI_SLOT3_INTP       0x0200
 365 #define FPGA_REG18_PCI_PCI0_VC          0x0100
 366 #define FPGA_REG18_PCI_PCI0_VTH1        0x0080
 367 #define FPGA_REG18_PCI_PCI0_VTH2        0x0040
 368 #define FPGA_REG18_PCI_PCI0_VTH3        0x0020
 369
 370 /*----------------------------------------------------------------------------+
 371 | PCIe Miscellaneous
 372 +----------------------------------------------------------------------------*/
 373 #define FPGA_REG1A      (FPGA_REG_BASE_ADDR+0x1A)
 374
 375 #define FPGA_REG1A_PE0_GLED             0x8000
 376 #define FPGA_REG1A_PE1_GLED             0x4000
 377 #define FPGA_REG1A_PE2_GLED             0x2000
 378 #define FPGA_REG1A_PE0_YLED             0x1000
 379 #define FPGA_REG1A_PE1_YLED             0x0800
 380 #define FPGA_REG1A_PE2_YLED             0x0400
 381 #define FPGA_REG1A_PE0_PWRON            0x0200
 382 #define FPGA_REG1A_PE1_PWRON            0x0100
 383 #define FPGA_REG1A_PE2_PWRON            0x0080
 384 #define FPGA_REG1A_PE0_REFCLK_ENABLE    0x0040
 385 #define FPGA_REG1A_PE1_REFCLK_ENABLE    0x0020
 386 #define FPGA_REG1A_PE2_REFCLK_ENABLE    0x0010
 387 #define FPGA_REG1A_PE_SPREAD0           0x0008
 388 #define FPGA_REG1A_PE_SPREAD1           0x0004
 389 #define FPGA_REG1A_PE_SELSOURCE_0       0x0002
 390 #define FPGA_REG1A_PE_SELSOURCE_1       0x0001
 391
 392 /*----------------------------------------------------------------------------+
 393 | PCIe Miscellaneous
 394 +----------------------------------------------------------------------------*/
 395 #define FPGA_REG1C      (FPGA_REG_BASE_ADDR+0x1C)
 396
 397 #define FPGA_REG1C_PE0_ROOTPOINT        0x8000
 398 #define FPGA_REG1C_PE1_ENDPOINT         0x4000
 399 #define FPGA_REG1C_PE2_ENDPOINT         0x2000
 400 #define FPGA_REG1C_PE0_PRSNT            0x1000
 401 #define FPGA_REG1C_PE1_PRSNT            0x0800
 402 #define FPGA_REG1C_PE2_PRSNT            0x0400
 403 #define FPGA_REG1C_PE0_WAKE             0x0080
 404 #define FPGA_REG1C_PE1_WAKE             0x0040
 405 #define FPGA_REG1C_PE2_WAKE             0x0020
 406 #define FPGA_REG1C_PE0_PERST            0x0010
 407 #define FPGA_REG1C_PE1_PERST            0x0008
 408 #define FPGA_REG1C_PE2_PERST            0x0004
 409
 410 /*----------------------------------------------------------------------------+
 411 | Defines
 412 +----------------------------------------------------------------------------*/
 413 #define PERIOD_133_33MHZ        7500    /* 7,5ns */
 414 #define PERIOD_100_00MHZ        10000   /* 10ns */
 415 #define PERIOD_83_33MHZ         12000   /* 12ns */
 416 #define PERIOD_75_00MHZ         13333   /* 13,333ns */
 417 #define PERIOD_66_66MHZ         15000   /* 15ns */
 418 #define PERIOD_50_00MHZ         20000   /* 20ns */
 419 #define PERIOD_33_33MHZ         30000   /* 30ns */
 420 #define PERIOD_25_00MHZ         40000   /* 40ns */
 421
 422 #endif  /* __CONFIG_H */