include/configs/yucca.h

   1 /*
   2  * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /************************************************************************
  24  * 1 january 2005       Alain Saurel <asaurel@amcc.com>
  25  * Adapted to current Das U-Boot source
  26  ***********************************************************************/
  27 /************************************************************************
  28  * yucca.h - configuration for AMCC 440SPe Ref (yucca)
  29  ***********************************************************************/
  30
  31 #ifndef __CONFIG_H
  32 #define __CONFIG_H
  33
  34 /*-----------------------------------------------------------------------
  35  * High Level Configuration Options
  36  *----------------------------------------------------------------------*/
  37 #define CONFIG_4xx                      1       /* ... PPC4xx family    */
  38 #define CONFIG_440                      1       /* ... PPC440 family    */
  39 #define CONFIG_440SPE                   1       /* Specifc SPe support  */
  40 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init  */
  41 #undef  CFG_DRAM_TEST                           /* Disable-takes long time */
  42 #define CONFIG_SYS_CLK_FREQ     33333333        /* external freq to pll */
  43 #define EXTCLK_33_33            33333333
  44 #define EXTCLK_66_66            66666666
  45 #define EXTCLK_50               50000000
  46 #define EXTCLK_83               83333333
  47
  48 #define CONFIG_MISC_INIT_F      1       /* Use misc_init_f()            */
  49 #undef  CONFIG_SHOW_BOOT_PROGRESS
  50 #undef  CONFIG_STRESS
  51
  52 /*-----------------------------------------------------------------------
  53  * Base addresses -- Note these are effective addresses where the
  54  * actual resources get mapped (not physical addresses)
  55  *----------------------------------------------------------------------*/
  56 #define CFG_SDRAM_BASE          0x00000000      /* _must_ be 0          */
  57 #define CFG_FLASH_BASE          0xfff00000      /* start of FLASH       */
  58 #define CFG_MONITOR_BASE        0xfffb0000      /* start of monitor     */
  59 #define CFG_PERIPHERAL_BASE     0xa0000000      /* internal peripherals */
  60 #define CFG_ISRAM_BASE          0x90000000      /* internal SRAM        */
  61
  62 #define CFG_PCI_MEMBASE         0x80000000      /* mapped PCI memory    */
  63 #define CFG_PCI_BASE            0xd0000000      /* internal PCI regs    */
  64 #define CFG_PCI_TARGBASE        CFG_PCI_MEMBASE
  65
  66 #define CFG_PCIE_MEMBASE        0xb0000000      /* mapped PCIe memory   */
  67 #define CFG_PCIE_MEMSIZE        0x01000000
  68 #define CFG_PCIE_BASE           0xe0000000      /* PCIe UTL regs */
  69
  70 #define CFG_PCIE0_CFGBASE       0xc0000000
  71 #define CFG_PCIE1_CFGBASE       0xc1000000
  72 #define CFG_PCIE2_CFGBASE       0xc2000000
  73 #define CFG_PCIE0_XCFGBASE      0xc3000000
  74 #define CFG_PCIE1_XCFGBASE      0xc3001000
  75 #define CFG_PCIE2_XCFGBASE      0xc3002000
  76
  77 /* System RAM mapped to PCI space */
  78 #define CONFIG_PCI_SYS_MEM_BUS  CFG_SDRAM_BASE
  79 #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
  80 #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
  81
  82 #define CFG_FPGA_BASE           0xe2000000      /* epld                 */
  83 #define CFG_OPER_FLASH          0xe7000000      /* SRAM - OPER Flash    */
  84
  85 /* #define CFG_NVRAM_BASE_ADDR 0x08000000 */
  86 /*-----------------------------------------------------------------------
  87  * Initial RAM & stack pointer (placed in internal SRAM)
  88  *----------------------------------------------------------------------*/
  89 #define CFG_TEMP_STACK_OCM      1
  90 #define CFG_OCM_DATA_ADDR       CFG_ISRAM_BASE
  91 #define CFG_INIT_RAM_ADDR       CFG_ISRAM_BASE  /* Initial RAM address  */
  92 #define CFG_INIT_RAM_END        0x2000          /* End of used area in RAM */
  93 #define CFG_GBL_DATA_SIZE       128             /* num bytes initial data */
  94
  95 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  96 #define CFG_POST_WORD_ADDR      (CFG_GBL_DATA_OFFSET - 0x4)
  97 #define CFG_INIT_SP_OFFSET      CFG_POST_WORD_ADDR
  98
  99 #define CFG_MONITOR_LEN         (320 * 1024)    /* Reserve 320 kB for Mon */
 100 #define CFG_MALLOC_LEN          (512 * 1024)    /* Reserve 512 kB for malloc */
 101
 102 /*-----------------------------------------------------------------------
 103  * Serial Port
 104  *----------------------------------------------------------------------*/
 105 #define CONFIG_SERIAL_MULTI     1
 106 #undef CONFIG_UART1_CONSOLE
 107
 108 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 109 #undef CFG_EXT_SERIAL_CLOCK
 110 /* #define CFG_EXT_SERIAL_CLOCK (1843200 * 6) */ /* Ext clk @ 11.059 MHz */
 111
 112 #define CONFIG_BAUDRATE         115200
 113
 114 #define CFG_BAUDRATE_TABLE  \
 115         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 116
 117 /*-----------------------------------------------------------------------
 118  * DDR SDRAM
 119  *----------------------------------------------------------------------*/
 120 #define CONFIG_SPD_EEPROM       1       /* Use SPD EEPROM for setup     */
 121 #define SPD_EEPROM_ADDRESS      {0x53, 0x52}    /* SPD i2c spd addresses*/
 122 #define CONFIG_DDR_ECC          1       /* with ECC support             */
 123
 124 /*-----------------------------------------------------------------------
 125  * I2C
 126  *----------------------------------------------------------------------*/
 127 #define CONFIG_HARD_I2C         1       /* I2C with hardware support    */
 128 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 129 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 130 #define CFG_I2C_SLAVE           0x7F
 131
 132 #define IIC0_BOOTPROM_ADDR      0x50
 133 #define IIC0_ALT_BOOTPROM_ADDR  0x54
 134
 135 /* Don't probe these addrs */
 136 #define CFG_I2C_NOPROBES        {0x50, 0x52, 0x53, 0x54}
 137
 138 /* #if defined(CONFIG_CMD_EEPROM) */
 139 /* #define CFG_I2C_EEPROM_ADDR  0x50 */ /* I2C boot EEPROM              */
 140 #define CFG_I2C_EEPROM_ADDR_LEN 2       /* Bytes of address             */
 141 /* #endif */
 142
 143 /*-----------------------------------------------------------------------
 144  * Environment
 145  *----------------------------------------------------------------------*/
 146 /* #define CFG_NVRAM_SIZE       (0x2000 - 8) */ /* NVRAM size(8k)- RTC regs */
 147
 148 #undef  CFG_ENV_IS_IN_NVRAM             /* ... not in NVRAM             */
 149 #define CFG_ENV_IS_IN_FLASH     1       /* Environment uses flash       */
 150 #undef  CFG_ENV_IS_IN_EEPROM            /* ... not in EEPROM            */
 151 #define CONFIG_ENV_OVERWRITE    1
 152
 153 #define CONFIG_PREBOOT  "echo;" \
 154         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
 155         "echo"
 156
 157 #undef  CONFIG_BOOTARGS
 158
 159 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 160         "netdev=eth0\0"                                                 \
 161         "hostname=yucca\0"                                              \
 162         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 163                 "nfsroot=${serverip}:${rootpath}\0"                     \
 164         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 165         "addip=setenv bootargs ${bootargs} "                            \
 166                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 167                 ":${hostname}:${netdev}:off panic=1\0"                  \
 168         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 169         "flash_nfs=run nfsargs addip addtty;"                           \
 170                 "bootm ${kernel_addr}\0"                                \
 171         "flash_self=run ramargs addip addtty;"                          \
 172                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 173         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 174                 "bootm\0"                                               \
 175         "rootpath=/opt/eldk/ppc_4xx\0"                          \
 176         "bootfile=yucca/uImage\0"                                       \
 177         "kernel_addr=E7F10000\0"                                        \
 178         "ramdisk_addr=E7F20000\0"                                       \
 179         "initrd_high=30000000\0"                                        \
 180         "load=tftp 100000 yuca/u-boot.bin\0"                            \
 181         "update=protect off 2:4-7;era 2:4-7;"                           \
 182                 "cp.b ${fileaddr} FFFB0000 ${filesize};"                \
 183                 "setenv filesize;saveenv\0"                             \
 184         "upd=run load;run update\0"                                     \
 185         "pciconfighost=1\0"                                             \
 186         ""
 187 #define CONFIG_BOOTCOMMAND      "run flash_self"
 188
 189 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 190
 191 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 192 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 193
 194
 195 /*
 196  * BOOTP options
 197  */
 198 #define CONFIG_BOOTP_BOOTFILESIZE
 199 #define CONFIG_BOOTP_BOOTPATH
 200 #define CONFIG_BOOTP_GATEWAY
 201 #define CONFIG_BOOTP_HOSTNAME
 202
 203
 204 /*
 205  * Command line configuration.
 206  */
 207 #include <config_cmd_default.h>
 208
 209 #define CONFIG_CMD_ASKENV
 210 #define CONFIG_CMD_EEPROM
 211 #define CONFIG_CMD_DHCP
 212 #define CONFIG_CMD_DIAG
 213 #define CONFIG_CMD_ELF
 214 #define CONFIG_CMD_I2C
 215 #define CONFIG_CMD_IRQ
 216 #define CONFIG_CMD_MII
 217 #define CONFIG_CMD_NET
 218 #define CONFIG_CMD_NFS
 219 #define CONFIG_CMD_PCI
 220 #define CONFIG_CMD_PING
 221 #define CONFIG_CMD_REGINFO
 222 #define CONFIG_CMD_SDRAM
 223
 224
 225 #define CONFIG_IBM_EMAC4_V4     1
 226 #define CONFIG_MII              1       /* MII PHY management           */
 227 #undef CONFIG_NET_MULTI
 228 #define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
 229 #define CONFIG_HAS_ETH0
 230 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 231 #define CONFIG_PHY_RESET_DELAY  1000
 232 #define CONFIG_CIS8201_PHY      1       /* Enable 'special' RGMII mode for Cicada phy */
 233 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 234 #define CFG_RX_ETH_BUFFER       32      /* Number of ethernet rx buffers & descriptors */
 235
 236 #define CONFIG_NETCONSOLE               /* include NetConsole support   */
 237 #define CONFIG_NET_MULTI                /* needed for NetConsole        */
 238
 239 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 240
 241 /*
 242  * Miscellaneous configurable options
 243  */
 244 #define CFG_LONGHELP                            /* undef to save memory         */
 245 #define CFG_PROMPT              "=> "           /* Monitor Command Prompt       */
 246
 247 #if defined(CONFIG_CMD_KGDB)
 248 #define CFG_CBSIZE              1024            /* Console I/O Buffer Size      */
 249 #else
 250 #define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
 251 #endif
 252 #define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 253 #define CFG_MAXARGS             16              /* max number of command args   */
 254 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 255
 256 #define CFG_MEMTEST_START       0x0400000       /* memtest works on             */
 257 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM          */
 258
 259 #define CFG_LOAD_ADDR           0x100000        /* default load address         */
 260 #define CFG_EXTBDINFO           1               /* To use extended board_into (bd_t) */
 261
 262 #define CFG_HZ                  1000            /* decrementer freq: 1 ms ticks */
 263
 264 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 265 #define CONFIG_LOOPW            1       /* enable loopw command         */
 266 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 267 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 268 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 269
 270 /*-----------------------------------------------------------------------
 271  * FLASH related
 272  *----------------------------------------------------------------------*/
 273 #define CFG_MAX_FLASH_BANKS     3       /* number of banks              */
 274 #define CFG_MAX_FLASH_SECT      256     /* sectors per device           */
 275
 276 #undef  CFG_FLASH_CHECKSUM
 277 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms) */
 278 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms) */
 279
 280 #define CFG_FLASH_ADDR0         0x5555
 281 #define CFG_FLASH_ADDR1         0x2aaa
 282 #define CFG_FLASH_WORD_SIZE     unsigned char
 283
 284 #define CFG_FLASH_2ND_16BIT_DEV 1       /* evb440SPe has 8 and 16bit device */
 285 #define CFG_FLASH_2ND_ADDR      0xe7c00000 /* evb440SPe has 8 and 16bit device*/
 286
 287 #ifdef CFG_ENV_IS_IN_FLASH
 288 #define CFG_ENV_SECT_SIZE       0x10000 /* size of one complete sector  */
 289 #define CFG_ENV_ADDR            0xfffa0000
 290 /* #define CFG_ENV_ADDR         (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) */
 291 #define CFG_ENV_SIZE            0x10000 /* Size of Environment vars     */
 292 #endif /* CFG_ENV_IS_IN_FLASH */
 293 /*-----------------------------------------------------------------------
 294  * PCI stuff
 295  *-----------------------------------------------------------------------
 296  */
 297 /* General PCI */
 298 #define CONFIG_PCI                      /* include pci support          */
 299 #define CONFIG_PCI_PNP          1       /* do pci plug-and-play         */
 300 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
 301 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
 302
 303 /* Board-specific PCI */
 304 #define CFG_PCI_TARGET_INIT             /* let board init pci target    */
 305 #undef  CFG_PCI_MASTER_INIT
 306
 307 #define CFG_PCI_SUBSYS_VENDORID 0x1014  /* IBM                          */
 308 #define CFG_PCI_SUBSYS_DEVICEID 0xcafe  /* Whatever                     */
 309 /* #define CFG_PCI_SUBSYS_ID    CFG_PCI_SUBSYS_DEVICEID */
 310
 311 /*
 312  *  NETWORK Support (PCI):
 313  */
 314 /* Support for Intel 82557/82559/82559ER chips. */
 315 #define CONFIG_EEPRO100
 316
 317 /*
 318  * For booting Linux, the board info and command line data
 319  * have to be in the first 8 MB of memory, since this is
 320  * the maximum mapped by the Linux kernel during initialization.
 321  */
 322 #define CFG_BOOTMAPSZ           (8 << 20)       /*Initial Memory map for Linux*/
 323 /*-----------------------------------------------------------------------
 324  * Cache Configuration
 325  */
 326 #define CFG_DCACHE_SIZE         8192    /* For AMCC 405 CPUs            */
 327 #define CFG_CACHELINE_SIZE      32      /* ...                          */
 328 #if defined(CONFIG_CMD_KGDB)
 329 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value */
 330 #endif
 331
 332 /*
 333  * Internal Definitions
 334  *
 335  * Boot Flags
 336  */
 337 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 338 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 339
 340 #if defined(CONFIG_CMD_KGDB)
 341 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 342 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 343 #endif
 344
 345 /* FB Divisor selection */
 346 #define FPGA_FB_DIV_6           6
 347 #define FPGA_FB_DIV_10          10
 348 #define FPGA_FB_DIV_12          12
 349 #define FPGA_FB_DIV_20          20
 350
 351 /* VCO Divisor selection */
 352 #define FPGA_VCO_DIV_4          4
 353 #define FPGA_VCO_DIV_6          6
 354 #define FPGA_VCO_DIV_8          8
 355 #define FPGA_VCO_DIV_10         10
 356
 357 /*----------------------------------------------------------------------------+
 358 | FPGA registers and bit definitions
 359 +----------------------------------------------------------------------------*/
 360 /* PowerPC 440SPe Board FPGA is reached with physical address 0x1 E2000000. */
 361 /* TLB initialization makes it correspond to logical address 0xE2000000. */
 362 /* => Done init_chip.s in bootlib */
 363 #define FPGA_REG_BASE_ADDR      0xE2000000
 364 #define FPGA_GPIO_BASE_ADDR     0xE2010000
 365 #define FPGA_INT_BASE_ADDR      0xE2020000
 366
 367 /*----------------------------------------------------------------------------+
 368 | Display
 369 +----------------------------------------------------------------------------*/
 370 #define PPC440SPE_DISPLAY       FPGA_REG_BASE_ADDR
 371
 372 #define PPC440SPE_DISPLAY_D8    (FPGA_REG_BASE_ADDR+0x06)
 373 #define PPC440SPE_DISPLAY_D4    (FPGA_REG_BASE_ADDR+0x04)
 374 #define PPC440SPE_DISPLAY_D2    (FPGA_REG_BASE_ADDR+0x02)
 375 #define PPC440SPE_DISPLAY_D1    (FPGA_REG_BASE_ADDR+0x00)
 376 /*define   WRITE_DISPLAY_DIGIT(n) IOREG8(FPGA_REG_BASE_ADDR + (2*n))*/
 377 /*#define   IOREG8(addr) *((volatile unsigned char *)(addr))*/
 378
 379 /*----------------------------------------------------------------------------+
 380 | ethernet/reset/boot Register 1
 381 +----------------------------------------------------------------------------*/
 382 #define FPGA_REG10      (FPGA_REG_BASE_ADDR+0x10)
 383
 384 #define FPGA_REG10_10MHZ_ENABLE         0x8000
 385 #define FPGA_REG10_100MHZ_ENABLE        0x4000
 386 #define FPGA_REG10_GIGABIT_ENABLE       0x2000
 387 #define FPGA_REG10_FULL_DUPLEX          0x1000  /* force Full Duplex*/
 388 #define FPGA_REG10_RESET_ETH            0x0800
 389 #define FPGA_REG10_AUTO_NEG_DIS         0x0400
 390 #define FPGA_REG10_INTP_ETH             0x0200
 391
 392 #define FPGA_REG10_RESET_HISR           0x0080
 393 #define FPGA_REG10_ENABLE_DISPLAY       0x0040
 394 #define FPGA_REG10_RESET_SDRAM          0x0020
 395 #define FPGA_REG10_OPER_BOOT            0x0010
 396 #define FPGA_REG10_SRAM_BOOT            0x0008
 397 #define FPGA_REG10_SMALL_BOOT           0x0004
 398 #define FPGA_REG10_FORCE_COLA           0x0002
 399 #define FPGA_REG10_COLA_MANUAL          0x0001
 400
 401 #define FPGA_REG10_SDRAM_ENABLE         0x0020
 402
 403 #define FPGA_REG10_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*from ocotea ?*/
 404 #define FPGA_REG10_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*from ocotea ?*/
 405
 406 /*----------------------------------------------------------------------------+
 407 | MUX control
 408 +----------------------------------------------------------------------------*/
 409 #define FPGA_REG12      (FPGA_REG_BASE_ADDR+0x12)
 410
 411 #define FPGA_REG12_EBC_CTL              0x8000
 412 #define FPGA_REG12_UART1_CTS_RTS        0x4000
 413 #define FPGA_REG12_UART0_RX_ENABLE      0x2000
 414 #define FPGA_REG12_UART1_RX_ENABLE      0x1000
 415 #define FPGA_REG12_UART2_RX_ENABLE      0x0800
 416 #define FPGA_REG12_EBC_OUT_ENABLE       0x0400
 417 #define FPGA_REG12_GPIO0_OUT_ENABLE     0x0200
 418 #define FPGA_REG12_GPIO1_OUT_ENABLE     0x0100
 419 #define FPGA_REG12_GPIO_SELECT          0x0010
 420 #define FPGA_REG12_GPIO_CHREG           0x0008
 421 #define FPGA_REG12_GPIO_CLK_CHREG       0x0004
 422 #define FPGA_REG12_GPIO_OETRI           0x0002
 423 #define FPGA_REG12_EBC_ERROR            0x0001
 424
 425 /*----------------------------------------------------------------------------+
 426 | PCI Clock control
 427 +----------------------------------------------------------------------------*/
 428 #define FPGA_REG16      (FPGA_REG_BASE_ADDR+0x16)
 429
 430 #define FPGA_REG16_PCI_CLK_CTL0         0x8000
 431 #define FPGA_REG16_PCI_CLK_CTL1         0x4000
 432 #define FPGA_REG16_PCI_CLK_CTL2         0x2000
 433 #define FPGA_REG16_PCI_CLK_CTL3         0x1000
 434 #define FPGA_REG16_PCI_CLK_CTL4         0x0800
 435 #define FPGA_REG16_PCI_CLK_CTL5         0x0400
 436 #define FPGA_REG16_PCI_CLK_CTL6         0x0200
 437 #define FPGA_REG16_PCI_CLK_CTL7         0x0100
 438 #define FPGA_REG16_PCI_CLK_CTL8         0x0080
 439 #define FPGA_REG16_PCI_CLK_CTL9         0x0040
 440 #define FPGA_REG16_PCI_EXT_ARB0         0x0020
 441 #define FPGA_REG16_PCI_MODE_1           0x0010
 442 #define FPGA_REG16_PCI_TARGET_MODE      0x0008
 443 #define FPGA_REG16_PCI_INTP_MODE        0x0004
 444
 445 /* FB1 Divisor selection */
 446 #define FPGA_REG16_FB2_DIV_MASK         0x1000
 447 #define FPGA_REG16_FB2_DIV_LOW          0x0000
 448 #define FPGA_REG16_FB2_DIV_HIGH         0x1000
 449 /* FB2 Divisor selection */
 450 /* S3 switch on Board */
 451 #define FPGA_REG16_FB1_DIV_MASK         0x2000
 452 #define FPGA_REG16_FB1_DIV_LOW          0x0000
 453 #define FPGA_REG16_FB1_DIV_HIGH         0x2000
 454 /* PCI0 Clock Selection */
 455 /* S3 switch on Board */
 456 #define FPGA_REG16_PCI0_CLK_MASK        0x0c00
 457 #define FPGA_REG16_PCI0_CLK_33_33       0x0000
 458 #define FPGA_REG16_PCI0_CLK_66_66       0x0800
 459 #define FPGA_REG16_PCI0_CLK_100         0x0400
 460 #define FPGA_REG16_PCI0_CLK_133_33      0x0c00
 461 /* VCO Divisor selection */
 462 /* S3 switch on Board */
 463 #define FPGA_REG16_VCO_DIV_MASK         0xc000
 464 #define FPGA_REG16_VCO_DIV_4            0x0000
 465 #define FPGA_REG16_VCO_DIV_8            0x4000
 466 #define FPGA_REG16_VCO_DIV_6            0x8000
 467 #define FPGA_REG16_VCO_DIV_10           0xc000
 468 /* Master Clock Selection */
 469 /* S3, S4 switches on Board */
 470 #define FPGA_REG16_MASTER_CLK_MASK      0x01c0
 471 #define FPGA_REG16_MASTER_CLK_EXT       0x0000
 472 #define FPGA_REG16_MASTER_CLK_66_66     0x0040
 473 #define FPGA_REG16_MASTER_CLK_50        0x0080
 474 #define FPGA_REG16_MASTER_CLK_33_33     0x00c0
 475 #define FPGA_REG16_MASTER_CLK_25        0x0100
 476
 477 /*----------------------------------------------------------------------------+
 478 | PCI Miscellaneous
 479 +----------------------------------------------------------------------------*/
 480 #define FPGA_REG18      (FPGA_REG_BASE_ADDR+0x18)
 481
 482 #define FPGA_REG18_PCI_PRSNT1           0x8000
 483 #define FPGA_REG18_PCI_PRSNT2           0x4000
 484 #define FPGA_REG18_PCI_INTA             0x2000
 485 #define FPGA_REG18_PCI_SLOT0_INTP       0x1000
 486 #define FPGA_REG18_PCI_SLOT1_INTP       0x0800
 487 #define FPGA_REG18_PCI_SLOT2_INTP       0x0400
 488 #define FPGA_REG18_PCI_SLOT3_INTP       0x0200
 489 #define FPGA_REG18_PCI_PCI0_VC          0x0100
 490 #define FPGA_REG18_PCI_PCI0_VTH1        0x0080
 491 #define FPGA_REG18_PCI_PCI0_VTH2        0x0040
 492 #define FPGA_REG18_PCI_PCI0_VTH3        0x0020
 493
 494 /*----------------------------------------------------------------------------+
 495 | PCIe Miscellaneous
 496 +----------------------------------------------------------------------------*/
 497 #define FPGA_REG1A      (FPGA_REG_BASE_ADDR+0x1A)
 498
 499 #define FPGA_REG1A_PE0_GLED             0x8000
 500 #define FPGA_REG1A_PE1_GLED             0x4000
 501 #define FPGA_REG1A_PE2_GLED             0x2000
 502 #define FPGA_REG1A_PE0_YLED             0x1000
 503 #define FPGA_REG1A_PE1_YLED             0x0800
 504 #define FPGA_REG1A_PE2_YLED             0x0400
 505 #define FPGA_REG1A_PE0_PWRON            0x0200
 506 #define FPGA_REG1A_PE1_PWRON            0x0100
 507 #define FPGA_REG1A_PE2_PWRON            0x0080
 508 #define FPGA_REG1A_PE0_REFCLK_ENABLE    0x0040
 509 #define FPGA_REG1A_PE1_REFCLK_ENABLE    0x0020
 510 #define FPGA_REG1A_PE2_REFCLK_ENABLE    0x0010
 511 #define FPGA_REG1A_PE_SPREAD0           0x0008
 512 #define FPGA_REG1A_PE_SPREAD1           0x0004
 513 #define FPGA_REG1A_PE_SELSOURCE_0       0x0002
 514 #define FPGA_REG1A_PE_SELSOURCE_1       0x0001
 515
 516 /*----------------------------------------------------------------------------+
 517 | PCIe Miscellaneous
 518 +----------------------------------------------------------------------------*/
 519 #define FPGA_REG1C      (FPGA_REG_BASE_ADDR+0x1C)
 520
 521 #define FPGA_REG1C_PE0_ROOTPOINT        0x8000
 522 #define FPGA_REG1C_PE1_ENDPOINT         0x4000
 523 #define FPGA_REG1C_PE2_ENDPOINT         0x2000
 524 #define FPGA_REG1C_PE0_PRSNT            0x1000
 525 #define FPGA_REG1C_PE1_PRSNT            0x0800
 526 #define FPGA_REG1C_PE2_PRSNT            0x0400
 527 #define FPGA_REG1C_PE0_WAKE             0x0080
 528 #define FPGA_REG1C_PE1_WAKE             0x0040
 529 #define FPGA_REG1C_PE2_WAKE             0x0020
 530 #define FPGA_REG1C_PE0_PERST            0x0010
 531 #define FPGA_REG1C_PE1_PERST            0x0008
 532 #define FPGA_REG1C_PE2_PERST            0x0004
 533
 534 /*----------------------------------------------------------------------------+
 535 | Defines
 536 +----------------------------------------------------------------------------*/
 537 #define PERIOD_133_33MHZ        7500    /* 7,5ns */
 538 #define PERIOD_100_00MHZ        10000   /* 10ns */
 539 #define PERIOD_83_33MHZ         12000   /* 12ns */
 540 #define PERIOD_75_00MHZ         13333   /* 13,333ns */
 541 #define PERIOD_66_66MHZ         15000   /* 15ns */
 542 #define PERIOD_50_00MHZ         20000   /* 20ns */
 543 #define PERIOD_33_33MHZ         30000   /* 30ns */
 544 #define PERIOD_25_00MHZ         40000   /* 40ns */
 545
 546 /*---------------------------------------------------------------------------*/
 547
 548 #endif  /* __CONFIG_H */