include/configs/zeus.h

   1 /*
   2  * (C) Copyright 2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /************************************************************************
   9  * zeus.h - configuration for Zeus board
  10  ***********************************************************************/
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*-----------------------------------------------------------------------
  15  * High Level Configuration Options
  16  *----------------------------------------------------------------------*/
  17 #define CONFIG_ZEUS             1               /* Board is Zeus        */
  18 #define CONFIG_405EP            1               /* Specifc 405EP support*/
  19
  20 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  21
  22 #define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
  23
  24 #define CONFIG_BOARD_EARLY_INIT_F 1             /* Call board_early_init_f */
  25 #define CONFIG_MISC_INIT_R      1               /* Call misc_init_r     */
  26
  27 #define PLLMR0_DEFAULT          PLLMR0_333_111_55_111
  28 #define PLLMR1_DEFAULT          PLLMR1_333_111_55_111
  29
  30 #define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
  31
  32 #define CONFIG_OVERWRITE_ETHADDR_ONCE   1
  33
  34 #define CONFIG_PPC4xx_EMAC
  35 #define CONFIG_MII              1       /* MII PHY management           */
  36 #define CONFIG_PHY_ADDR         0x01    /* PHY address                  */
  37 #define CONFIG_HAS_ETH1         1
  38 #define CONFIG_PHY1_ADDR        0x11    /* EMAC1 PHY address            */
  39 #define CONFIG_SYS_RX_ETH_BUFFER        16      /* Number of ethernet rx buffers & descriptors */
  40 #define CONFIG_PHY_RESET        1
  41 #define CONFIG_PHY_RESET_DELAY  300     /* PHY RESET recovery delay     */
  42
  43 /*
  44  * BOOTP options
  45  */
  46 #define CONFIG_BOOTP_BOOTFILESIZE
  47 #define CONFIG_BOOTP_BOOTPATH
  48 #define CONFIG_BOOTP_GATEWAY
  49 #define CONFIG_BOOTP_HOSTNAME
  50
  51 /*
  52  * Command line configuration.
  53  */
  54 #include <config_cmd_default.h>
  55
  56 #define CONFIG_CMD_ASKENV
  57 #define CONFIG_CMD_CACHE
  58 #define CONFIG_CMD_DHCP
  59 #define CONFIG_CMD_DIAG
  60 #define CONFIG_CMD_EEPROM
  61 #define CONFIG_CMD_ELF
  62 #define CONFIG_CMD_I2C
  63 #define CONFIG_CMD_IRQ
  64 #define CONFIG_CMD_MII
  65 #define CONFIG_CMD_NET
  66 #define CONFIG_CMD_NFS
  67 #define CONFIG_CMD_PING
  68 #define CONFIG_CMD_REGINFO
  69
  70 /* POST support */
  71 #define CONFIG_POST             (CONFIG_SYS_POST_MEMORY   | \
  72                                  CONFIG_SYS_POST_CPU       | \
  73                                  CONFIG_SYS_POST_CACHE     | \
  74                                  CONFIG_SYS_POST_UART      | \
  75                                  CONFIG_SYS_POST_ETHER)
  76
  77 #define CONFIG_SYS_POST_ETHER_EXT_LOOPBACK      /* eth POST using ext loopack connector */
  78
  79 /* Define here the base-addresses of the UARTs to test in POST */
  80 #define CONFIG_SYS_POST_UART_TABLE      { CONFIG_SYS_NS16550_COM1 }
  81
  82 #define CONFIG_LOGBUFFER
  83 #define CONFIG_SYS_POST_CACHE_ADDR      0x00800000 /* free virtual address      */
  84
  85 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
  86
  87 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
  88
  89 /*-----------------------------------------------------------------------
  90  * SDRAM
  91  *----------------------------------------------------------------------*/
  92 /*
  93  * SDRAM configuration (please see cpu/ppc/sdram.[ch])
  94  */
  95 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0 */
  96 #define CONFIG_SDRAM_BANK1      1       /* init onboard SDRAM bank 1 */
  97
  98 /* SDRAM timings used in datasheet */
  99 #define CONFIG_SYS_SDRAM_CL            3        /* CAS latency */
 100 #define CONFIG_SYS_SDRAM_tRP           20       /* PRECHARGE command period */
 101 #define CONFIG_SYS_SDRAM_tRC           66       /* ACTIVE-to-ACTIVE command period */
 102 #define CONFIG_SYS_SDRAM_tRCD          20       /* ACTIVE-to-READ delay */
 103 #define CONFIG_SYS_SDRAM_tRFC           66      /* Auto refresh period */
 104
 105 /*-----------------------------------------------------------------------
 106  * Serial Port
 107  *----------------------------------------------------------------------*/
 108 #define CONFIG_CONS_INDEX       1
 109 #define CONFIG_SYS_NS16550
 110 #define CONFIG_SYS_NS16550_SERIAL
 111 #define CONFIG_SYS_NS16550_REG_SIZE     1
 112 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 113 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK                     /* external serial clock */
 114 #define CONFIG_SYS_BASE_BAUD    691200
 115 #define CONFIG_BAUDRATE         115200
 116
 117 #define CONFIG_SYS_BAUDRATE_TABLE  \
 118     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 119
 120 /*-----------------------------------------------------------------------
 121  * Miscellaneous configurable options
 122  *----------------------------------------------------------------------*/
 123 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 124 #if defined(CONFIG_CMD_KGDB)
 125 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 126 #else
 127 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 128 #endif
 129 #define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 130 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 131 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size  */
 132
 133 #define CONFIG_SYS_MEMTEST_START        0x0400000 /* memtest works on           */
 134 #define CONFIG_SYS_MEMTEST_END          0x0C00000 /* 4 ... 12 MB in DRAM        */
 135
 136 #define CONFIG_SYS_LOAD_ADDR            0x100000  /* default load address       */
 137 #define CONFIG_SYS_EXTBDINFO            1       /* To use extended board_into (bd_t) */
 138
 139 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 140 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 141
 142 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 143 #define CONFIG_LOOPW            1       /* enable loopw command         */
 144 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 145 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 146 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 147
 148 /*-----------------------------------------------------------------------
 149  * I2C
 150  *----------------------------------------------------------------------*/
 151 #define CONFIG_SYS_I2C
 152 #define CONFIG_SYS_I2C_PPC4XX
 153 #define CONFIG_SYS_I2C_PPC4XX_CH0
 154 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 155 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 156
 157 /* these are for the ST M24C02 2kbit serial i2c eeprom */
 158 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50            /* base address */
 159 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1               /* bytes of address */
 160 /* mask of address bits that overflow into the "EEPROM chip address"    */
 161 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 162
 163 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3       /* 8 byte write page size */
 164 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 165
 166 /*
 167  * The layout of the I2C EEPROM, used for bootstrap setup and for board-
 168  * specific values, like ethaddr... that can be restored via the sw-reset
 169  * button
 170  */
 171 #define FACTORY_RESET_I2C_EEPROM        0x50
 172 #define FACTORY_RESET_ENV_OFFS          0x80
 173 #define FACTORY_RESET_ENV_SIZE          0x80
 174
 175 /*-----------------------------------------------------------------------
 176  * Start addresses for the final memory configuration
 177  * (Set up by the startup code)
 178  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 179  */
 180 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 181 #define CONFIG_SYS_FLASH_BASE           0xFF000000
 182 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Monitor   */
 183 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserve 128 kB for malloc()  */
 184 #define CONFIG_SYS_MONITOR_BASE (-CONFIG_SYS_MONITOR_LEN)
 185
 186 /*
 187  * For booting Linux, the board info and command line data
 188  * have to be in the first 8 MB of memory, since this is
 189  * the maximum mapped by the Linux kernel during initialization.
 190  */
 191 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 192
 193 /*-----------------------------------------------------------------------
 194  * FLASH organization
 195  */
 196 #define CONFIG_SYS_FLASH_CFI                            /* The flash is CFI compatible  */
 197 #define CONFIG_FLASH_CFI_DRIVER                 /* Use common CFI driver        */
 198
 199 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 200
 201 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 202 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 203
 204 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 205 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 206
 207 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 208 #define CONFIG_SYS_FLASH_PROTECTION     1       /* use hardware flash protection        */
 209
 210 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 211 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash        */
 212
 213 #ifdef CONFIG_ENV_IS_IN_FLASH
 214 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector          */
 215 #define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 216 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 217
 218 /* Address and size of Redundant Environment Sector     */
 219 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 220 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 221 #endif
 222
 223 /*-----------------------------------------------------------------------
 224  * Definitions for initial stack pointer and data area (in data cache)
 225  */
 226 /* use on chip memory (OCM) for temperary stack until sdram is tested */
 227 #define CONFIG_SYS_TEMP_STACK_OCM       1
 228
 229 /* On Chip Memory location */
 230 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 231 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 232 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM               */
 233 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM    */
 234
 235 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 236 /* reserve some memory for POST and BOOT limit info */
 237 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 16)
 238
 239 /* extra data in OCM */
 240 #define CONFIG_SYS_POST_MAGIC           \
 241                 (CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 8)
 242 #define CONFIG_SYS_POST_VAL             \
 243                 (CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 12)
 244
 245 /*-----------------------------------------------------------------------
 246  * External Bus Controller (EBC) Setup
 247  */
 248
 249 /* Memory Bank 0 (Flash 16M) initialization                                     */
 250 #define CONFIG_SYS_EBC_PB0AP            0x05815600
 251 #define CONFIG_SYS_EBC_PB0CR            0xFF09A000  /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit  */
 252
 253 /*-----------------------------------------------------------------------
 254  * Definitions for GPIO setup (PPC405EP specific)
 255  *
 256  * GPIO0[0]     - External Bus Controller BLAST output
 257  * GPIO0[1-9]   - Instruction trace outputs
 258  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 259  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
 260  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 261  * GPIO0[24-27] - UART0 control signal inputs/outputs
 262  * GPIO0[28-29] - UART1 data signal input/output
 263  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 264  */
 265 #define CONFIG_SYS_GPIO0_OSRL           0x15555550      /* Chip selects */
 266 #define CONFIG_SYS_GPIO0_OSRH           0x00000110      /* UART_DTR-pin 27 alt out */
 267 #define CONFIG_SYS_GPIO0_ISR1L          0x10000041      /* Pin 2, 12 is input */
 268 #define CONFIG_SYS_GPIO0_ISR1H          0x15505440      /* OUT: LEDs 22/23; IN: pin12,2, NVALID# */
 269 #define CONFIG_SYS_GPIO0_TSRL           0x00000000
 270 #define CONFIG_SYS_GPIO0_TSRH           0x00000000
 271 #define CONFIG_SYS_GPIO0_TCR            0xBFF68317      /* 3-state OUT: 22/23/29; 12,2 is not 3-state */
 272 #define CONFIG_SYS_GPIO0_ODR            0x00000000
 273
 274 #define CONFIG_SYS_GPIO_SW_RESET        1
 275 #define CONFIG_SYS_GPIO_ZEUS_PE 12
 276 #define CONFIG_SYS_GPIO_LED_RED 22
 277 #define CONFIG_SYS_GPIO_LED_GREEN       23
 278
 279 /* Time in milli-seconds */
 280 #define CONFIG_SYS_TIME_POST            5000
 281 #define CONFIG_SYS_TIME_FACTORY_RESET   10000
 282
 283 #if defined(CONFIG_CMD_KGDB)
 284 #define CONFIG_KGDB_BAUDRATE    230400          /* speed to run kgdb serial port */
 285 #endif
 286
 287 /*
 288  * Pass open firmware flat tree
 289  */
 290 #define CONFIG_OF_LIBFDT
 291 #define CONFIG_OF_BOARD_SETUP
 292
 293 /* ENVIRONMENT VARS */
 294
 295 #define CONFIG_PREBOOT          "echo;echo Welcome to Bulletendpoints board v1.1;echo"
 296 #define CONFIG_IPADDR           192.168.1.10
 297 #define CONFIG_SERVERIP         192.168.1.100
 298 #define CONFIG_GATEWAYIP        192.168.1.100
 299 #if 0
 300 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled        */
 301 #else
 302 #define CONFIG_BOOTDELAY        3       /* autoboot after 5 seconds */
 303 #endif
 304
 305 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 306         "logversion=2\0"                                                \
 307         "hostname=zeus\0"                                               \
 308         "netdev=eth0\0"                                                 \
 309         "ethact=ppc_4xx_eth0\0"                                         \
 310         "netmask=255.255.255.0\0"                                       \
 311         "ramdisk_size=50000\0"                                          \
 312         "nfsargs=setenv bootargs root=/dev/nfs rw"                      \
 313                 " nfsroot=${serverip}:${rootpath}\0"                    \
 314         "ramargs=setenv bootargs root=/dev/ram rw"                      \
 315                 " ramdisk_size=${ramdisk_size}\0"                       \
 316         "addip=setenv bootargs ${bootargs} "                            \
 317                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 318                 ":${hostname}:${netdev}:off panic=1\0"                  \
 319         "addtty=setenv bootargs ${bootargs} console=ttyS0,"             \
 320                 "${baudrate}\0"                                         \
 321         "net_nfs=tftp ${kernel_mem_addr} ${file_kernel};"               \
 322                 "run nfsargs addip addtty;bootm\0"                      \
 323         "net_ram=tftp ${kernel_mem_addr} ${file_kernel};"               \
 324                 "tftp ${ramdisk_mem_addr} ${file_fs};"                  \
 325                 "run ramargs addip addtty;"                             \
 326                 "bootm ${kernel_mem_addr} ${ramdisk_mem_addr}\0"        \
 327         "rootpath=/target_fs/zeus\0"                                    \
 328         "kernel_fl_addr=ff000000\0"                                     \
 329         "kernel_mem_addr=200000\0"                                      \
 330         "ramdisk_fl_addr=ff300000\0"                                    \
 331         "ramdisk_mem_addr=4000000\0"                                    \
 332         "uboot_fl_addr=fffc0000\0"                                      \
 333         "uboot_mem_addr=100000\0"                                       \
 334         "file_uboot=/zeus/u-boot.bin\0"                                 \
 335         "tftp_uboot=tftp 100000 ${file_uboot}\0"                        \
 336         "update_uboot=protect off fffc0000 ffffffff;"                   \
 337                 "era fffc0000 ffffffff;cp.b 100000 fffc0000 40000;"     \
 338                 "protect on fffc0000 ffffffff\0"                        \
 339         "upd_uboot=run tftp_uboot;run update_uboot\0"                   \
 340         "file_kernel=/zeus/uImage_ba\0"                                 \
 341         "tftp_kernel=tftp 100000 ${file_kernel}\0"                      \
 342         "update_kernel=protect off ff000000 ff17ffff;"                  \
 343                 "era ff000000 ff17ffff;cp.b 100000 ff000000 180000\0"   \
 344         "upd_kernel=run tftp_kernel;run update_kernel\0"                \
 345         "file_fs=/zeus/rootfs_ba.img\0"                                 \
 346         "tftp_fs=tftp 100000 ${file_fs}\0"                              \
 347         "update_fs=protect off ff300000 ff87ffff;era ff300000 ff87ffff;"\
 348                 "cp.b 100000 ff300000 580000\0"                         \
 349         "upd_fs=run tftp_fs;run update_fs\0"                            \
 350         "bootcmd=chkreset;run ramargs addip addtty addmisc;"            \
 351                 "bootm ${kernel_fl_addr} ${ramdisk_fl_addr}\0"          \
 352         ""
 353
 354 #endif  /* __CONFIG_H */