include/dwmmc.h

   1 /*
   2  * (C) Copyright 2012 SAMSUNG Electronics
   3  * Jaehoon Chung <jh80.chung@samsung.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __DWMMC_HW_H
   9 #define __DWMMC_HW_H
  10
  11 #include <asm/io.h>
  12 #include <mmc.h>
  13
  14 #define DWMCI_CTRL              0x000
  15 #define DWMCI_PWREN             0x004
  16 #define DWMCI_CLKDIV            0x008
  17 #define DWMCI_CLKSRC            0x00C
  18 #define DWMCI_CLKENA            0x010
  19 #define DWMCI_TMOUT             0x014
  20 #define DWMCI_CTYPE             0x018
  21 #define DWMCI_BLKSIZ            0x01C
  22 #define DWMCI_BYTCNT            0x020
  23 #define DWMCI_INTMASK           0x024
  24 #define DWMCI_CMDARG            0x028
  25 #define DWMCI_CMD               0x02C
  26 #define DWMCI_RESP0             0x030
  27 #define DWMCI_RESP1             0x034
  28 #define DWMCI_RESP2             0x038
  29 #define DWMCI_RESP3             0x03C
  30 #define DWMCI_MINTSTS           0x040
  31 #define DWMCI_RINTSTS           0x044
  32 #define DWMCI_STATUS            0x048
  33 #define DWMCI_FIFOTH            0x04C
  34 #define DWMCI_CDETECT           0x050
  35 #define DWMCI_WRTPRT            0x054
  36 #define DWMCI_GPIO              0x058
  37 #define DWMCI_TCMCNT            0x05C
  38 #define DWMCI_TBBCNT            0x060
  39 #define DWMCI_DEBNCE            0x064
  40 #define DWMCI_USRID             0x068
  41 #define DWMCI_VERID             0x06C
  42 #define DWMCI_HCON              0x070
  43 #define DWMCI_UHS_REG           0x074
  44 #define DWMCI_BMOD              0x080
  45 #define DWMCI_PLDMND            0x084
  46 #define DWMCI_DBADDR            0x088
  47 #define DWMCI_IDSTS             0x08C
  48 #define DWMCI_IDINTEN           0x090
  49 #define DWMCI_DSCADDR           0x094
  50 #define DWMCI_BUFADDR           0x098
  51 #define DWMCI_DATA              0x200
  52
  53 /* Interrupt Mask register */
  54 #define DWMCI_INTMSK_ALL        0xffffffff
  55 #define DWMCI_INTMSK_RE         (1 << 1)
  56 #define DWMCI_INTMSK_CDONE      (1 << 2)
  57 #define DWMCI_INTMSK_DTO        (1 << 3)
  58 #define DWMCI_INTMSK_TXDR       (1 << 4)
  59 #define DWMCI_INTMSK_RXDR       (1 << 5)
  60 #define DWMCI_INTMSK_DCRC       (1 << 7)
  61 #define DWMCI_INTMSK_RTO        (1 << 8)
  62 #define DWMCI_INTMSK_DRTO       (1 << 9)
  63 #define DWMCI_INTMSK_HTO        (1 << 10)
  64 #define DWMCI_INTMSK_FRUN       (1 << 11)
  65 #define DWMCI_INTMSK_HLE        (1 << 12)
  66 #define DWMCI_INTMSK_SBE        (1 << 13)
  67 #define DWMCI_INTMSK_ACD        (1 << 14)
  68 #define DWMCI_INTMSK_EBE        (1 << 15)
  69
  70 /* Raw interrupt Regsiter */
  71 #define DWMCI_DATA_ERR  (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\
  72                         DWMCI_INTMSK_FRUN | DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC)
  73 #define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO)
  74 /* CTRL register */
  75 #define DWMCI_CTRL_RESET        (1 << 0)
  76 #define DWMCI_CTRL_FIFO_RESET   (1 << 1)
  77 #define DWMCI_CTRL_DMA_RESET    (1 << 2)
  78 #define DWMCI_DMA_EN            (1 << 5)
  79 #define DWMCI_CTRL_SEND_AS_CCSD (1 << 10)
  80 #define DWMCI_IDMAC_EN          (1 << 25)
  81 #define DWMCI_RESET_ALL         (DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\
  82                                 DWMCI_CTRL_DMA_RESET)
  83
  84 /* CMD register */
  85 #define DWMCI_CMD_RESP_EXP      (1 << 6)
  86 #define DWMCI_CMD_RESP_LENGTH   (1 << 7)
  87 #define DWMCI_CMD_CHECK_CRC     (1 << 8)
  88 #define DWMCI_CMD_DATA_EXP      (1 << 9)
  89 #define DWMCI_CMD_RW            (1 << 10)
  90 #define DWMCI_CMD_SEND_STOP     (1 << 12)
  91 #define DWMCI_CMD_ABORT_STOP    (1 << 14)
  92 #define DWMCI_CMD_PRV_DAT_WAIT  (1 << 13)
  93 #define DWMCI_CMD_UPD_CLK       (1 << 21)
  94 #define DWMCI_CMD_USE_HOLD_REG  (1 << 29)
  95 #define DWMCI_CMD_START         (1 << 31)
  96
  97 /* CLKENA register */
  98 #define DWMCI_CLKEN_ENABLE      (1 << 0)
  99 #define DWMCI_CLKEN_LOW_PWR     (1 << 16)
 100
 101 /* Card-type registe */
 102 #define DWMCI_CTYPE_1BIT        0
 103 #define DWMCI_CTYPE_4BIT        (1 << 0)
 104 #define DWMCI_CTYPE_8BIT        (1 << 16)
 105
 106 /* Status Register */
 107 #define DWMCI_BUSY              (1 << 9)
 108
 109 /* FIFOTH Register */
 110 #define MSIZE(x)                ((x) << 28)
 111 #define RX_WMARK(x)             ((x) << 16)
 112 #define TX_WMARK(x)             (x)
 113 #define RX_WMARK_SHIFT          16
 114 #define RX_WMARK_MASK           (0xfff << RX_WMARK_SHIFT)
 115
 116 #define DWMCI_IDMAC_OWN         (1 << 31)
 117 #define DWMCI_IDMAC_CH          (1 << 4)
 118 #define DWMCI_IDMAC_FS          (1 << 3)
 119 #define DWMCI_IDMAC_LD          (1 << 2)
 120
 121 /*  Bus Mode Register */
 122 #define DWMCI_BMOD_IDMAC_RESET  (1 << 0)
 123 #define DWMCI_BMOD_IDMAC_FB     (1 << 1)
 124 #define DWMCI_BMOD_IDMAC_EN     (1 << 7)
 125
 126 /* UHS register */
 127 #define DWMCI_DDR_MODE  (1 << 16)
 128
 129 /* quirks */
 130 #define DWMCI_QUIRK_DISABLE_SMU         (1 << 0)
 131
 132 struct dwmci_host {
 133         char *name;
 134         void *ioaddr;
 135         unsigned int quirks;
 136         unsigned int caps;
 137         unsigned int version;
 138         unsigned int clock;
 139         unsigned int bus_hz;
 140         unsigned int div;
 141         int dev_index;
 142         int dev_id;
 143         int buswidth;
 144         u32 fifoth_val;
 145         struct mmc *mmc;
 146         void *priv;
 147
 148         void (*clksel)(struct dwmci_host *host);
 149         void (*board_init)(struct dwmci_host *host);
 150         unsigned int (*get_mmc_clk)(struct dwmci_host *host);
 151
 152         struct mmc_config cfg;
 153 };
 154
 155 struct dwmci_idmac {
 156         u32 flags;
 157         u32 cnt;
 158         u32 addr;
 159         u32 next_addr;
 160 } __aligned(ARCH_DMA_MINALIGN);
 161
 162 static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val)
 163 {
 164         writel(val, host->ioaddr + reg);
 165 }
 166
 167 static inline void dwmci_writew(struct dwmci_host *host, int reg, u16 val)
 168 {
 169         writew(val, host->ioaddr + reg);
 170 }
 171
 172 static inline void dwmci_writeb(struct dwmci_host *host, int reg, u8 val)
 173 {
 174         writeb(val, host->ioaddr + reg);
 175 }
 176 static inline u32 dwmci_readl(struct dwmci_host *host, int reg)
 177 {
 178         return readl(host->ioaddr + reg);
 179 }
 180
 181 static inline u16 dwmci_readw(struct dwmci_host *host, int reg)
 182 {
 183         return readw(host->ioaddr + reg);
 184 }
 185
 186 static inline u8 dwmci_readb(struct dwmci_host *host, int reg)
 187 {
 188         return readb(host->ioaddr + reg);
 189 }
 190
 191 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
 192 #endif  /* __DWMMC_HW_H */