include/dwmmc.h

   1 /*
   2  * (C) Copyright 2012 SAMSUNG Electronics
   3  * Jaehoon Chung <jh80.chung@samsung.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __DWMMC_HW_H
   9 #define __DWMMC_HW_H
  10
  11 #include <asm/io.h>
  12 #include <mmc.h>
  13
  14 #define DWMCI_CTRL              0x000
  15 #define DWMCI_PWREN             0x004
  16 #define DWMCI_CLKDIV            0x008
  17 #define DWMCI_CLKSRC            0x00C
  18 #define DWMCI_CLKENA            0x010
  19 #define DWMCI_TMOUT             0x014
  20 #define DWMCI_CTYPE             0x018
  21 #define DWMCI_BLKSIZ            0x01C
  22 #define DWMCI_BYTCNT            0x020
  23 #define DWMCI_INTMASK           0x024
  24 #define DWMCI_CMDARG            0x028
  25 #define DWMCI_CMD               0x02C
  26 #define DWMCI_RESP0             0x030
  27 #define DWMCI_RESP1             0x034
  28 #define DWMCI_RESP2             0x038
  29 #define DWMCI_RESP3             0x03C
  30 #define DWMCI_MINTSTS           0x040
  31 #define DWMCI_RINTSTS           0x044
  32 #define DWMCI_STATUS            0x048
  33 #define DWMCI_FIFOTH            0x04C
  34 #define DWMCI_CDETECT           0x050
  35 #define DWMCI_WRTPRT            0x054
  36 #define DWMCI_GPIO              0x058
  37 #define DWMCI_TCMCNT            0x05C
  38 #define DWMCI_TBBCNT            0x060
  39 #define DWMCI_DEBNCE            0x064
  40 #define DWMCI_USRID             0x068
  41 #define DWMCI_VERID             0x06C
  42 #define DWMCI_HCON              0x070
  43 #define DWMCI_UHS_REG           0x074
  44 #define DWMCI_BMOD              0x080
  45 #define DWMCI_PLDMND            0x084
  46 #define DWMCI_DBADDR            0x088
  47 #define DWMCI_IDSTS             0x08C
  48 #define DWMCI_IDINTEN           0x090
  49 #define DWMCI_DSCADDR           0x094
  50 #define DWMCI_BUFADDR           0x098
  51 #define DWMCI_DATA              0x200
  52
  53 /* Interrupt Mask register */
  54 #define DWMCI_INTMSK_ALL        0xffffffff
  55 #define DWMCI_INTMSK_RE         (1 << 1)
  56 #define DWMCI_INTMSK_CDONE      (1 << 2)
  57 #define DWMCI_INTMSK_DTO        (1 << 3)
  58 #define DWMCI_INTMSK_TXDR       (1 << 4)
  59 #define DWMCI_INTMSK_RXDR       (1 << 5)
  60 #define DWMCI_INTMSK_DCRC       (1 << 7)
  61 #define DWMCI_INTMSK_RTO        (1 << 8)
  62 #define DWMCI_INTMSK_DRTO       (1 << 9)
  63 #define DWMCI_INTMSK_HTO        (1 << 10)
  64 #define DWMCI_INTMSK_FRUN       (1 << 11)
  65 #define DWMCI_INTMSK_HLE        (1 << 12)
  66 #define DWMCI_INTMSK_SBE        (1 << 13)
  67 #define DWMCI_INTMSK_ACD        (1 << 14)
  68 #define DWMCI_INTMSK_EBE        (1 << 15)
  69
  70 /* Raw interrupt Regsiter */
  71 #define DWMCI_DATA_ERR  (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\
  72                         DWMCI_INTMSK_FRUN | DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC)
  73 #define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO)
  74 /* CTRL register */
  75 #define DWMCI_CTRL_RESET        (1 << 0)
  76 #define DWMCI_CTRL_FIFO_RESET   (1 << 1)
  77 #define DWMCI_CTRL_DMA_RESET    (1 << 2)
  78 #define DWMCI_DMA_EN            (1 << 5)
  79 #define DWMCI_CTRL_SEND_AS_CCSD (1 << 10)
  80 #define DWMCI_IDMAC_EN          (1 << 25)
  81 #define DWMCI_RESET_ALL         (DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\
  82                                 DWMCI_CTRL_DMA_RESET)
  83
  84 /* CMD register */
  85 #define DWMCI_CMD_RESP_EXP      (1 << 6)
  86 #define DWMCI_CMD_RESP_LENGTH   (1 << 7)
  87 #define DWMCI_CMD_CHECK_CRC     (1 << 8)
  88 #define DWMCI_CMD_DATA_EXP      (1 << 9)
  89 #define DWMCI_CMD_RW            (1 << 10)
  90 #define DWMCI_CMD_SEND_STOP     (1 << 12)
  91 #define DWMCI_CMD_ABORT_STOP    (1 << 14)
  92 #define DWMCI_CMD_PRV_DAT_WAIT  (1 << 13)
  93 #define DWMCI_CMD_UPD_CLK       (1 << 21)
  94 #define DWMCI_CMD_USE_HOLD_REG  (1 << 29)
  95 #define DWMCI_CMD_START         (1 << 31)
  96
  97 /* CLKENA register */
  98 #define DWMCI_CLKEN_ENABLE      (1 << 0)
  99 #define DWMCI_CLKEN_LOW_PWR     (1 << 16)
 100
 101 /* Card-type registe */
 102 #define DWMCI_CTYPE_1BIT        0
 103 #define DWMCI_CTYPE_4BIT        (1 << 0)
 104 #define DWMCI_CTYPE_8BIT        (1 << 16)
 105
 106 /* Status Register */
 107 #define DWMCI_BUSY              (1 << 9)
 108 #define DWMCI_FIFO_MASK         0x1fff
 109 #define DWMCI_FIFO_SHIFT        17
 110
 111 /* FIFOTH Register */
 112 #define MSIZE(x)                ((x) << 28)
 113 #define RX_WMARK(x)             ((x) << 16)
 114 #define TX_WMARK(x)             (x)
 115 #define RX_WMARK_SHIFT          16
 116 #define RX_WMARK_MASK           (0xfff << RX_WMARK_SHIFT)
 117
 118 #define DWMCI_IDMAC_OWN         (1 << 31)
 119 #define DWMCI_IDMAC_CH          (1 << 4)
 120 #define DWMCI_IDMAC_FS          (1 << 3)
 121 #define DWMCI_IDMAC_LD          (1 << 2)
 122
 123 /*  Bus Mode Register */
 124 #define DWMCI_BMOD_IDMAC_RESET  (1 << 0)
 125 #define DWMCI_BMOD_IDMAC_FB     (1 << 1)
 126 #define DWMCI_BMOD_IDMAC_EN     (1 << 7)
 127
 128 /* UHS register */
 129 #define DWMCI_DDR_MODE  (1 << 16)
 130
 131 /* quirks */
 132 #define DWMCI_QUIRK_DISABLE_SMU         (1 << 0)
 133
 134 /**
 135  * struct dwmci_host - Information about a designware MMC host
 136  *
 137  * @name:       Device name
 138  * @ioaddr:     Base I/O address of controller
 139  * @quirks:     Quick flags - see DWMCI_QUIRK_...
 140  * @caps:       Capabilities - see MMC_MODE_...
 141  * @bus_hz:     Bus speed in Hz, if @get_mmc_clk() is NULL
 142  * @div:        Arbitrary clock divider value for use by controller
 143  * @dev_index:  Arbitrary device index for use by controller
 144  * @dev_id:     Arbitrary device ID for use by controller
 145  * @buswidth:   Bus width in bits (8 or 4)
 146  * @fifoth_val: Value for FIFOTH register (or 0 to leave unset)
 147  * @mmc:        Pointer to generic MMC structure for this device
 148  * @priv:       Private pointer for use by controller
 149  */
 150 struct dwmci_host {
 151         const char *name;
 152         void *ioaddr;
 153         unsigned int quirks;
 154         unsigned int caps;
 155         unsigned int version;
 156         unsigned int clock;
 157         unsigned int bus_hz;
 158         unsigned int div;
 159         int dev_index;
 160         int dev_id;
 161         int buswidth;
 162         u32 fifoth_val;
 163         struct mmc *mmc;
 164         void *priv;
 165
 166         void (*clksel)(struct dwmci_host *host);
 167         void (*board_init)(struct dwmci_host *host);
 168
 169         /**
 170          * Get / set a particular MMC clock frequency
 171          *
 172          * This is used to request the current clock frequency of the clock
 173          * that drives the DWMMC peripheral. The caller will then use this
 174          * information to work out the divider it needs to achieve the
 175          * required MMC bus clock frequency. If you want to handle the
 176          * clock external to DWMMC, use @freq to select the frequency and
 177          * return that value too. Then DWMMC will put itself in bypass mode.
 178          *
 179          * @host:       DWMMC host
 180          * @freq:       Frequency the host is trying to achieve
 181          */
 182         unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq);
 183 #ifndef CONFIG_BLK
 184         struct mmc_config cfg;
 185 #endif
 186
 187         /* use fifo mode to read and write data */
 188         bool fifo_mode;
 189 };
 190
 191 struct dwmci_idmac {
 192         u32 flags;
 193         u32 cnt;
 194         u32 addr;
 195         u32 next_addr;
 196 } __aligned(ARCH_DMA_MINALIGN);
 197
 198 static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val)
 199 {
 200         writel(val, host->ioaddr + reg);
 201 }
 202
 203 static inline void dwmci_writew(struct dwmci_host *host, int reg, u16 val)
 204 {
 205         writew(val, host->ioaddr + reg);
 206 }
 207
 208 static inline void dwmci_writeb(struct dwmci_host *host, int reg, u8 val)
 209 {
 210         writeb(val, host->ioaddr + reg);
 211 }
 212 static inline u32 dwmci_readl(struct dwmci_host *host, int reg)
 213 {
 214         return readl(host->ioaddr + reg);
 215 }
 216
 217 static inline u16 dwmci_readw(struct dwmci_host *host, int reg)
 218 {
 219         return readw(host->ioaddr + reg);
 220 }
 221
 222 static inline u8 dwmci_readb(struct dwmci_host *host, int reg)
 223 {
 224         return readb(host->ioaddr + reg);
 225 }
 226
 227 #ifdef CONFIG_BLK
 228 /**
 229  * dwmci_setup_cfg() - Set up the configuration for DWMMC
 230  *
 231  * This is used to set up a DWMMC device when you are using CONFIG_BLK.
 232  *
 233  * This should be called from your MMC driver's probe() method once you have
 234  * the information required.
 235  *
 236  * Generally your driver will have a platform data structure which holds both
 237  * the configuration (struct mmc_config) and the MMC device info (struct mmc).
 238  * For example:
 239  *
 240  * struct rockchip_mmc_plat {
 241  *      struct mmc_config cfg;
 242  *      struct mmc mmc;
 243  * };
 244  *
 245  * ...
 246  *
 247  * Inside U_BOOT_DRIVER():
 248  *      .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat),
 249  *
 250  * To access platform data:
 251  *      struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
 252  *
 253  * See rockchip_dw_mmc.c for an example.
 254  *
 255  * @cfg:        Configuration structure to fill in (generally &plat->mmc)
 256  * @host:       DWMMC host
 257  * @max_clk:    Maximum supported clock speed in HZ (e.g. 150000000)
 258  * @min_clk:    Minimum supported clock speed in HZ (e.g. 400000)
 259  */
 260 void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,
 261                 u32 max_clk, u32 min_clk);
 262
 263 /**
 264  * dwmci_bind() - Set up a new MMC block device
 265  *
 266  * This is used to set up a DWMMC block device when you are using CONFIG_BLK.
 267  * It should be called from your driver's bind() method.
 268  *
 269  * See rockchip_dw_mmc.c for an example.
 270  *
 271  * @dev:        Device to set up
 272  * @mmc:        Pointer to mmc structure (normally &plat->mmc)
 273  * @cfg:        Empty configuration structure (generally &plat->cfg). This is
 274  *              normally all zeroes at this point. The only purpose of passing
 275  *              this in is to set mmc->cfg to it.
 276  * @return 0 if OK, -ve if the block device could not be created
 277  */
 278 int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
 279
 280 #else
 281 /**
 282  * add_dwmci() - Add a new DWMMC interface
 283  *
 284  * This is used when you are not using CONFIG_BLK. Convert your driver over!
 285  *
 286  * @host:       DWMMC host structure
 287  * @max_clk:    Maximum supported clock speed in HZ (e.g. 150000000)
 288  * @min_clk:    Minimum supported clock speed in HZ (e.g. 400000)
 289  * @return 0 if OK, -ve on error
 290  */
 291 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
 292 #endif /* !CONFIG_BLK */
 293
 294 #ifdef CONFIG_DM_MMC
 295 /* Export the operations to drivers */
 296 int dwmci_probe(struct udevice *dev);
 297 extern const struct dm_mmc_ops dm_dwmci_ops;
 298 #endif
 299
 300 #endif  /* __DWMMC_HW_H */