include/fsl_ddr_dimm_params.h

   1 /*
   2  * Copyright 2008-2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0
   5  */
   6
   7 #ifndef DDR2_DIMM_PARAMS_H
   8 #define DDR2_DIMM_PARAMS_H
   9
  10 #define EDC_DATA_PARITY 1
  11 #define EDC_ECC         2
  12 #define EDC_AC_PARITY   4
  13
  14 /* Parameters for a DDR dimm computed from the SPD */
  15 typedef struct dimm_params_s {
  16
  17         /* DIMM organization parameters */
  18         char mpart[19];         /* guaranteed null terminated */
  19
  20         unsigned int n_ranks;
  21         unsigned long long rank_density;
  22         unsigned long long capacity;
  23         unsigned int data_width;
  24         unsigned int primary_sdram_width;
  25         unsigned int ec_sdram_width;
  26         unsigned int registered_dimm;
  27         unsigned int device_width;      /* x4, x8, x16 components */
  28
  29         /* SDRAM device parameters */
  30         unsigned int n_row_addr;
  31         unsigned int n_col_addr;
  32         unsigned int edc_config;        /* 0 = none, 1 = parity, 2 = ECC */
  33 #ifdef CONFIG_SYS_FSL_DDR4
  34         unsigned int bank_addr_bits;
  35         unsigned int bank_group_bits;
  36 #else
  37         unsigned int n_banks_per_sdram_device;
  38 #endif
  39         unsigned int burst_lengths_bitmask;     /* BL=4 bit 2, BL=8 = bit 3 */
  40         unsigned int row_density;
  41
  42         /* used in computing base address of DIMMs */
  43         unsigned long long base_address;
  44         /* mirrored DIMMs */
  45         unsigned int mirrored_dimm;     /* only for ddr3 */
  46
  47         /* DIMM timing parameters */
  48
  49         int mtb_ps;     /* medium timebase ps */
  50         int ftb_10th_ps; /* fine timebase, in 1/10 ps */
  51         int taa_ps;     /* minimum CAS latency time */
  52         int tfaw_ps;    /* four active window delay */
  53
  54         /*
  55          * SDRAM clock periods
  56          * The range for these are 1000-10000 so a short should be sufficient
  57          */
  58         int tckmin_x_ps;
  59         int tckmin_x_minus_1_ps;
  60         int tckmin_x_minus_2_ps;
  61         int tckmax_ps;
  62
  63         /* SPD-defined CAS latencies */
  64         unsigned int caslat_x;
  65         unsigned int caslat_x_minus_1;
  66         unsigned int caslat_x_minus_2;
  67
  68         unsigned int caslat_lowest_derated;     /* Derated CAS latency */
  69
  70         /* basic timing parameters */
  71         int trcd_ps;
  72         int trp_ps;
  73         int tras_ps;
  74
  75 #ifdef CONFIG_SYS_FSL_DDR4
  76         int trfc1_ps;
  77         int trfc2_ps;
  78         int trfc4_ps;
  79         int trrds_ps;
  80         int trrdl_ps;
  81         int tccdl_ps;
  82 #else
  83         int twr_ps;     /* maximum = 63750 ps */
  84         int trfc_ps;    /* max = 255 ns + 256 ns + .75 ns
  85                                        = 511750 ps */
  86         int trrd_ps;    /* maximum = 63750 ps */
  87         int twtr_ps;    /* maximum = 63750 ps */
  88         int trtp_ps;    /* byte 38, spd->trtp */
  89 #endif
  90
  91         int trc_ps;     /* maximum = 254 ns + .75 ns = 254750 ps */
  92
  93         int refresh_rate_ps;
  94         int extended_op_srt;
  95
  96 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
  97         int tis_ps;     /* byte 32, spd->ca_setup */
  98         int tih_ps;     /* byte 33, spd->ca_hold */
  99         int tds_ps;     /* byte 34, spd->data_setup */
 100         int tdh_ps;     /* byte 35, spd->data_hold */
 101         int tdqsq_max_ps;       /* byte 44, spd->tdqsq */
 102         int tqhs_ps;    /* byte 45, spd->tqhs */
 103 #endif
 104
 105         /* DDR3 RDIMM */
 106         unsigned char rcw[16];  /* Register Control Word 0-15 */
 107 #ifdef CONFIG_SYS_FSL_DDR4
 108         unsigned int dq_mapping[18];
 109         unsigned int dq_mapping_ors;
 110 #endif
 111 } dimm_params_t;
 112
 113 unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
 114                                          const generic_spd_eeprom_t *spd,
 115                                          dimm_params_t *pdimm,
 116                                          unsigned int dimm_number);
 117
 118 #endif