include/fsl_ddr_dimm_params.h

   1 /*
   2  * Copyright 2008-2016 Freescale Semiconductor, Inc.
   3  * Copyright 2017-2018 NXP Semiconductor
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0
   6  */
   7
   8 #ifndef DDR2_DIMM_PARAMS_H
   9 #define DDR2_DIMM_PARAMS_H
  10
  11 #define EDC_DATA_PARITY 1
  12 #define EDC_ECC         2
  13 #define EDC_AC_PARITY   4
  14
  15 /* Parameters for a DDR dimm computed from the SPD */
  16 typedef struct dimm_params_s {
  17
  18         /* DIMM organization parameters */
  19         char mpart[19];         /* guaranteed null terminated */
  20
  21         unsigned int n_ranks;
  22         unsigned int die_density;
  23         unsigned long long rank_density;
  24         unsigned long long capacity;
  25         unsigned int data_width;
  26         unsigned int primary_sdram_width;
  27         unsigned int ec_sdram_width;
  28         unsigned int registered_dimm;
  29         unsigned int package_3ds;       /* number of dies in 3DS DIMM */
  30         unsigned int device_width;      /* x4, x8, x16 components */
  31
  32         /* SDRAM device parameters */
  33         unsigned int n_row_addr;
  34         unsigned int n_col_addr;
  35         unsigned int edc_config;        /* 0 = none, 1 = parity, 2 = ECC */
  36 #ifdef CONFIG_SYS_FSL_DDR4
  37         unsigned int bank_addr_bits;
  38         unsigned int bank_group_bits;
  39 #else
  40         unsigned int n_banks_per_sdram_device;
  41 #endif
  42         unsigned int burst_lengths_bitmask;     /* BL=4 bit 2, BL=8 = bit 3 */
  43
  44         /* used in computing base address of DIMMs */
  45         unsigned long long base_address;
  46         /* mirrored DIMMs */
  47         unsigned int mirrored_dimm;     /* only for ddr3 */
  48
  49         /* DIMM timing parameters */
  50
  51         int mtb_ps;     /* medium timebase ps */
  52         int ftb_10th_ps; /* fine timebase, in 1/10 ps */
  53         int taa_ps;     /* minimum CAS latency time */
  54         int tfaw_ps;    /* four active window delay */
  55
  56         /*
  57          * SDRAM clock periods
  58          * The range for these are 1000-10000 so a short should be sufficient
  59          */
  60         int tckmin_x_ps;
  61         int tckmin_x_minus_1_ps;
  62         int tckmin_x_minus_2_ps;
  63         int tckmax_ps;
  64
  65         /* SPD-defined CAS latencies */
  66         unsigned int caslat_x;
  67         unsigned int caslat_x_minus_1;
  68         unsigned int caslat_x_minus_2;
  69
  70         unsigned int caslat_lowest_derated;     /* Derated CAS latency */
  71
  72         /* basic timing parameters */
  73         int trcd_ps;
  74         int trp_ps;
  75         int tras_ps;
  76
  77 #ifdef CONFIG_SYS_FSL_DDR4
  78         int trfc1_ps;
  79         int trfc2_ps;
  80         int trfc4_ps;
  81         int trrds_ps;
  82         int trrdl_ps;
  83         int tccdl_ps;
  84         int trfc_slr_ps;
  85 #else
  86         int twr_ps;     /* maximum = 63750 ps */
  87         int trfc_ps;    /* max = 255 ns + 256 ns + .75 ns
  88                                        = 511750 ps */
  89         int trrd_ps;    /* maximum = 63750 ps */
  90         int twtr_ps;    /* maximum = 63750 ps */
  91         int trtp_ps;    /* byte 38, spd->trtp */
  92 #endif
  93
  94         int trc_ps;     /* maximum = 254 ns + .75 ns = 254750 ps */
  95
  96         int refresh_rate_ps;
  97         int extended_op_srt;
  98
  99 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
 100         int tis_ps;     /* byte 32, spd->ca_setup */
 101         int tih_ps;     /* byte 33, spd->ca_hold */
 102         int tds_ps;     /* byte 34, spd->data_setup */
 103         int tdh_ps;     /* byte 35, spd->data_hold */
 104         int tdqsq_max_ps;       /* byte 44, spd->tdqsq */
 105         int tqhs_ps;    /* byte 45, spd->tqhs */
 106 #endif
 107
 108         /* DDR3 & DDR4 RDIMM */
 109         unsigned char rcw[16];  /* Register Control Word 0-15 */
 110 #ifdef CONFIG_SYS_FSL_DDR4
 111         unsigned int dq_mapping[18];
 112         unsigned int dq_mapping_ors;
 113 #endif
 114 } dimm_params_t;
 115
 116 unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
 117                                          const generic_spd_eeprom_t *spd,
 118                                          dimm_params_t *pdimm,
 119                                          unsigned int dimm_number);
 120
 121 #endif