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git.ipfire.org Git - people/ms/u-boot.git/blob - include/fsl_ddr_dimm_params.h
2 * Copyright 2008-2016 Freescale Semiconductor, Inc.
3 * Copyright 2017-2018 NXP Semiconductor
5 * SPDX-License-Identifier: GPL-2.0
8 #ifndef DDR2_DIMM_PARAMS_H
9 #define DDR2_DIMM_PARAMS_H
11 #define EDC_DATA_PARITY 1
13 #define EDC_AC_PARITY 4
15 /* Parameters for a DDR dimm computed from the SPD */
16 typedef struct dimm_params_s
{
18 /* DIMM organization parameters */
19 char mpart
[19]; /* guaranteed null terminated */
22 unsigned int die_density
;
23 unsigned long long rank_density
;
24 unsigned long long capacity
;
25 unsigned int data_width
;
26 unsigned int primary_sdram_width
;
27 unsigned int ec_sdram_width
;
28 unsigned int registered_dimm
;
29 unsigned int package_3ds
; /* number of dies in 3DS DIMM */
30 unsigned int device_width
; /* x4, x8, x16 components */
32 /* SDRAM device parameters */
33 unsigned int n_row_addr
;
34 unsigned int n_col_addr
;
35 unsigned int edc_config
; /* 0 = none, 1 = parity, 2 = ECC */
36 #ifdef CONFIG_SYS_FSL_DDR4
37 unsigned int bank_addr_bits
;
38 unsigned int bank_group_bits
;
40 unsigned int n_banks_per_sdram_device
;
42 unsigned int burst_lengths_bitmask
; /* BL=4 bit 2, BL=8 = bit 3 */
44 /* used in computing base address of DIMMs */
45 unsigned long long base_address
;
47 unsigned int mirrored_dimm
; /* only for ddr3 */
49 /* DIMM timing parameters */
51 int mtb_ps
; /* medium timebase ps */
52 int ftb_10th_ps
; /* fine timebase, in 1/10 ps */
53 int taa_ps
; /* minimum CAS latency time */
54 int tfaw_ps
; /* four active window delay */
58 * The range for these are 1000-10000 so a short should be sufficient
61 int tckmin_x_minus_1_ps
;
62 int tckmin_x_minus_2_ps
;
65 /* SPD-defined CAS latencies */
66 unsigned int caslat_x
;
67 unsigned int caslat_x_minus_1
;
68 unsigned int caslat_x_minus_2
;
70 unsigned int caslat_lowest_derated
; /* Derated CAS latency */
72 /* basic timing parameters */
77 #ifdef CONFIG_SYS_FSL_DDR4
86 int twr_ps
; /* maximum = 63750 ps */
87 int trfc_ps
; /* max = 255 ns + 256 ns + .75 ns
89 int trrd_ps
; /* maximum = 63750 ps */
90 int twtr_ps
; /* maximum = 63750 ps */
91 int trtp_ps
; /* byte 38, spd->trtp */
94 int trc_ps
; /* maximum = 254 ns + .75 ns = 254750 ps */
99 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
100 int tis_ps
; /* byte 32, spd->ca_setup */
101 int tih_ps
; /* byte 33, spd->ca_hold */
102 int tds_ps
; /* byte 34, spd->data_setup */
103 int tdh_ps
; /* byte 35, spd->data_hold */
104 int tdqsq_max_ps
; /* byte 44, spd->tdqsq */
105 int tqhs_ps
; /* byte 45, spd->tqhs */
108 /* DDR3 & DDR4 RDIMM */
109 unsigned char rcw
[16]; /* Register Control Word 0-15 */
110 #ifdef CONFIG_SYS_FSL_DDR4
111 unsigned int dq_mapping
[18];
112 unsigned int dq_mapping_ors
;
116 unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num
,
117 const generic_spd_eeprom_t
*spd
,
118 dimm_params_t
*pdimm
,
119 unsigned int dimm_number
);