include/fsl_ifc.h

   1 /*
   2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   3  * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __FSL_IFC_H
   9 #define __FSL_IFC_H
  10
  11 #ifdef CONFIG_FSL_IFC
  12 #include <config.h>
  13 #include <common.h>
  14 #ifdef CONFIG_ARM
  15 #include <asm/arch/soc.h>
  16 #endif
  17
  18 #define FSL_IFC_V1_1_0  0x01010000
  19 #define FSL_IFC_V2_0_0  0x02000000
  20
  21 #ifdef CONFIG_SYS_FSL_IFC_LE
  22 #define ifc_in32(a)       in_le32(a)
  23 #define ifc_out32(a, v)   out_le32(a, v)
  24 #define ifc_in16(a)       in_le16(a)
  25 #define ifc_out16(a, v)   out_le16(a, v)
  26 #elif defined(CONFIG_SYS_FSL_IFC_BE)
  27 #define ifc_in32(a)       in_be32(a)
  28 #define ifc_out32(a, v)   out_be32(a, v)
  29 #define ifc_in16(a)       in_be16(a)
  30 #define ifc_out16(a, v)   out_be16(a, v)
  31 #else
  32 #error Neither CONFIG_SYS_FSL_IFC_LE nor CONFIG_SYS_FSL_IFC_BE is defined
  33 #endif
  34
  35
  36 /*
  37  * CSPR - Chip Select Property Register
  38  */
  39 #define CSPR_BA                         0xFFFF0000
  40 #define CSPR_BA_SHIFT                   16
  41 #define CSPR_PORT_SIZE                  0x00000180
  42 #define CSPR_PORT_SIZE_SHIFT            7
  43 /* Port Size 8 bit */
  44 #define CSPR_PORT_SIZE_8                0x00000080
  45 /* Port Size 16 bit */
  46 #define CSPR_PORT_SIZE_16               0x00000100
  47 /* Port Size 32 bit */
  48 #define CSPR_PORT_SIZE_32               0x00000180
  49 /* Write Protect */
  50 #define CSPR_WP                         0x00000040
  51 #define CSPR_WP_SHIFT                   6
  52 /* Machine Select */
  53 #define CSPR_MSEL                       0x00000006
  54 #define CSPR_MSEL_SHIFT                 1
  55 /* NOR */
  56 #define CSPR_MSEL_NOR                   0x00000000
  57 /* NAND */
  58 #define CSPR_MSEL_NAND                  0x00000002
  59 /* GPCM */
  60 #define CSPR_MSEL_GPCM                  0x00000004
  61 /* Bank Valid */
  62 #define CSPR_V                          0x00000001
  63 #define CSPR_V_SHIFT                    0
  64
  65 /* Convert an address into the right format for the CSPR Registers */
  66 #define CSPR_PHYS_ADDR(x)               (((uint64_t)x) & 0xffff0000)
  67
  68 /*
  69  * Address Mask Register
  70  */
  71 #define IFC_AMASK_MASK                  0xFFFF0000
  72 #define IFC_AMASK_SHIFT                 16
  73 #define IFC_AMASK(n)                    (IFC_AMASK_MASK << \
  74                                         (__ilog2(n) - IFC_AMASK_SHIFT))
  75
  76 /*
  77  * Chip Select Option Register IFC_NAND Machine
  78  */
  79 /* Enable ECC Encoder */
  80 #define CSOR_NAND_ECC_ENC_EN            0x80000000
  81 #define CSOR_NAND_ECC_MODE_MASK         0x30000000
  82 /* 4 bit correction per 520 Byte sector */
  83 #define CSOR_NAND_ECC_MODE_4            0x00000000
  84 /* 8 bit correction per 528 Byte sector */
  85 #define CSOR_NAND_ECC_MODE_8            0x10000000
  86 /* Enable ECC Decoder */
  87 #define CSOR_NAND_ECC_DEC_EN            0x04000000
  88 /* Row Address Length */
  89 #define CSOR_NAND_RAL_MASK              0x01800000
  90 #define CSOR_NAND_RAL_SHIFT             20
  91 #define CSOR_NAND_RAL_1                 0x00000000
  92 #define CSOR_NAND_RAL_2                 0x00800000
  93 #define CSOR_NAND_RAL_3                 0x01000000
  94 #define CSOR_NAND_RAL_4                 0x01800000
  95 /* Page Size 512b, 2k, 4k */
  96 #define CSOR_NAND_PGS_MASK              0x00180000
  97 #define CSOR_NAND_PGS_SHIFT             16
  98 #define CSOR_NAND_PGS_512               0x00000000
  99 #define CSOR_NAND_PGS_2K                0x00080000
 100 #define CSOR_NAND_PGS_4K                0x00100000
 101 #define CSOR_NAND_PGS_8K                0x00180000
 102 /* Spare region Size */
 103 #define CSOR_NAND_SPRZ_MASK             0x0000E000
 104 #define CSOR_NAND_SPRZ_SHIFT            13
 105 #define CSOR_NAND_SPRZ_16               0x00000000
 106 #define CSOR_NAND_SPRZ_64               0x00002000
 107 #define CSOR_NAND_SPRZ_128              0x00004000
 108 #define CSOR_NAND_SPRZ_210              0x00006000
 109 #define CSOR_NAND_SPRZ_218              0x00008000
 110 #define CSOR_NAND_SPRZ_224              0x0000A000
 111 #define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000
 112 /* Pages Per Block */
 113 #define CSOR_NAND_PB_MASK               0x00000700
 114 #define CSOR_NAND_PB_SHIFT              8
 115 #define CSOR_NAND_PB(n)         ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
 116 /* Time for Read Enable High to Output High Impedance */
 117 #define CSOR_NAND_TRHZ_MASK             0x0000001C
 118 #define CSOR_NAND_TRHZ_SHIFT            2
 119 #define CSOR_NAND_TRHZ_20               0x00000000
 120 #define CSOR_NAND_TRHZ_40               0x00000004
 121 #define CSOR_NAND_TRHZ_60               0x00000008
 122 #define CSOR_NAND_TRHZ_80               0x0000000C
 123 #define CSOR_NAND_TRHZ_100              0x00000010
 124 /* Buffer control disable */
 125 #define CSOR_NAND_BCTLD                 0x00000001
 126
 127 /*
 128  * Chip Select Option Register - NOR Flash Mode
 129  */
 130 /* Enable Address shift Mode */
 131 #define CSOR_NOR_ADM_SHFT_MODE_EN       0x80000000
 132 /* Page Read Enable from NOR device */
 133 #define CSOR_NOR_PGRD_EN                0x10000000
 134 /* AVD Toggle Enable during Burst Program */
 135 #define CSOR_NOR_AVD_TGL_PGM_EN         0x01000000
 136 /* Address Data Multiplexing Shift */
 137 #define CSOR_NOR_ADM_MASK               0x0003E000
 138 #define CSOR_NOR_ADM_SHIFT_SHIFT        13
 139 #define CSOR_NOR_ADM_SHIFT(n)   ((n) << CSOR_NOR_ADM_SHIFT_SHIFT)
 140 /* Type of the NOR device hooked */
 141 #define CSOR_NOR_NOR_MODE_AYSNC_NOR     0x00000000
 142 #define CSOR_NOR_NOR_MODE_AVD_NOR       0x00000020
 143 /* Time for Read Enable High to Output High Impedance */
 144 #define CSOR_NOR_TRHZ_MASK              0x0000001C
 145 #define CSOR_NOR_TRHZ_SHIFT             2
 146 #define CSOR_NOR_TRHZ_20                0x00000000
 147 #define CSOR_NOR_TRHZ_40                0x00000004
 148 #define CSOR_NOR_TRHZ_60                0x00000008
 149 #define CSOR_NOR_TRHZ_80                0x0000000C
 150 #define CSOR_NOR_TRHZ_100               0x00000010
 151 /* Buffer control disable */
 152 #define CSOR_NOR_BCTLD                  0x00000001
 153
 154 /*
 155  * Chip Select Option Register - GPCM Mode
 156  */
 157 /* GPCM Mode - Normal */
 158 #define CSOR_GPCM_GPMODE_NORMAL         0x00000000
 159 /* GPCM Mode - GenericASIC */
 160 #define CSOR_GPCM_GPMODE_ASIC           0x80000000
 161 /* Parity Mode odd/even */
 162 #define CSOR_GPCM_PARITY_EVEN           0x40000000
 163 /* Parity Checking enable/disable */
 164 #define CSOR_GPCM_PAR_EN                0x20000000
 165 /* GPCM Timeout Count */
 166 #define CSOR_GPCM_GPTO_MASK             0x0F000000
 167 #define CSOR_GPCM_GPTO_SHIFT            24
 168 #define CSOR_GPCM_GPTO(n)       ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
 169 /* GPCM External Access Termination mode for read access */
 170 #define CSOR_GPCM_RGETA_EXT             0x00080000
 171 /* GPCM External Access Termination mode for write access */
 172 #define CSOR_GPCM_WGETA_EXT             0x00040000
 173 /* Address Data Multiplexing Shift */
 174 #define CSOR_GPCM_ADM_MASK              0x0003E000
 175 #define CSOR_GPCM_ADM_SHIFT_SHIFT       13
 176 #define CSOR_GPCM_ADM_SHIFT(n)  ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT)
 177 /* Generic ASIC Parity error indication delay */
 178 #define CSOR_GPCM_GAPERRD_MASK          0x00000180
 179 #define CSOR_GPCM_GAPERRD_SHIFT         7
 180 #define CSOR_GPCM_GAPERRD(n)    (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT)
 181 /* Time for Read Enable High to Output High Impedance */
 182 #define CSOR_GPCM_TRHZ_MASK             0x0000001C
 183 #define CSOR_GPCM_TRHZ_20               0x00000000
 184 #define CSOR_GPCM_TRHZ_40               0x00000004
 185 #define CSOR_GPCM_TRHZ_60               0x00000008
 186 #define CSOR_GPCM_TRHZ_80               0x0000000C
 187 #define CSOR_GPCM_TRHZ_100              0x00000010
 188 /* Buffer control disable */
 189 #define CSOR_GPCM_BCTLD                 0x00000001
 190
 191 /*
 192  * Flash Timing Registers (FTIM0 - FTIM2_CSn)
 193  */
 194 /*
 195  * FTIM0 - NAND Flash Mode
 196  */
 197 #define FTIM0_NAND                      0x7EFF3F3F
 198 #define FTIM0_NAND_TCCST_SHIFT  25
 199 #define FTIM0_NAND_TCCST(n)     ((n) << FTIM0_NAND_TCCST_SHIFT)
 200 #define FTIM0_NAND_TWP_SHIFT    16
 201 #define FTIM0_NAND_TWP(n)       ((n) << FTIM0_NAND_TWP_SHIFT)
 202 #define FTIM0_NAND_TWCHT_SHIFT  8
 203 #define FTIM0_NAND_TWCHT(n)     ((n) << FTIM0_NAND_TWCHT_SHIFT)
 204 #define FTIM0_NAND_TWH_SHIFT    0
 205 #define FTIM0_NAND_TWH(n)       ((n) << FTIM0_NAND_TWH_SHIFT)
 206 /*
 207  * FTIM1 - NAND Flash Mode
 208  */
 209 #define FTIM1_NAND                      0xFFFF3FFF
 210 #define FTIM1_NAND_TADLE_SHIFT  24
 211 #define FTIM1_NAND_TADLE(n)     ((n) << FTIM1_NAND_TADLE_SHIFT)
 212 #define FTIM1_NAND_TWBE_SHIFT   16
 213 #define FTIM1_NAND_TWBE(n)      ((n) << FTIM1_NAND_TWBE_SHIFT)
 214 #define FTIM1_NAND_TRR_SHIFT    8
 215 #define FTIM1_NAND_TRR(n)       ((n) << FTIM1_NAND_TRR_SHIFT)
 216 #define FTIM1_NAND_TRP_SHIFT    0
 217 #define FTIM1_NAND_TRP(n)       ((n) << FTIM1_NAND_TRP_SHIFT)
 218 /*
 219  * FTIM2 - NAND Flash Mode
 220  */
 221 #define FTIM2_NAND                      0x1FE1F8FF
 222 #define FTIM2_NAND_TRAD_SHIFT   21
 223 #define FTIM2_NAND_TRAD(n)      ((n) << FTIM2_NAND_TRAD_SHIFT)
 224 #define FTIM2_NAND_TREH_SHIFT   11
 225 #define FTIM2_NAND_TREH(n)      ((n) << FTIM2_NAND_TREH_SHIFT)
 226 #define FTIM2_NAND_TWHRE_SHIFT  0
 227 #define FTIM2_NAND_TWHRE(n)     ((n) << FTIM2_NAND_TWHRE_SHIFT)
 228 /*
 229  * FTIM3 - NAND Flash Mode
 230  */
 231 #define FTIM3_NAND                      0xFF000000
 232 #define FTIM3_NAND_TWW_SHIFT    24
 233 #define FTIM3_NAND_TWW(n)       ((n) << FTIM3_NAND_TWW_SHIFT)
 234
 235 /*
 236  * FTIM0 - NOR Flash Mode
 237  */
 238 #define FTIM0_NOR                       0xF03F3F3F
 239 #define FTIM0_NOR_TACSE_SHIFT   28
 240 #define FTIM0_NOR_TACSE(n)      ((n) << FTIM0_NOR_TACSE_SHIFT)
 241 #define FTIM0_NOR_TEADC_SHIFT   16
 242 #define FTIM0_NOR_TEADC(n)      ((n) << FTIM0_NOR_TEADC_SHIFT)
 243 #define FTIM0_NOR_TAVDS_SHIFT   8
 244 #define FTIM0_NOR_TAVDS(n)      ((n) << FTIM0_NOR_TAVDS_SHIFT)
 245 #define FTIM0_NOR_TEAHC_SHIFT   0
 246 #define FTIM0_NOR_TEAHC(n)      ((n) << FTIM0_NOR_TEAHC_SHIFT)
 247 /*
 248  * FTIM1 - NOR Flash Mode
 249  */
 250 #define FTIM1_NOR                       0xFF003F3F
 251 #define FTIM1_NOR_TACO_SHIFT    24
 252 #define FTIM1_NOR_TACO(n)       ((n) << FTIM1_NOR_TACO_SHIFT)
 253 #define FTIM1_NOR_TRAD_NOR_SHIFT        8
 254 #define FTIM1_NOR_TRAD_NOR(n)   ((n) << FTIM1_NOR_TRAD_NOR_SHIFT)
 255 #define FTIM1_NOR_TSEQRAD_NOR_SHIFT     0
 256 #define FTIM1_NOR_TSEQRAD_NOR(n)        ((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT)
 257 /*
 258  * FTIM2 - NOR Flash Mode
 259  */
 260 #define FTIM2_NOR                       0x0F3CFCFF
 261 #define FTIM2_NOR_TCS_SHIFT             24
 262 #define FTIM2_NOR_TCS(n)        ((n) << FTIM2_NOR_TCS_SHIFT)
 263 #define FTIM2_NOR_TCH_SHIFT             18
 264 #define FTIM2_NOR_TCH(n)        ((n) << FTIM2_NOR_TCH_SHIFT)
 265 #define FTIM2_NOR_TWPH_SHIFT    10
 266 #define FTIM2_NOR_TWPH(n)       ((n) << FTIM2_NOR_TWPH_SHIFT)
 267 #define FTIM2_NOR_TWP_SHIFT             0
 268 #define FTIM2_NOR_TWP(n)        ((n) << FTIM2_NOR_TWP_SHIFT)
 269
 270 /*
 271  * FTIM0 - Normal GPCM Mode
 272  */
 273 #define FTIM0_GPCM                      0xF03F3F3F
 274 #define FTIM0_GPCM_TACSE_SHIFT  28
 275 #define FTIM0_GPCM_TACSE(n)     ((n) << FTIM0_GPCM_TACSE_SHIFT)
 276 #define FTIM0_GPCM_TEADC_SHIFT  16
 277 #define FTIM0_GPCM_TEADC(n)     ((n) << FTIM0_GPCM_TEADC_SHIFT)
 278 #define FTIM0_GPCM_TAVDS_SHIFT  8
 279 #define FTIM0_GPCM_TAVDS(n)     ((n) << FTIM0_GPCM_TAVDS_SHIFT)
 280 #define FTIM0_GPCM_TEAHC_SHIFT  0
 281 #define FTIM0_GPCM_TEAHC(n)     ((n) << FTIM0_GPCM_TEAHC_SHIFT)
 282 /*
 283  * FTIM1 - Normal GPCM Mode
 284  */
 285 #define FTIM1_GPCM                      0xFF003F00
 286 #define FTIM1_GPCM_TACO_SHIFT   24
 287 #define FTIM1_GPCM_TACO(n)      ((n) << FTIM1_GPCM_TACO_SHIFT)
 288 #define FTIM1_GPCM_TRAD_SHIFT   8
 289 #define FTIM1_GPCM_TRAD(n)      ((n) << FTIM1_GPCM_TRAD_SHIFT)
 290 /*
 291  * FTIM2 - Normal GPCM Mode
 292  */
 293 #define FTIM2_GPCM                      0x0F3C00FF
 294 #define FTIM2_GPCM_TCS_SHIFT    24
 295 #define FTIM2_GPCM_TCS(n)       ((n) << FTIM2_GPCM_TCS_SHIFT)
 296 #define FTIM2_GPCM_TCH_SHIFT    18
 297 #define FTIM2_GPCM_TCH(n)       ((n) << FTIM2_GPCM_TCH_SHIFT)
 298 #define FTIM2_GPCM_TWP_SHIFT    0
 299 #define FTIM2_GPCM_TWP(n)       ((n) << FTIM2_GPCM_TWP_SHIFT)
 300
 301 /*
 302  * Ready Busy Status Register (RB_STAT)
 303  */
 304 /* CSn is READY */
 305 #define IFC_RB_STAT_READY_CS0           0x80000000
 306 #define IFC_RB_STAT_READY_CS1           0x40000000
 307 #define IFC_RB_STAT_READY_CS2           0x20000000
 308 #define IFC_RB_STAT_READY_CS3           0x10000000
 309
 310 /*
 311  * General Control Register (GCR)
 312  */
 313 #define IFC_GCR_MASK                    0x8000F800
 314 /* reset all IFC hardware */
 315 #define IFC_GCR_SOFT_RST_ALL            0x80000000
 316 /* Turnaroud Time of external buffer */
 317 #define IFC_GCR_TBCTL_TRN_TIME          0x0000F800
 318 #define IFC_GCR_TBCTL_TRN_TIME_SHIFT    11
 319
 320 /*
 321  * Common Event and Error Status Register (CM_EVTER_STAT)
 322  */
 323 /* Chip select error */
 324 #define IFC_CM_EVTER_STAT_CSER          0x80000000
 325
 326 /*
 327  * Common Event and Error Enable Register (CM_EVTER_EN)
 328  */
 329 /* Chip select error checking enable */
 330 #define IFC_CM_EVTER_EN_CSEREN          0x80000000
 331
 332 /*
 333  * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN)
 334  */
 335 /* Chip select error interrupt enable */
 336 #define IFC_CM_EVTER_INTR_EN_CSERIREN   0x80000000
 337
 338 /*
 339  * Common Transfer Error Attribute Register-0 (CM_ERATTR0)
 340  */
 341 /* transaction type of error Read/Write */
 342 #define IFC_CM_ERATTR0_ERTYP_READ       0x80000000
 343 #define IFC_CM_ERATTR0_ERAID            0x0FF00000
 344 #define IFC_CM_ERATTR0_ESRCID           0x0000FF00
 345
 346 /*
 347  * Clock Control Register (CCR)
 348  */
 349 #define IFC_CCR_MASK                    0x0F0F8800
 350 /* Clock division ratio */
 351 #define IFC_CCR_CLK_DIV_MASK            0x0F000000
 352 #define IFC_CCR_CLK_DIV_SHIFT           24
 353 #define IFC_CCR_CLK_DIV(n)              ((n-1) << IFC_CCR_CLK_DIV_SHIFT)
 354 /* IFC Clock Delay */
 355 #define IFC_CCR_CLK_DLY_MASK            0x000F0000
 356 #define IFC_CCR_CLK_DLY_SHIFT           16
 357 #define IFC_CCR_CLK_DLY(n)              ((n) << IFC_CCR_CLK_DLY_SHIFT)
 358 /* Invert IFC clock before sending out */
 359 #define IFC_CCR_INV_CLK_EN              0x00008000
 360 /* Fedback IFC Clock */
 361 #define IFC_CCR_FB_IFC_CLK_SEL          0x00000800
 362
 363 /*
 364  * Clock Status Register (CSR)
 365  */
 366 /* Clk is stable */
 367 #define IFC_CSR_CLK_STAT_STABLE         0x80000000
 368
 369 /*
 370  * IFC_NAND Machine Specific Registers
 371  */
 372 /*
 373  * NAND Configuration Register (NCFGR)
 374  */
 375 /* Auto Boot Mode */
 376 #define IFC_NAND_NCFGR_BOOT             0x80000000
 377 /* SRAM INIT EN */
 378 #define IFC_NAND_SRAM_INIT_EN           0x20000000
 379 /* Addressing Mode-ROW0+n/COL0 */
 380 #define IFC_NAND_NCFGR_ADDR_MODE_RC0    0x00000000
 381 /* Addressing Mode-ROW0+n/COL0+n */
 382 #define IFC_NAND_NCFGR_ADDR_MODE_RC1    0x00400000
 383 /* Number of loop iterations of FIR sequences for multi page operations */
 384 #define IFC_NAND_NCFGR_NUM_LOOP_MASK    0x0000F000
 385 #define IFC_NAND_NCFGR_NUM_LOOP_SHIFT   12
 386 #define IFC_NAND_NCFGR_NUM_LOOP(n)      ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT)
 387 /* Number of wait cycles */
 388 #define IFC_NAND_NCFGR_NUM_WAIT_MASK    0x000000FF
 389 #define IFC_NAND_NCFGR_NUM_WAIT_SHIFT   0
 390
 391 /*
 392  * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
 393  */
 394 /* General purpose FCM flash command bytes CMD0-CMD7 */
 395 #define IFC_NAND_FCR0_CMD0              0xFF000000
 396 #define IFC_NAND_FCR0_CMD0_SHIFT        24
 397 #define IFC_NAND_FCR0_CMD1              0x00FF0000
 398 #define IFC_NAND_FCR0_CMD1_SHIFT        16
 399 #define IFC_NAND_FCR0_CMD2              0x0000FF00
 400 #define IFC_NAND_FCR0_CMD2_SHIFT        8
 401 #define IFC_NAND_FCR0_CMD3              0x000000FF
 402 #define IFC_NAND_FCR0_CMD3_SHIFT        0
 403 #define IFC_NAND_FCR1_CMD4              0xFF000000
 404 #define IFC_NAND_FCR1_CMD4_SHIFT        24
 405 #define IFC_NAND_FCR1_CMD5              0x00FF0000
 406 #define IFC_NAND_FCR1_CMD5_SHIFT        16
 407 #define IFC_NAND_FCR1_CMD6              0x0000FF00
 408 #define IFC_NAND_FCR1_CMD6_SHIFT        8
 409 #define IFC_NAND_FCR1_CMD7              0x000000FF
 410 #define IFC_NAND_FCR1_CMD7_SHIFT        0
 411
 412 /*
 413  * Flash ROW and COL Address Register (ROWn, COLn)
 414  */
 415 /* Main/spare region locator */
 416 #define IFC_NAND_COL_MS                 0x80000000
 417 /* Column Address */
 418 #define IFC_NAND_COL_CA_MASK            0x00000FFF
 419
 420 /*
 421  * NAND Flash Byte Count Register (NAND_BC)
 422  */
 423 /* Byte Count for read/Write */
 424 #define IFC_NAND_BC                     0x000001FF
 425
 426 /*
 427  * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
 428  */
 429 /* NAND Machine specific opcodes OP0-OP14*/
 430 #define IFC_NAND_FIR0_OP0               0xFC000000
 431 #define IFC_NAND_FIR0_OP0_SHIFT         26
 432 #define IFC_NAND_FIR0_OP1               0x03F00000
 433 #define IFC_NAND_FIR0_OP1_SHIFT         20
 434 #define IFC_NAND_FIR0_OP2               0x000FC000
 435 #define IFC_NAND_FIR0_OP2_SHIFT         14
 436 #define IFC_NAND_FIR0_OP3               0x00003F00
 437 #define IFC_NAND_FIR0_OP3_SHIFT         8
 438 #define IFC_NAND_FIR0_OP4               0x000000FC
 439 #define IFC_NAND_FIR0_OP4_SHIFT         2
 440 #define IFC_NAND_FIR1_OP5               0xFC000000
 441 #define IFC_NAND_FIR1_OP5_SHIFT         26
 442 #define IFC_NAND_FIR1_OP6               0x03F00000
 443 #define IFC_NAND_FIR1_OP6_SHIFT         20
 444 #define IFC_NAND_FIR1_OP7               0x000FC000
 445 #define IFC_NAND_FIR1_OP7_SHIFT         14
 446 #define IFC_NAND_FIR1_OP8               0x00003F00
 447 #define IFC_NAND_FIR1_OP8_SHIFT         8
 448 #define IFC_NAND_FIR1_OP9               0x000000FC
 449 #define IFC_NAND_FIR1_OP9_SHIFT         2
 450 #define IFC_NAND_FIR2_OP10              0xFC000000
 451 #define IFC_NAND_FIR2_OP10_SHIFT        26
 452 #define IFC_NAND_FIR2_OP11              0x03F00000
 453 #define IFC_NAND_FIR2_OP11_SHIFT        20
 454 #define IFC_NAND_FIR2_OP12              0x000FC000
 455 #define IFC_NAND_FIR2_OP12_SHIFT        14
 456 #define IFC_NAND_FIR2_OP13              0x00003F00
 457 #define IFC_NAND_FIR2_OP13_SHIFT        8
 458 #define IFC_NAND_FIR2_OP14              0x000000FC
 459 #define IFC_NAND_FIR2_OP14_SHIFT        2
 460
 461 /*
 462  * Instruction opcodes to be programmed
 463  * in FIR registers- 6bits
 464  */
 465 enum ifc_nand_fir_opcodes {
 466         IFC_FIR_OP_NOP,
 467         IFC_FIR_OP_CA0,
 468         IFC_FIR_OP_CA1,
 469         IFC_FIR_OP_CA2,
 470         IFC_FIR_OP_CA3,
 471         IFC_FIR_OP_RA0,
 472         IFC_FIR_OP_RA1,
 473         IFC_FIR_OP_RA2,
 474         IFC_FIR_OP_RA3,
 475         IFC_FIR_OP_CMD0,
 476         IFC_FIR_OP_CMD1,
 477         IFC_FIR_OP_CMD2,
 478         IFC_FIR_OP_CMD3,
 479         IFC_FIR_OP_CMD4,
 480         IFC_FIR_OP_CMD5,
 481         IFC_FIR_OP_CMD6,
 482         IFC_FIR_OP_CMD7,
 483         IFC_FIR_OP_CW0,
 484         IFC_FIR_OP_CW1,
 485         IFC_FIR_OP_CW2,
 486         IFC_FIR_OP_CW3,
 487         IFC_FIR_OP_CW4,
 488         IFC_FIR_OP_CW5,
 489         IFC_FIR_OP_CW6,
 490         IFC_FIR_OP_CW7,
 491         IFC_FIR_OP_WBCD,
 492         IFC_FIR_OP_RBCD,
 493         IFC_FIR_OP_BTRD,
 494         IFC_FIR_OP_RDSTAT,
 495         IFC_FIR_OP_NWAIT,
 496         IFC_FIR_OP_WFR,
 497         IFC_FIR_OP_SBRD,
 498         IFC_FIR_OP_UA,
 499         IFC_FIR_OP_RB,
 500 };
 501
 502 /*
 503  * NAND Chip Select Register (NAND_CSEL)
 504  */
 505 #define IFC_NAND_CSEL                   0x0C000000
 506 #define IFC_NAND_CSEL_SHIFT             26
 507 #define IFC_NAND_CSEL_CS0               0x00000000
 508 #define IFC_NAND_CSEL_CS1               0x04000000
 509 #define IFC_NAND_CSEL_CS2               0x08000000
 510 #define IFC_NAND_CSEL_CS3               0x0C000000
 511
 512 /*
 513  * NAND Operation Sequence Start (NANDSEQ_STRT)
 514  */
 515 /* NAND Flash Operation Start */
 516 #define IFC_NAND_SEQ_STRT_FIR_STRT      0x80000000
 517 /* Automatic Erase */
 518 #define IFC_NAND_SEQ_STRT_AUTO_ERS      0x00800000
 519 /* Automatic Program */
 520 #define IFC_NAND_SEQ_STRT_AUTO_PGM      0x00100000
 521 /* Automatic Copyback */
 522 #define IFC_NAND_SEQ_STRT_AUTO_CPB      0x00020000
 523 /* Automatic Read Operation */
 524 #define IFC_NAND_SEQ_STRT_AUTO_RD       0x00004000
 525 /* Automatic Status Read */
 526 #define IFC_NAND_SEQ_STRT_AUTO_STAT_RD  0x00000800
 527
 528 /*
 529  * NAND Event and Error Status Register (NAND_EVTER_STAT)
 530  */
 531 /* Operation Complete */
 532 #define IFC_NAND_EVTER_STAT_OPC         0x80000000
 533 /* Flash Timeout Error */
 534 #define IFC_NAND_EVTER_STAT_FTOER       0x08000000
 535 /* Write Protect Error */
 536 #define IFC_NAND_EVTER_STAT_WPER        0x04000000
 537 /* ECC Error */
 538 #define IFC_NAND_EVTER_STAT_ECCER       0x02000000
 539 /* RCW Load Done */
 540 #define IFC_NAND_EVTER_STAT_RCW_DN      0x00008000
 541 /* Boot Loadr Done */
 542 #define IFC_NAND_EVTER_STAT_BOOT_DN     0x00004000
 543 /* Bad Block Indicator search select */
 544 #define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800
 545
 546 /*
 547  * NAND Flash Page Read Completion Event Status Register
 548  * (PGRDCMPL_EVT_STAT)
 549  */
 550 #define PGRDCMPL_EVT_STAT_MASK          0xFFFF0000
 551 /* Small Page 0-15 Done */
 552 #define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n)))
 553 /* Large Page(2K) 0-3 Done */
 554 #define PGRDCMPL_EVT_STAT_LP_2K(n)      (0xF << (28 - (n)*4))
 555 /* Large Page(4K) 0-1 Done */
 556 #define PGRDCMPL_EVT_STAT_LP_4K(n)      (0xFF << (24 - (n)*8))
 557
 558 /*
 559  * NAND Event and Error Enable Register (NAND_EVTER_EN)
 560  */
 561 /* Operation complete event enable */
 562 #define IFC_NAND_EVTER_EN_OPC_EN        0x80000000
 563 /* Page read complete event enable */
 564 #define IFC_NAND_EVTER_EN_PGRDCMPL_EN   0x20000000
 565 /* Flash Timeout error enable */
 566 #define IFC_NAND_EVTER_EN_FTOER_EN      0x08000000
 567 /* Write Protect error enable */
 568 #define IFC_NAND_EVTER_EN_WPER_EN       0x04000000
 569 /* ECC error logging enable */
 570 #define IFC_NAND_EVTER_EN_ECCER_EN      0x02000000
 571
 572 /*
 573  * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN)
 574  */
 575 /* Enable interrupt for operation complete */
 576 #define IFC_NAND_EVTER_INTR_OPCIR_EN            0x80000000
 577 /* Enable interrupt for Page read complete */
 578 #define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN       0x20000000
 579 /* Enable interrupt for Flash timeout error */
 580 #define IFC_NAND_EVTER_INTR_FTOERIR_EN          0x08000000
 581 /* Enable interrupt for Write protect error */
 582 #define IFC_NAND_EVTER_INTR_WPERIR_EN           0x04000000
 583 /* Enable interrupt for ECC error*/
 584 #define IFC_NAND_EVTER_INTR_ECCERIR_EN          0x02000000
 585
 586 /*
 587  * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0)
 588  */
 589 #define IFC_NAND_ERATTR0_MASK           0x0C080000
 590 /* Error on CS0-3 for NAND */
 591 #define IFC_NAND_ERATTR0_ERCS_CS0       0x00000000
 592 #define IFC_NAND_ERATTR0_ERCS_CS1       0x04000000
 593 #define IFC_NAND_ERATTR0_ERCS_CS2       0x08000000
 594 #define IFC_NAND_ERATTR0_ERCS_CS3       0x0C000000
 595 /* Transaction type of error Read/Write */
 596 #define IFC_NAND_ERATTR0_ERTTYPE_READ   0x00080000
 597
 598 /*
 599  * NAND Flash Status Register (NAND_FSR)
 600  */
 601 /* First byte of data read from read status op */
 602 #define IFC_NAND_NFSR_RS0               0xFF000000
 603 /* Second byte of data read from read status op */
 604 #define IFC_NAND_NFSR_RS1               0x00FF0000
 605
 606 /*
 607  * ECC Error Status Registers (ECCSTAT0-ECCSTAT3)
 608  */
 609 /* Number of ECC errors on sector n (n = 0-15) */
 610 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK   0x0F000000
 611 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT  24
 612 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK   0x000F0000
 613 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT  16
 614 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK   0x00000F00
 615 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT  8
 616 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK   0x0000000F
 617 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT  0
 618 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK   0x0F000000
 619 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT  24
 620 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK   0x000F0000
 621 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT  16
 622 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK   0x00000F00
 623 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT  8
 624 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK   0x0000000F
 625 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT  0
 626 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK   0x0F000000
 627 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT  24
 628 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK   0x000F0000
 629 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT  16
 630 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK  0x00000F00
 631 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8
 632 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK  0x0000000F
 633 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0
 634 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK  0x0F000000
 635 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24
 636 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK  0x000F0000
 637 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16
 638 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK  0x00000F00
 639 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8
 640 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK  0x0000000F
 641 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0
 642
 643 /*
 644  * NAND Control Register (NANDCR)
 645  */
 646 #define IFC_NAND_NCR_FTOCNT_MASK        0x1E000000
 647 #define IFC_NAND_NCR_FTOCNT_SHIFT       25
 648 #define IFC_NAND_NCR_FTOCNT(n)  ((_ilog2(n) - 8)  << IFC_NAND_NCR_FTOCNT_SHIFT)
 649
 650 /*
 651  * NAND_AUTOBOOT_TRGR
 652  */
 653 /* Trigger RCW load */
 654 #define IFC_NAND_AUTOBOOT_TRGR_RCW_LD   0x80000000
 655 /* Trigget Auto Boot */
 656 #define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD  0x20000000
 657
 658 /*
 659  * NAND_MDR
 660  */
 661 /* 1st read data byte when opcode SBRD */
 662 #define IFC_NAND_MDR_RDATA0             0xFF000000
 663 /* 2nd read data byte when opcode SBRD */
 664 #define IFC_NAND_MDR_RDATA1             0x00FF0000
 665
 666 /*
 667  * NOR Machine Specific Registers
 668  */
 669 /*
 670  * NOR Event and Error Status Register (NOR_EVTER_STAT)
 671  */
 672 /* NOR Command Sequence Operation Complete */
 673 #define IFC_NOR_EVTER_STAT_OPC_NOR      0x80000000
 674 /* Write Protect Error */
 675 #define IFC_NOR_EVTER_STAT_WPER         0x04000000
 676 /* Command Sequence Timeout Error */
 677 #define IFC_NOR_EVTER_STAT_STOER        0x01000000
 678
 679 /*
 680  * NOR Event and Error Enable Register (NOR_EVTER_EN)
 681  */
 682 /* NOR Command Seq complete event enable */
 683 #define IFC_NOR_EVTER_EN_OPCEN_NOR      0x80000000
 684 /* Write Protect Error Checking Enable */
 685 #define IFC_NOR_EVTER_EN_WPEREN         0x04000000
 686 /* Timeout Error Enable */
 687 #define IFC_NOR_EVTER_EN_STOEREN        0x01000000
 688
 689 /*
 690  * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN)
 691  */
 692 /* Enable interrupt for OPC complete */
 693 #define IFC_NOR_EVTER_INTR_OPCEN_NOR    0x80000000
 694 /* Enable interrupt for write protect error */
 695 #define IFC_NOR_EVTER_INTR_WPEREN       0x04000000
 696 /* Enable interrupt for timeout error */
 697 #define IFC_NOR_EVTER_INTR_STOEREN      0x01000000
 698
 699 /*
 700  * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0)
 701  */
 702 /* Source ID for error transaction */
 703 #define IFC_NOR_ERATTR0_ERSRCID         0xFF000000
 704 /* AXI ID for error transation */
 705 #define IFC_NOR_ERATTR0_ERAID           0x000FF000
 706 /* Chip select corresponds to NOR error */
 707 #define IFC_NOR_ERATTR0_ERCS_CS0        0x00000000
 708 #define IFC_NOR_ERATTR0_ERCS_CS1        0x00000010
 709 #define IFC_NOR_ERATTR0_ERCS_CS2        0x00000020
 710 #define IFC_NOR_ERATTR0_ERCS_CS3        0x00000030
 711 /* Type of transaction read/write */
 712 #define IFC_NOR_ERATTR0_ERTYPE_READ     0x00000001
 713
 714 /*
 715  * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2)
 716  */
 717 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP        0x000F0000
 718 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER        0x00000F00
 719
 720 /*
 721  * NOR Control Register (NORCR)
 722  */
 723 #define IFC_NORCR_MASK                  0x0F0F0000
 724 /* No. of Address/Data Phase */
 725 #define IFC_NORCR_NUM_PHASE_MASK        0x0F000000
 726 #define IFC_NORCR_NUM_PHASE_SHIFT       24
 727 #define IFC_NORCR_NUM_PHASE(n)  ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT)
 728 /* Sequence Timeout Count */
 729 #define IFC_NORCR_STOCNT_MASK           0x000F0000
 730 #define IFC_NORCR_STOCNT_SHIFT          16
 731 #define IFC_NORCR_STOCNT(n)     ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
 732
 733 /*
 734  * GPCM Machine specific registers
 735  */
 736 /*
 737  * GPCM Event and Error Status Register (GPCM_EVTER_STAT)
 738  */
 739 /* Timeout error */
 740 #define IFC_GPCM_EVTER_STAT_TOER        0x04000000
 741 /* Parity error */
 742 #define IFC_GPCM_EVTER_STAT_PER         0x01000000
 743
 744 /*
 745  * GPCM Event and Error Enable Register (GPCM_EVTER_EN)
 746  */
 747 /* Timeout error enable */
 748 #define IFC_GPCM_EVTER_EN_TOER_EN       0x04000000
 749 /* Parity error enable */
 750 #define IFC_GPCM_EVTER_EN_PER_EN        0x01000000
 751
 752 /*
 753  * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN)
 754  */
 755 /* Enable Interrupt for timeout error */
 756 #define IFC_GPCM_EEIER_TOERIR_EN        0x04000000
 757 /* Enable Interrupt for Parity error */
 758 #define IFC_GPCM_EEIER_PERIR_EN         0x01000000
 759
 760 /*
 761  * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0)
 762  */
 763 /* Source ID for error transaction */
 764 #define IFC_GPCM_ERATTR0_ERSRCID        0xFF000000
 765 /* AXI ID for error transaction */
 766 #define IFC_GPCM_ERATTR0_ERAID          0x000FF000
 767 /* Chip select corresponds to GPCM error */
 768 #define IFC_GPCM_ERATTR0_ERCS_CS0       0x00000000
 769 #define IFC_GPCM_ERATTR0_ERCS_CS1       0x00000040
 770 #define IFC_GPCM_ERATTR0_ERCS_CS2       0x00000080
 771 #define IFC_GPCM_ERATTR0_ERCS_CS3       0x000000C0
 772 /* Type of transaction read/Write */
 773 #define IFC_GPCM_ERATTR0_ERTYPE_READ    0x00000001
 774
 775 /*
 776  * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2)
 777  */
 778 /* On which beat of address/data parity error is observed */
 779 #define IFC_GPCM_ERATTR2_PERR_BEAT              0x00000C00
 780 /* Parity Error on byte */
 781 #define IFC_GPCM_ERATTR2_PERR_BYTE              0x000000F0
 782 /* Parity Error reported in addr or data phase */
 783 #define IFC_GPCM_ERATTR2_PERR_DATA_PHASE        0x00000001
 784
 785 /*
 786  * GPCM Status Register (GPCM_STAT)
 787  */
 788 #define IFC_GPCM_STAT_BSY               0x80000000  /* GPCM is busy */
 789
 790
 791 #ifndef __ASSEMBLY__
 792 #include <asm/io.h>
 793
 794 extern void print_ifc_regs(void);
 795 extern void init_early_memctl_regs(void);
 796 void init_final_memctl_regs(void);
 797
 798 #define IFC_RREGS_4KOFFSET      (4*1024)
 799 #define IFC_RREGS_64KOFFSET     (64*1024)
 800
 801 #define IFC_FCM_BASE_ADDR \
 802         ((struct fsl_ifc_fcm *)CONFIG_SYS_IFC_ADDR)
 803
 804 #define get_ifc_cspr_ext(i)     \
 805                 (ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext))
 806 #define get_ifc_cspr(i)         \
 807                 (ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr))
 808 #define get_ifc_csor_ext(i)     \
 809                 (ifc_in32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor_ext))
 810 #define get_ifc_csor(i)         \
 811                 (ifc_in32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor))
 812 #define get_ifc_amask(i)        \
 813                 (ifc_in32(&(IFC_FCM_BASE_ADDR)->amask_cs[i].amask))
 814 #define get_ifc_ftim(i, j)      \
 815                 (ifc_in32(&(IFC_FCM_BASE_ADDR)->ftim_cs[i].ftim[j]))
 816 #define set_ifc_cspr_ext(i, v)  \
 817                 (ifc_out32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext, v))
 818 #define set_ifc_cspr(i, v)      \
 819                 (ifc_out32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr, v))
 820 #define set_ifc_csor_ext(i, v)  \
 821                 (ifc_out32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor_ext, v))
 822 #define set_ifc_csor(i, v)      \
 823                 (ifc_out32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor, v))
 824 #define set_ifc_amask(i, v)     \
 825                 (ifc_out32(&(IFC_FCM_BASE_ADDR)->amask_cs[i].amask, v))
 826 #define set_ifc_ftim(i, j, v)   \
 827                 (ifc_out32(&(IFC_FCM_BASE_ADDR)->ftim_cs[i].ftim[j], v))
 828
 829 enum ifc_chip_sel {
 830         IFC_CS0,
 831         IFC_CS1,
 832         IFC_CS2,
 833         IFC_CS3,
 834         IFC_CS4,
 835         IFC_CS5,
 836         IFC_CS6,
 837         IFC_CS7,
 838 };
 839
 840 enum ifc_ftims {
 841         IFC_FTIM0,
 842         IFC_FTIM1,
 843         IFC_FTIM2,
 844         IFC_FTIM3,
 845 };
 846
 847 /*
 848  * IFC Controller NAND Machine registers
 849  */
 850 struct fsl_ifc_nand {
 851         u32 ncfgr;
 852         u32 res1[0x4];
 853         u32 nand_fcr0;
 854         u32 nand_fcr1;
 855         u32 res2[0x8];
 856         u32 row0;
 857         u32 res3;
 858         u32 col0;
 859         u32 res4;
 860         u32 row1;
 861         u32 res5;
 862         u32 col1;
 863         u32 res6;
 864         u32 row2;
 865         u32 res7;
 866         u32 col2;
 867         u32 res8;
 868         u32 row3;
 869         u32 res9;
 870         u32 col3;
 871         u32 res10[0x24];
 872         u32 nand_fbcr;
 873         u32 res11;
 874         u32 nand_fir0;
 875         u32 nand_fir1;
 876         u32 nand_fir2;
 877         u32 res12[0x10];
 878         u32 nand_csel;
 879         u32 res13;
 880         u32 nandseq_strt;
 881         u32 res14;
 882         u32 nand_evter_stat;
 883         u32 res15;
 884         u32 pgrdcmpl_evt_stat;
 885         u32 res16[0x2];
 886         u32 nand_evter_en;
 887         u32 res17[0x2];
 888         u32 nand_evter_intr_en;
 889         u32 nand_vol_addr_stat;
 890         u32 res18;
 891         u32 nand_erattr0;
 892         u32 nand_erattr1;
 893         u32 res19[0x10];
 894         u32 nand_fsr;
 895         u32 res20[0x3];
 896         u32 nand_eccstat[6];
 897         u32 res21[0x1c];
 898         u32 nanndcr;
 899         u32 res22[0x2];
 900         u32 nand_autoboot_trgr;
 901         u32 res23;
 902         u32 nand_mdr;
 903         u32 res24[0x1c];
 904         u32 nand_dll_lowcfg0;
 905         u32 nand_dll_lowcfg1;
 906         u32 res25;
 907         u32 nand_dll_lowstat;
 908         u32 res26[0x3C];
 909 };
 910
 911 /*
 912  * IFC controller NOR Machine registers
 913  */
 914 struct fsl_ifc_nor {
 915         u32 nor_evter_stat;
 916         u32 res1[0x2];
 917         u32 nor_evter_en;
 918         u32 res2[0x2];
 919         u32 nor_evter_intr_en;
 920         u32 res3[0x2];
 921         u32 nor_erattr0;
 922         u32 nor_erattr1;
 923         u32 nor_erattr2;
 924         u32 res4[0x4];
 925         u32 norcr;
 926         u32 res5[0xEF];
 927 };
 928
 929 /*
 930  * IFC controller GPCM Machine registers
 931  */
 932 struct fsl_ifc_gpcm {
 933         u32 gpcm_evter_stat;
 934         u32 res1[0x2];
 935         u32 gpcm_evter_en;
 936         u32 res2[0x2];
 937         u32 gpcm_evter_intr_en;
 938         u32 res3[0x2];
 939         u32 gpcm_erattr0;
 940         u32 gpcm_erattr1;
 941         u32 gpcm_erattr2;
 942         u32 gpcm_stat;
 943 };
 944
 945 #ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT
 946 #if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8)
 947 #define IFC_CSPR_REG_LEN        148
 948 #define IFC_AMASK_REG_LEN       144
 949 #define IFC_CSOR_REG_LEN        144
 950 #define IFC_FTIM_REG_LEN        576
 951
 952 #define IFC_CSPR_USED_LEN       sizeof(struct fsl_ifc_cspr) * \
 953                                         CONFIG_SYS_FSL_IFC_BANK_COUNT
 954 #define IFC_AMASK_USED_LEN      sizeof(struct fsl_ifc_amask) * \
 955                                         CONFIG_SYS_FSL_IFC_BANK_COUNT
 956 #define IFC_CSOR_USED_LEN       sizeof(struct fsl_ifc_csor) * \
 957                                         CONFIG_SYS_FSL_IFC_BANK_COUNT
 958 #define IFC_FTIM_USED_LEN       sizeof(struct fsl_ifc_ftim) * \
 959                                         CONFIG_SYS_FSL_IFC_BANK_COUNT
 960 #else
 961 #error IFC BANK count not vaild
 962 #endif
 963 #else
 964 #error IFC BANK count not defined
 965 #endif
 966
 967 struct fsl_ifc_cspr {
 968         u32 cspr_ext;
 969         u32 cspr;
 970         u32 res;
 971 };
 972
 973 struct fsl_ifc_amask {
 974         u32 amask;
 975         u32 res[0x2];
 976 };
 977
 978 struct fsl_ifc_csor {
 979         u32 csor;
 980         u32 csor_ext;
 981         u32 res;
 982 };
 983
 984 struct fsl_ifc_ftim {
 985         u32 ftim[4];
 986         u32 res[0x8];
 987 };
 988
 989 /*
 990  * IFC Controller Global Registers
 991  * FCM - Flash control machine
 992  */
 993
 994 struct fsl_ifc_fcm {
 995         u32 ifc_rev;
 996         u32 res1[0x2];
 997         struct fsl_ifc_cspr cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
 998         u8 res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN];
 999         struct fsl_ifc_amask amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
1000         u8 res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN];
1001         struct fsl_ifc_csor csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
1002         u8 res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN];
1003         struct fsl_ifc_ftim ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
1004         u8 res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN];
1005         u32 rb_stat;
1006         u32 rb_map;
1007         u32 wp_map;
1008         u32 ifc_gcr;
1009         u32 res7[0x2];
1010         u32 cm_evter_stat;
1011         u32 res8[0x2];
1012         u32 cm_evter_en;
1013         u32 res9[0x2];
1014         u32 cm_evter_intr_en;
1015         u32 res10[0x2];
1016         u32 cm_erattr0;
1017         u32 cm_erattr1;
1018         u32 res11[0x2];
1019         u32 ifc_ccr;
1020         u32 ifc_csr;
1021         u32 ddr_ccr_low;
1022 };
1023
1024 struct fsl_ifc_runtime {
1025         struct fsl_ifc_nand ifc_nand;
1026         struct fsl_ifc_nor ifc_nor;
1027         struct fsl_ifc_gpcm ifc_gpcm;
1028 };
1029
1030 struct fsl_ifc {
1031         struct fsl_ifc_fcm *gregs;
1032         struct fsl_ifc_runtime *rregs;
1033 };
1034
1035 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
1036 #undef CSPR_MSEL_NOR
1037 #define CSPR_MSEL_NOR   CSPR_MSEL_GPCM
1038 #endif
1039 #endif /* CONFIG_FSL_IFC */
1040
1041 #endif /* __ASSEMBLY__ */
1042 #endif /* __FSL_IFC_H */