include/fsl_mc.h

   1 /*
   2  * Copyright (C) 2014 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __FSL_MC_H__
   8 #define __FSL_MC_H__
   9
  10 #include <common.h>
  11
  12 #define MC_CCSR_BASE_ADDR \
  13         ((struct mc_ccsr_registers __iomem *)0x8340000)
  14
  15 #define BIT(x)                  (1 << (x))
  16 #define GCR1_P1_STOP            BIT(31)
  17 #define GCR1_P2_STOP            BIT(30)
  18 #define GCR1_P1_DE_RST          BIT(23)
  19 #define GCR1_P2_DE_RST          BIT(22)
  20 #define GCR1_M1_DE_RST          BIT(15)
  21 #define GCR1_M2_DE_RST          BIT(14)
  22 #define GCR1_M_ALL_DE_RST       (GCR1_M1_DE_RST | GCR1_M2_DE_RST)
  23 #define GSR_FS_MASK             0x3fffffff
  24 #define MCFAPR_PL_MASK          (0x1 << 18)
  25 #define MCFAPR_BMT_MASK         (0x1 << 17)
  26 #define MCFAPR_BYPASS_ICID_MASK \
  27         (MCFAPR_PL_MASK | MCFAPR_BMT_MASK)
  28
  29 #define SOC_MC_PORTALS_BASE_ADDR    ((void __iomem *)0x00080C000000)
  30 #define SOC_MC_PORTAL_STRIDE        0x10000
  31
  32 #define SOC_MC_PORTAL_ADDR(_portal_id) \
  33         ((void __iomem *)((uintptr_t)SOC_MC_PORTALS_BASE_ADDR + \
  34          (_portal_id) * SOC_MC_PORTAL_STRIDE))
  35
  36 struct mc_ccsr_registers {
  37         u32 reg_gcr1;
  38         u32 reserved1;
  39         u32 reg_gsr;
  40         u32 reserved2;
  41         u32 reg_sicbalr;
  42         u32 reg_sicbahr;
  43         u32 reg_sicapr;
  44         u32 reserved3;
  45         u32 reg_mcfbalr;
  46         u32 reg_mcfbahr;
  47         u32 reg_mcfapr;
  48         u32 reserved4[0x2f1];
  49         u32 reg_psr;
  50         u32 reserved5;
  51         u32 reg_brr[2];
  52         u32 reserved6[0x80];
  53         u32 reg_error[];
  54 };
  55
  56 int mc_init(bd_t *bis);
  57
  58 int get_mc_boot_status(void);
  59 #endif