include/fsl_mmdc.h

   1 /*
   2  * Copyright 2016 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef FSL_MMDC_H
   8 #define FSL_MMDC_H
   9
  10 #define CONFIG_SYS_MMDC_CORE_ODT_TIMING         0x12554000
  11 #define CONFIG_SYS_MMDC_CORE_TIMING_CFG_0       0xbabf7954
  12 #define CONFIG_SYS_MMDC_CORE_TIMING_CFG_1       0xff328f64
  13 #define CONFIG_SYS_MMDC_CORE_TIMING_CFG_2       0x01ff00db
  14
  15 #define CONFIG_SYS_MMDC_CORE_MISC               0x00000680
  16 #define CONFIG_SYS_MMDC_PHY_MEASURE_UNIT        0x00000800
  17 #define CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY     0x00002000
  18 #define CONFIG_SYS_MMDC_PHY_ODT_CTRL            0x0000022a
  19
  20 #define CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY 0x00bf1023
  21
  22 #define CONFIG_SYS_MMDC_CORE_ADDR_PARTITION     0x0000007f
  23
  24 #define CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL          0xa1390003
  25
  26 #define FORCE_ZQ_AUTO_CALIBRATION               (0x1 << 16)
  27
  28 /* PHY Write Leveling Configuration and Error Status (MPWLGCR) */
  29 #define WR_LVL_HW_EN                            0x00000001
  30
  31 /* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */
  32 #define MPR_COMPARE_EN                          0x00000001
  33
  34 #define CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG    0x40404040
  35
  36 /* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */
  37 #define AUTO_RD_DQS_GATING_CALIBRATION_EN       0x10000000
  38
  39 /* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */
  40 #define AUTO_RD_CALIBRATION_EN                  0x00000010
  41
  42 #define CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL      0x00030035
  43
  44 #define CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT  0x00001067
  45
  46 #define CONFIG_SYS_MMDC_CORE_REFRESH_CTL        0x103e8000
  47
  48 #define START_REFRESH                           0x00000001
  49
  50 /* MMDC Core Special Command Register (MDSCR) */
  51 #define CMD_ADDR_MSB_MR_OP(x)   (x << 24)
  52
  53 #define  CMD_ADDR_LSB_MR_ADDR(x)    (x << 16)
  54
  55 #define DISABLE_CFG_REQ         0x0
  56 #define CONFIGURATION_REQ       (0x1  << 15)
  57 #define WL_EN                   (0x1  << 9)
  58
  59 #define CMD_NORMAL              (0x0 << 4)
  60 #define CMD_PRECHARGE           (0x1 << 4)
  61 #define CMD_AUTO_REFRESH        (0x2 << 4)
  62 #define CMD_LOAD_MODE_REG       (0x3 << 4)
  63 #define CMD_ZQ_CALIBRATION      (0x4 << 4)
  64 #define CMD_PRECHARGE_BANK_OPEN (0x5 << 4)
  65 #define CMD_MRR                 (0x6 << 4)
  66
  67 #define CMD_BANK_ADDR_0         0x0
  68 #define CMD_BANK_ADDR_1         0x1
  69 #define CMD_BANK_ADDR_2         0x2
  70 #define CMD_BANK_ADDR_3         0x3
  71 #define CMD_BANK_ADDR_4         0x4
  72 #define CMD_BANK_ADDR_5         0x5
  73 #define CMD_BANK_ADDR_6         0x6
  74 #define CMD_BANK_ADDR_7         0x7
  75
  76 /* MMDC Registers */
  77 struct mmdc_p_regs {
  78         u32 mdctl;
  79         u32 mdpdc;
  80         u32 mdotc;
  81         u32 mdcfg0;
  82         u32 mdcfg1;
  83         u32 mdcfg2;
  84         u32 mdmisc;
  85         u32 mdscr;
  86         u32 mdref;
  87         u32 res1[2];
  88         u32 mdrwd;
  89         u32 mdor;
  90         u32 mdmrr;
  91         u32 mdcfg3lp;
  92         u32 mdmr4;
  93         u32 mdasp;
  94         u32 res2[239];
  95         u32 maarcr;
  96         u32 mapsr;
  97         u32 maexidr0;
  98         u32 maexidr1;
  99         u32 madpcr0;
 100         u32 madpcr1;
 101         u32 madpsr0;
 102         u32 madpsr1;
 103         u32 madpsr2;
 104         u32 madpsr3;
 105         u32 madpsr4;
 106         u32 madpsr5;
 107         u32 masbs0;
 108         u32 masbs1;
 109         u32 res3[2];
 110         u32 magenp;
 111         u32 res4[239];
 112         u32 mpzqhwctrl;
 113         u32 mpzqswctrl;
 114         u32 mpwlgcr;
 115         u32 mpwldectrl0;
 116         u32 mpwldectrl1;
 117         u32 mpwldlst;
 118         u32 mpodtctrl;
 119         u32 mprddqby0dl;
 120         u32 mprddqby1dl;
 121         u32 mprddqby2dl;
 122         u32 mprddqby3dl;
 123         u32 res5[4];
 124         u32 mpdgctrl0;
 125         u32 mpdgctrl1;
 126         u32 mpdgdlst0;
 127         u32 mprddlctl;
 128         u32 mprddlst;
 129         u32 mpwrdlctl;
 130         u32 mpwrdlst;
 131         u32 mpsdctrl;
 132         u32 mpzqlp2ctl;
 133         u32 mprddlhwctl;
 134         u32 mpwrdlhwctl;
 135         u32 mprddlhwst0;
 136         u32 mprddlhwst1;
 137         u32 mpwrdlhwst0;
 138         u32 mpwrdlhwst1;
 139         u32 mpwlhwerr;
 140         u32 mpdghwst0;
 141         u32 mpdghwst1;
 142         u32 mpdghwst2;
 143         u32 mpdghwst3;
 144         u32 mppdcmpr1;
 145         u32 mppdcmpr2;
 146         u32 mpswdar0;
 147         u32 mpswdrdr0;
 148         u32 mpswdrdr1;
 149         u32 mpswdrdr2;
 150         u32 mpswdrdr3;
 151         u32 mpswdrdr4;
 152         u32 mpswdrdr5;
 153         u32 mpswdrdr6;
 154         u32 mpswdrdr7;
 155         u32 mpmur0;
 156         u32 mpwrcadl;
 157         u32 mpdccr;
 158 };
 159
 160 #endif /* FSL_MMDC_H */