include/fsl_usb.h

   1 /*
   2  * Freescale USB Controller
   3  *
   4  * Copyright 2013 Freescale Semiconductor, Inc.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef _ASM_FSL_USB_H_
  10 #define _ASM_FSL_USB_H_
  11
  12 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
  13 struct ccsr_usb_port_ctrl {
  14         u32     ctrl;
  15         u32     drvvbuscfg;
  16         u32     pwrfltcfg;
  17         u32     sts;
  18         u8      res_14[0xc];
  19         u32     bistcfg;
  20         u32     biststs;
  21         u32     abistcfg;
  22         u32     abiststs;
  23         u8      res_30[0x10];
  24         u32     xcvrprg;
  25         u32     anaprg;
  26         u32     anadrv;
  27         u32     anasts;
  28 };
  29
  30 struct ccsr_usb_phy {
  31         u32     id;
  32         struct ccsr_usb_port_ctrl port1;
  33         u8      res_50[0xc];
  34         u32     tvr;
  35         u32     pllprg[4];
  36         u8      res_70[0x4];
  37         u32     anaccfg;
  38         u32     dbg;
  39         u8      res_7c[0x4];
  40         struct ccsr_usb_port_ctrl port2;
  41         u8      res_dc[0x334];
  42 };
  43
  44 #define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0)
  45 #define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1)
  46 #define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1)
  47 #define CONFIG_SYS_FSL_USB_PLLPRG1_PHY_DIV (1 << 0)
  48 #define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0)
  49 #define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1)
  50 #define CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN (1 << 13)
  51 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
  52 #define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK (5 << 4)
  53 #define CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK (6 << 16)
  54 #define CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN (1 << 20)
  55 #endif
  56 #define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV (1 << 4)
  57 #define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
  58 #define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
  59 #define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0)
  60 #define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN (1 << 7)
  61 #define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK (3 << 4)
  62
  63 #define INC_DCNT_THRESHOLD_25MV        (0 << 4)
  64 #define INC_DCNT_THRESHOLD_50MV        (1 << 4)
  65 #define DEC_DCNT_THRESHOLD_25MV        (2 << 4)
  66 #define DEC_DCNT_THRESHOLD_50MV        (3 << 4)
  67 #else
  68 struct ccsr_usb_phy {
  69         u32     config1;
  70         u32     config2;
  71         u32     config3;
  72         u32     config4;
  73         u32     config5;
  74         u32     status1;
  75         u32     usb_enable_override;
  76         u8      res[0xe4];
  77 };
  78 #define CONFIG_SYS_FSL_USB_HS_DISCNCT_INC (3 << 22)
  79 #define CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL (1 << 20)
  80 #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0 13
  81 #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3 16
  82 #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0 0
  83 #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3 3
  84 #define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
  85 #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK 0x07
  86 #endif
  87
  88 /* USB Erratum Checking code */
  89 #if defined(CONFIG_PPC) || defined(CONFIG_ARM)
  90 bool has_dual_phy(void);
  91 bool has_erratum_a006261(void);
  92 bool has_erratum_a007075(void);
  93 bool has_erratum_a007798(void);
  94 bool has_erratum_a007792(void);
  95 bool has_erratum_a005697(void);
  96 bool has_erratum_a004477(void);
  97 bool has_erratum_a008751(void);
  98 bool has_erratum_a010151(void);
  99 #endif
 100 #endif /*_ASM_FSL_USB_H_ */