include/gdsys_fpga.h

   1 /*
   2  * (C) Copyright 2010
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __GDSYS_FPGA_H
   9 #define __GDSYS_FPGA_H
  10
  11 int init_func_fpga(void);
  12
  13 enum {
  14         FPGA_STATE_DONE_FAILED = 1 << 0,
  15         FPGA_STATE_REFLECTION_FAILED = 1 << 1,
  16         FPGA_STATE_PLATFORM = 1 << 2,
  17 };
  18
  19 int get_fpga_state(unsigned dev);
  20
  21 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data);
  22 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data);
  23
  24 extern struct ihs_fpga *fpga_ptr[];
  25
  26 #define FPGA_SET_REG(ix, fld, val) \
  27         fpga_set_reg((ix), \
  28                      &fpga_ptr[ix]->fld, \
  29                      offsetof(struct ihs_fpga, fld), \
  30                      val)
  31
  32 #define FPGA_GET_REG(ix, fld, val) \
  33         fpga_get_reg((ix), \
  34                      &fpga_ptr[ix]->fld, \
  35                      offsetof(struct ihs_fpga, fld), \
  36                      val)
  37
  38 struct ihs_gpio {
  39         u16 read;
  40         u16 clear;
  41         u16 set;
  42 };
  43
  44 struct ihs_i2c {
  45         u16 interrupt_status;
  46         u16 interrupt_enable;
  47         u16 write_mailbox_ext;
  48         u16 write_mailbox;
  49         u16 read_mailbox_ext;
  50         u16 read_mailbox;
  51 };
  52
  53 struct ihs_osd {
  54         u16 version;
  55         u16 features;
  56         u16 control;
  57         u16 xy_size;
  58         u16 xy_scale;
  59         u16 x_pos;
  60         u16 y_pos;
  61 };
  62
  63 struct ihs_mdio {
  64         u16 control;
  65         u16 address_data;
  66         u16 rx_data;
  67 };
  68
  69 struct ihs_io_ep {
  70         u16 transmit_data;
  71         u16 rx_tx_control;
  72         u16 receive_data;
  73         u16 rx_tx_status;
  74         u16 reserved;
  75         u16 device_address;
  76         u16 target_address;
  77 };
  78
  79 #ifdef CONFIG_NEO
  80 struct ihs_fpga {
  81         u16 reflection_low;     /* 0x0000 */
  82         u16 versions;           /* 0x0002 */
  83         u16 fpga_features;      /* 0x0004 */
  84         u16 fpga_version;       /* 0x0006 */
  85         u16 reserved_0[8187];   /* 0x0008 */
  86         u16 reflection_high;    /* 0x3ffe */
  87 };
  88 #endif
  89
  90 #ifdef CONFIG_IO
  91 struct ihs_fpga {
  92         u16 reflection_low;     /* 0x0000 */
  93         u16 versions;           /* 0x0002 */
  94         u16 fpga_features;      /* 0x0004 */
  95         u16 fpga_version;       /* 0x0006 */
  96         u16 reserved_0[5];      /* 0x0008 */
  97         u16 quad_serdes_reset;  /* 0x0012 */
  98         u16 reserved_1[8181];   /* 0x0014 */
  99         u16 reflection_high;    /* 0x3ffe */
 100 };
 101 #endif
 102
 103 #ifdef CONFIG_IO64
 104 struct ihs_fpga_channel {
 105         u16 status_int;
 106         u16 config_int;
 107         u16 switch_connect_config;
 108         u16 tx_destination;
 109 };
 110
 111 struct ihs_fpga_hicb {
 112         u16 status_int;
 113         u16 config_int;
 114 };
 115
 116 struct ihs_fpga {
 117         u16 reflection_low;     /* 0x0000 */
 118         u16 versions;           /* 0x0002 */
 119         u16 fpga_features;      /* 0x0004 */
 120         u16 fpga_version;       /* 0x0006 */
 121         u16 reserved_0[5];      /* 0x0008 */
 122         u16 quad_serdes_reset;  /* 0x0012 */
 123         u16 reserved_1[502];    /* 0x0014 */
 124         struct ihs_fpga_channel ch[32];         /* 0x0400 */
 125         struct ihs_fpga_channel hicb_ch[32];    /* 0x0500 */
 126         u16 reserved_2[7487];   /* 0x0580 */
 127         u16 reflection_high;    /* 0x3ffe */
 128 };
 129 #endif
 130
 131 #ifdef CONFIG_IOCON
 132 struct ihs_fpga {
 133         u16 reflection_low;     /* 0x0000 */
 134         u16 versions;           /* 0x0002 */
 135         u16 fpga_version;       /* 0x0004 */
 136         u16 fpga_features;      /* 0x0006 */
 137         u16 reserved_0[1];      /* 0x0008 */
 138         u16 top_interrupt;      /* 0x000a */
 139         u16 reserved_1[4];      /* 0x000c */
 140         struct ihs_gpio gpio;   /* 0x0014 */
 141         u16 mpc3w_control;      /* 0x001a */
 142         u16 reserved_2[2];      /* 0x001c */
 143         struct ihs_io_ep ep;    /* 0x0020 */
 144         u16 reserved_3[9];      /* 0x002e */
 145         struct ihs_i2c i2c0;    /* 0x0040 */
 146         u16 reserved_4[10];     /* 0x004c */
 147         u16 mc_int;             /* 0x0060 */
 148         u16 mc_int_en;          /* 0x0062 */
 149         u16 mc_status;          /* 0x0064 */
 150         u16 mc_control;         /* 0x0066 */
 151         u16 mc_tx_data;         /* 0x0068 */
 152         u16 mc_tx_address;      /* 0x006a */
 153         u16 mc_tx_cmd;          /* 0x006c */
 154         u16 mc_res;             /* 0x006e */
 155         u16 mc_rx_cmd_status;   /* 0x0070 */
 156         u16 mc_rx_data;         /* 0x0072 */
 157         u16 reserved_5[69];     /* 0x0074 */
 158         u16 reflection_high;    /* 0x00fe */
 159         struct ihs_osd osd0;    /* 0x0100 */
 160         u16 reserved_6[889];    /* 0x010e */
 161         u16 videomem0[2048];    /* 0x0800 */
 162 };
 163 #endif
 164
 165 #if defined(CONFIG_HRCON) || defined(CONFIG_STRIDER_CON_DP)
 166 struct ihs_fpga {
 167         u16 reflection_low;     /* 0x0000 */
 168         u16 versions;           /* 0x0002 */
 169         u16 fpga_version;       /* 0x0004 */
 170         u16 fpga_features;      /* 0x0006 */
 171         u16 reserved_0[1];      /* 0x0008 */
 172         u16 top_interrupt;      /* 0x000a */
 173         u16 reserved_1[2];      /* 0x000c */
 174         u16 control;            /* 0x0010 */
 175         u16 extended_control;   /* 0x0012 */
 176         struct ihs_gpio gpio;   /* 0x0014 */
 177         u16 mpc3w_control;      /* 0x001a */
 178         u16 reserved_2[2];      /* 0x001c */
 179         struct ihs_io_ep ep;    /* 0x0020 */
 180         u16 reserved_3[9];      /* 0x002e */
 181         struct ihs_i2c i2c0;    /* 0x0040 */
 182         u16 reserved_4[10];     /* 0x004c */
 183         u16 mc_int;             /* 0x0060 */
 184         u16 mc_int_en;          /* 0x0062 */
 185         u16 mc_status;          /* 0x0064 */
 186         u16 mc_control;         /* 0x0066 */
 187         u16 mc_tx_data;         /* 0x0068 */
 188         u16 mc_tx_address;      /* 0x006a */
 189         u16 mc_tx_cmd;          /* 0x006c */
 190         u16 mc_res;             /* 0x006e */
 191         u16 mc_rx_cmd_status;   /* 0x0070 */
 192         u16 mc_rx_data;         /* 0x0072 */
 193         u16 reserved_5[69];     /* 0x0074 */
 194         u16 reflection_high;    /* 0x00fe */
 195         struct ihs_osd osd0;    /* 0x0100 */
 196 #ifdef CONFIG_SYS_OSD_DH
 197         u16 reserved_6[57];     /* 0x010e */
 198         struct ihs_osd osd1;    /* 0x0180 */
 199         u16 reserved_7[9];      /* 0x018e */
 200         struct ihs_i2c i2c1;    /* 0x01a0 */
 201         u16 reserved_8[1834];   /* 0x01ac */
 202         u16 videomem0[2048];    /* 0x1000 */
 203         u16 videomem1[2048];    /* 0x2000 */
 204 #else
 205         u16 reserved_6[889];    /* 0x010e */
 206         u16 videomem0[2048];    /* 0x0800 */
 207 #endif
 208 };
 209 #endif
 210
 211 #ifdef CONFIG_STRIDER_CPU
 212 struct ihs_fpga {
 213         u16 reflection_low;     /* 0x0000 */
 214         u16 versions;           /* 0x0002 */
 215         u16 fpga_version;       /* 0x0004 */
 216         u16 fpga_features;      /* 0x0006 */
 217         u16 reserved_0[1];      /* 0x0008 */
 218         u16 top_interrupt;      /* 0x000a */
 219         u16 reserved_1[3];      /* 0x000c */
 220         u16 extended_control;   /* 0x0012 */
 221         struct ihs_gpio gpio;   /* 0x0014 */
 222         u16 mpc3w_control;      /* 0x001a */
 223         u16 reserved_2[2];      /* 0x001c */
 224         struct ihs_io_ep ep;    /* 0x0020 */
 225         u16 reserved_3[9];      /* 0x002e */
 226         u16 mc_int;             /* 0x0040 */
 227         u16 mc_int_en;          /* 0x0042 */
 228         u16 mc_status;          /* 0x0044 */
 229         u16 mc_control;         /* 0x0046 */
 230         u16 mc_tx_data;         /* 0x0048 */
 231         u16 mc_tx_address;      /* 0x004a */
 232         u16 mc_tx_cmd;          /* 0x004c */
 233         u16 mc_res;             /* 0x004e */
 234         u16 mc_rx_cmd_status;   /* 0x0050 */
 235         u16 mc_rx_data;         /* 0x0052 */
 236         u16 reserved_4[62];     /* 0x0054 */
 237         struct ihs_i2c i2c0;    /* 0x00d0 */
 238 };
 239 #endif
 240
 241 #ifdef CONFIG_STRIDER_CON
 242 struct ihs_fpga {
 243         u16 reflection_low;     /* 0x0000 */
 244         u16 versions;           /* 0x0002 */
 245         u16 fpga_version;       /* 0x0004 */
 246         u16 fpga_features;      /* 0x0006 */
 247         u16 reserved_0[1];      /* 0x0008 */
 248         u16 top_interrupt;      /* 0x000a */
 249         u16 reserved_1[4];      /* 0x000c */
 250         struct ihs_gpio gpio;   /* 0x0014 */
 251         u16 mpc3w_control;      /* 0x001a */
 252         u16 reserved_2[2];      /* 0x001c */
 253         struct ihs_io_ep ep;    /* 0x0020 */
 254         u16 reserved_3[9];      /* 0x002e */
 255         struct ihs_i2c i2c0;    /* 0x0040 */
 256         u16 reserved_4[10];     /* 0x004c */
 257         u16 mc_int;             /* 0x0060 */
 258         u16 mc_int_en;          /* 0x0062 */
 259         u16 mc_status;          /* 0x0064 */
 260         u16 mc_control;         /* 0x0066 */
 261         u16 mc_tx_data;         /* 0x0068 */
 262         u16 mc_tx_address;      /* 0x006a */
 263         u16 mc_tx_cmd;          /* 0x006c */
 264         u16 mc_res;             /* 0x006e */
 265         u16 mc_rx_cmd_status;   /* 0x0070 */
 266         u16 mc_rx_data;         /* 0x0072 */
 267         u16 reserved_5[70];     /* 0x0074 */
 268         struct ihs_osd osd0;    /* 0x0100 */
 269         u16 reserved_6[889];    /* 0x010e */
 270         u16 videomem0[2048];    /* 0x0800 */
 271 };
 272 #endif
 273
 274 #ifdef CONFIG_DLVISION_10G
 275 struct ihs_fpga {
 276         u16 reflection_low;     /* 0x0000 */
 277         u16 versions;           /* 0x0002 */
 278         u16 fpga_version;       /* 0x0004 */
 279         u16 fpga_features;      /* 0x0006 */
 280         u16 reserved_0[10];     /* 0x0008 */
 281         u16 extended_interrupt; /* 0x001c */
 282         u16 reserved_1[29];     /* 0x001e */
 283         u16 mpc3w_control;      /* 0x0058 */
 284         u16 reserved_2[3];      /* 0x005a */
 285         struct ihs_i2c i2c0;    /* 0x0060 */
 286         u16 reserved_3[2];      /* 0x006c */
 287         struct ihs_i2c i2c1;    /* 0x0070 */
 288         u16 reserved_4[194];    /* 0x007c */
 289         struct ihs_osd osd0;    /* 0x0200 */
 290         u16 reserved_5[761];    /* 0x020e */
 291         u16 videomem0[2048];    /* 0x0800 */
 292 };
 293 #endif
 294
 295 #endif