include/linux/mtd/nand.h

   1 /*
   2  *  linux/include/linux/mtd/nand.h
   3  *
   4  *  Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
   5  *                     Steven J. Hill <sjhill@realitydiluted.com>
   6  *                     Thomas Gleixner <tglx@linutronix.de>
   7  *
   8  * $Id: nand.h,v 1.74 2005/09/15 13:58:50 vwool Exp $
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * Info:
  15  *      Contains standard defines and IDs for NAND flash devices
  16  *
  17  * Changelog:
  18  *      See git changelog.
  19  */
  20 #ifndef __LINUX_MTD_NAND_H
  21 #define __LINUX_MTD_NAND_H
  22
  23 /* XXX U-BOOT XXX */
  24 #if 0
  25 #include <linux/wait.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/mtd/mtd.h>
  28 #endif
  29
  30 #include "config.h"
  31
  32 #include "linux/mtd/compat.h"
  33 #include "linux/mtd/mtd.h"
  34
  35
  36 struct mtd_info;
  37 /* Scan and identify a NAND device */
  38 extern int nand_scan (struct mtd_info *mtd, int max_chips);
  39 /* Separate phases of nand_scan(), allowing board driver to intervene
  40  * and override command or ECC setup according to flash type */
  41 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips);
  42 extern int nand_scan_tail(struct mtd_info *mtd);
  43
  44 /* Free resources held by the NAND device */
  45 extern void nand_release (struct mtd_info *mtd);
  46
  47 /* Internal helper for board drivers which need to override command function */
  48 extern void nand_wait_ready(struct mtd_info *mtd);
  49
  50 /* The maximum number of NAND chips in an array */
  51 #ifndef NAND_MAX_CHIPS
  52 #define NAND_MAX_CHIPS          8
  53 #endif
  54
  55 /* This constant declares the max. oobsize / page, which
  56  * is supported now. If you add a chip with bigger oobsize/page
  57  * adjust this accordingly.
  58  */
  59 #define NAND_MAX_OOBSIZE        128
  60 #define NAND_MAX_PAGESIZE       4096
  61
  62 /*
  63  * Constants for hardware specific CLE/ALE/NCE function
  64  *
  65  * These are bits which can be or'ed to set/clear multiple
  66  * bits in one go.
  67  */
  68 /* Select the chip by setting nCE to low */
  69 #define NAND_NCE                0x01
  70 /* Select the command latch by setting CLE to high */
  71 #define NAND_CLE                0x02
  72 /* Select the address latch by setting ALE to high */
  73 #define NAND_ALE                0x04
  74
  75 #define NAND_CTRL_CLE           (NAND_NCE | NAND_CLE)
  76 #define NAND_CTRL_ALE           (NAND_NCE | NAND_ALE)
  77 #define NAND_CTRL_CHANGE        0x80
  78
  79 /*
  80  * Standard NAND flash commands
  81  */
  82 #define NAND_CMD_READ0          0
  83 #define NAND_CMD_READ1          1
  84 #define NAND_CMD_RNDOUT         5
  85 #define NAND_CMD_PAGEPROG       0x10
  86 #define NAND_CMD_READOOB        0x50
  87 #define NAND_CMD_ERASE1         0x60
  88 #define NAND_CMD_STATUS         0x70
  89 #define NAND_CMD_STATUS_MULTI   0x71
  90 #define NAND_CMD_SEQIN          0x80
  91 #define NAND_CMD_RNDIN          0x85
  92 #define NAND_CMD_READID         0x90
  93 #define NAND_CMD_ERASE2         0xd0
  94 #define NAND_CMD_RESET          0xff
  95
  96 /* Extended commands for large page devices */
  97 #define NAND_CMD_READSTART      0x30
  98 #define NAND_CMD_RNDOUTSTART    0xE0
  99 #define NAND_CMD_CACHEDPROG     0x15
 100
 101 /* Extended commands for AG-AND device */
 102 /*
 103  * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
 104  *       there is no way to distinguish that from NAND_CMD_READ0
 105  *       until the remaining sequence of commands has been completed
 106  *       so add a high order bit and mask it off in the command.
 107  */
 108 #define NAND_CMD_DEPLETE1       0x100
 109 #define NAND_CMD_DEPLETE2       0x38
 110 #define NAND_CMD_STATUS_MULTI   0x71
 111 #define NAND_CMD_STATUS_ERROR   0x72
 112 /* multi-bank error status (banks 0-3) */
 113 #define NAND_CMD_STATUS_ERROR0  0x73
 114 #define NAND_CMD_STATUS_ERROR1  0x74
 115 #define NAND_CMD_STATUS_ERROR2  0x75
 116 #define NAND_CMD_STATUS_ERROR3  0x76
 117 #define NAND_CMD_STATUS_RESET   0x7f
 118 #define NAND_CMD_STATUS_CLEAR   0xff
 119
 120 #define NAND_CMD_NONE           -1
 121
 122 /* Status bits */
 123 #define NAND_STATUS_FAIL        0x01
 124 #define NAND_STATUS_FAIL_N1     0x02
 125 #define NAND_STATUS_TRUE_READY  0x20
 126 #define NAND_STATUS_READY       0x40
 127 #define NAND_STATUS_WP          0x80
 128
 129 /*
 130  * Constants for ECC_MODES
 131  */
 132 typedef enum {
 133         NAND_ECC_NONE,
 134         NAND_ECC_SOFT,
 135         NAND_ECC_HW,
 136         NAND_ECC_HW_SYNDROME,
 137 } nand_ecc_modes_t;
 138
 139 /*
 140  * Constants for Hardware ECC
 141  */
 142 /* Reset Hardware ECC for read */
 143 #define NAND_ECC_READ           0
 144 /* Reset Hardware ECC for write */
 145 #define NAND_ECC_WRITE          1
 146 /* Enable Hardware ECC before syndrom is read back from flash */
 147 #define NAND_ECC_READSYN        2
 148
 149 /* Bit mask for flags passed to do_nand_read_ecc */
 150 #define NAND_GET_DEVICE         0x80
 151
 152
 153 /* Option constants for bizarre disfunctionality and real
 154 *  features
 155 */
 156 /* Chip can not auto increment pages */
 157 #define NAND_NO_AUTOINCR        0x00000001
 158 /* Buswitdh is 16 bit */
 159 #define NAND_BUSWIDTH_16        0x00000002
 160 /* Device supports partial programming without padding */
 161 #define NAND_NO_PADDING         0x00000004
 162 /* Chip has cache program function */
 163 #define NAND_CACHEPRG           0x00000008
 164 /* Chip has copy back function */
 165 #define NAND_COPYBACK           0x00000010
 166 /* AND Chip which has 4 banks and a confusing page / block
 167  * assignment. See Renesas datasheet for further information */
 168 #define NAND_IS_AND             0x00000020
 169 /* Chip has a array of 4 pages which can be read without
 170  * additional ready /busy waits */
 171 #define NAND_4PAGE_ARRAY        0x00000040
 172 /* Chip requires that BBT is periodically rewritten to prevent
 173  * bits from adjacent blocks from 'leaking' in altering data.
 174  * This happens with the Renesas AG-AND chips, possibly others.  */
 175 #define BBT_AUTO_REFRESH        0x00000080
 176 /* Chip does not require ready check on read. True
 177  * for all large page devices, as they do not support
 178  * autoincrement.*/
 179 #define NAND_NO_READRDY         0x00000100
 180 /* Chip does not allow subpage writes */
 181 #define NAND_NO_SUBPAGE_WRITE   0x00000200
 182
 183
 184 /* Options valid for Samsung large page devices */
 185 #define NAND_SAMSUNG_LP_OPTIONS \
 186         (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
 187
 188 /* Macros to identify the above */
 189 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
 190 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
 191 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
 192 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
 193
 194 /* Mask to zero out the chip options, which come from the id table */
 195 #define NAND_CHIPOPTIONS_MSK    (0x0000ffff & ~NAND_NO_AUTOINCR)
 196
 197 /* Non chip related options */
 198 /* Use a flash based bad block table. This option is passed to the
 199  * default bad block table function. */
 200 #define NAND_USE_FLASH_BBT      0x00010000
 201 /* This option skips the bbt scan during initialization. */
 202 #define NAND_SKIP_BBTSCAN       0x00020000
 203 /* This option is defined if the board driver allocates its own buffers
 204    (e.g. because it needs them DMA-coherent */
 205 #define NAND_OWN_BUFFERS        0x00040000
 206 /* Options set by nand scan */
 207 /* bbt has already been read */
 208 #define NAND_BBT_SCANNED        0x40000000
 209 /* Nand scan has allocated controller struct */
 210 #define NAND_CONTROLLER_ALLOC   0x80000000
 211
 212 /* Cell info constants */
 213 #define NAND_CI_CHIPNR_MSK      0x03
 214 #define NAND_CI_CELLTYPE_MSK    0x0C
 215
 216 /* Keep gcc happy */
 217 struct nand_chip;
 218
 219 /**
 220  * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
 221  * @lock:               protection lock
 222  * @active:             the mtd device which holds the controller currently
 223  * @wq:                 wait queue to sleep on if a NAND operation is in progress
 224  *                      used instead of the per chip wait queue when a hw controller is available
 225  */
 226 struct nand_hw_control {
 227 /* XXX U-BOOT XXX */
 228 #if 0
 229         spinlock_t       lock;
 230         wait_queue_head_t wq;
 231 #endif
 232         struct nand_chip *active;
 233 };
 234
 235 /**
 236  * struct nand_ecc_ctrl - Control structure for ecc
 237  * @mode:       ecc mode
 238  * @steps:      number of ecc steps per page
 239  * @size:       data bytes per ecc step
 240  * @bytes:      ecc bytes per step
 241  * @total:      total number of ecc bytes per page
 242  * @prepad:     padding information for syndrome based ecc generators
 243  * @postpad:    padding information for syndrome based ecc generators
 244  * @layout:     ECC layout control struct pointer
 245  * @hwctl:      function to control hardware ecc generator. Must only
 246  *              be provided if an hardware ECC is available
 247  * @calculate:  function for ecc calculation or readback from ecc hardware
 248  * @correct:    function for ecc correction, matching to ecc generator (sw/hw)
 249  * @read_page_raw:      function to read a raw page without ECC
 250  * @write_page_raw:     function to write a raw page without ECC
 251  * @read_page:  function to read a page according to the ecc generator requirements
 252  * @write_page: function to write a page according to the ecc generator requirements
 253  * @read_oob:   function to read chip OOB data
 254  * @write_oob:  function to write chip OOB data
 255  */
 256 struct nand_ecc_ctrl {
 257         nand_ecc_modes_t        mode;
 258         int                     steps;
 259         int                     size;
 260         int                     bytes;
 261         int                     total;
 262         int                     prepad;
 263         int                     postpad;
 264         struct nand_ecclayout   *layout;
 265         void                    (*hwctl)(struct mtd_info *mtd, int mode);
 266         int                     (*calculate)(struct mtd_info *mtd,
 267                                              const uint8_t *dat,
 268                                              uint8_t *ecc_code);
 269         int                     (*correct)(struct mtd_info *mtd, uint8_t *dat,
 270                                            uint8_t *read_ecc,
 271                                            uint8_t *calc_ecc);
 272         int                     (*read_page_raw)(struct mtd_info *mtd,
 273                                                  struct nand_chip *chip,
 274                                                  uint8_t *buf);
 275         void                    (*write_page_raw)(struct mtd_info *mtd,
 276                                                   struct nand_chip *chip,
 277                                                   const uint8_t *buf);
 278         int                     (*read_page)(struct mtd_info *mtd,
 279                                              struct nand_chip *chip,
 280                                              uint8_t *buf);
 281         void                    (*write_page)(struct mtd_info *mtd,
 282                                               struct nand_chip *chip,
 283                                               const uint8_t *buf);
 284         int                     (*read_oob)(struct mtd_info *mtd,
 285                                             struct nand_chip *chip,
 286                                             int page,
 287                                             int sndcmd);
 288         int                     (*write_oob)(struct mtd_info *mtd,
 289                                              struct nand_chip *chip,
 290                                              int page);
 291 };
 292
 293 /**
 294  * struct nand_buffers - buffer structure for read/write
 295  * @ecccalc:    buffer for calculated ecc
 296  * @ecccode:    buffer for ecc read from flash
 297  * @databuf:    buffer for data - dynamically sized
 298  *
 299  * Do not change the order of buffers. databuf and oobrbuf must be in
 300  * consecutive order.
 301  */
 302 struct nand_buffers {
 303         uint8_t ecccalc[NAND_MAX_OOBSIZE];
 304         uint8_t ecccode[NAND_MAX_OOBSIZE];
 305         uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
 306 };
 307
 308 /**
 309  * struct nand_chip - NAND Private Flash Chip Data
 310  * @IO_ADDR_R:          [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
 311  * @IO_ADDR_W:          [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
 312  * @read_byte:          [REPLACEABLE] read one byte from the chip
 313  * @read_word:          [REPLACEABLE] read one word from the chip
 314  * @write_buf:          [REPLACEABLE] write data from the buffer to the chip
 315  * @read_buf:           [REPLACEABLE] read data from the chip into the buffer
 316  * @verify_buf:         [REPLACEABLE] verify buffer contents against the chip data
 317  * @select_chip:        [REPLACEABLE] select chip nr
 318  * @block_bad:          [REPLACEABLE] check, if the block is bad
 319  * @block_markbad:      [REPLACEABLE] mark the block bad
 320  * @cmd_ctrl:           [BOARDSPECIFIC] hardwarespecific funtion for controlling
 321  *                      ALE/CLE/nCE. Also used to write command and address
 322  * @dev_ready:          [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
 323  *                      If set to NULL no access to ready/busy is available and the ready/busy information
 324  *                      is read from the chip status register
 325  * @cmdfunc:            [REPLACEABLE] hardwarespecific function for writing commands to the chip
 326  * @waitfunc:           [REPLACEABLE] hardwarespecific function for wait on ready
 327  * @ecc:                [BOARDSPECIFIC] ecc control ctructure
 328  * @buffers:            buffer structure for read/write
 329  * @hwcontrol:          platform-specific hardware control structure
 330  * @ops:                oob operation operands
 331  * @erase_cmd:          [INTERN] erase command write function, selectable due to AND support
 332  * @scan_bbt:           [REPLACEABLE] function to scan bad block table
 333  * @chip_delay:         [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
 334  * @wq:                 [INTERN] wait queue to sleep on if a NAND operation is in progress
 335  * @state:              [INTERN] the current state of the NAND device
 336  * @oob_poi:            poison value buffer
 337  * @page_shift:         [INTERN] number of address bits in a page (column address bits)
 338  * @phys_erase_shift:   [INTERN] number of address bits in a physical eraseblock
 339  * @bbt_erase_shift:    [INTERN] number of address bits in a bbt entry
 340  * @chip_shift:         [INTERN] number of address bits in one chip
 341  * @datbuf:             [INTERN] internal buffer for one page + oob
 342  * @oobbuf:             [INTERN] oob buffer for one eraseblock
 343  * @oobdirty:           [INTERN] indicates that oob_buf must be reinitialized
 344  * @data_poi:           [INTERN] pointer to a data buffer
 345  * @options:            [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
 346  *                      special functionality. See the defines for further explanation
 347  * @badblockpos:        [INTERN] position of the bad block marker in the oob area
 348  * @cellinfo:           [INTERN] MLC/multichip data from chip ident
 349  * @numchips:           [INTERN] number of physical chips
 350  * @chipsize:           [INTERN] the size of one chip for multichip arrays
 351  * @pagemask:           [INTERN] page number mask = number of (pages / chip) - 1
 352  * @pagebuf:            [INTERN] holds the pagenumber which is currently in data_buf
 353  * @subpagesize:        [INTERN] holds the subpagesize
 354  * @ecclayout:          [REPLACEABLE] the default ecc placement scheme
 355  * @bbt:                [INTERN] bad block table pointer
 356  * @bbt_td:             [REPLACEABLE] bad block table descriptor for flash lookup
 357  * @bbt_md:             [REPLACEABLE] bad block table mirror descriptor
 358  * @badblock_pattern:   [REPLACEABLE] bad block scan pattern used for initial bad block scan
 359  * @controller:         [REPLACEABLE] a pointer to a hardware controller structure
 360  *                      which is shared among multiple independend devices
 361  * @priv:               [OPTIONAL] pointer to private chip date
 362  * @errstat:            [OPTIONAL] hardware specific function to perform additional error status checks
 363  *                      (determine if errors are correctable)
 364  * @write_page:         [REPLACEABLE] High-level page write function
 365  */
 366
 367 struct nand_chip {
 368         void  __iomem   *IO_ADDR_R;
 369         void  __iomem   *IO_ADDR_W;
 370
 371         uint8_t         (*read_byte)(struct mtd_info *mtd);
 372         u16             (*read_word)(struct mtd_info *mtd);
 373         void            (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 374         void            (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
 375         int             (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 376         void            (*select_chip)(struct mtd_info *mtd, int chip);
 377         int             (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
 378         int             (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
 379         void            (*cmd_ctrl)(struct mtd_info *mtd, int dat,
 380                                     unsigned int ctrl);
 381         int             (*dev_ready)(struct mtd_info *mtd);
 382         void            (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
 383         int             (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
 384         void            (*erase_cmd)(struct mtd_info *mtd, int page);
 385         int             (*scan_bbt)(struct mtd_info *mtd);
 386         int             (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
 387         int             (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
 388                                       const uint8_t *buf, int page, int cached, int raw);
 389
 390         int             chip_delay;
 391         unsigned int    options;
 392
 393         int             page_shift;
 394         int             phys_erase_shift;
 395         int             bbt_erase_shift;
 396         int             chip_shift;
 397         int             numchips;
 398         unsigned long   chipsize;
 399         int             pagemask;
 400         int             pagebuf;
 401         int             subpagesize;
 402         uint8_t         cellinfo;
 403         int             badblockpos;
 404
 405         int             state;
 406
 407         uint8_t         *oob_poi;
 408         struct nand_hw_control  *controller;
 409         struct nand_ecclayout   *ecclayout;
 410
 411         struct nand_ecc_ctrl ecc;
 412         struct nand_buffers *buffers;
 413
 414         struct nand_hw_control hwcontrol;
 415
 416         struct mtd_oob_ops ops;
 417
 418         uint8_t         *bbt;
 419         struct nand_bbt_descr   *bbt_td;
 420         struct nand_bbt_descr   *bbt_md;
 421
 422         struct nand_bbt_descr   *badblock_pattern;
 423
 424         void            *priv;
 425 };
 426
 427 /*
 428  * NAND Flash Manufacturer ID Codes
 429  */
 430 #define NAND_MFR_TOSHIBA        0x98
 431 #define NAND_MFR_SAMSUNG        0xec
 432 #define NAND_MFR_FUJITSU        0x04
 433 #define NAND_MFR_NATIONAL       0x8f
 434 #define NAND_MFR_RENESAS        0x07
 435 #define NAND_MFR_STMICRO        0x20
 436 #define NAND_MFR_HYNIX          0xad
 437 #define NAND_MFR_MICRON         0x2c
 438
 439 /**
 440  * struct nand_flash_dev - NAND Flash Device ID Structure
 441  * @name:       Identify the device type
 442  * @id:         device ID code
 443  * @pagesize:   Pagesize in bytes. Either 256 or 512 or 0
 444  *              If the pagesize is 0, then the real pagesize
 445  *              and the eraseize are determined from the
 446  *              extended id bytes in the chip
 447  * @erasesize:  Size of an erase block in the flash device.
 448  * @chipsize:   Total chipsize in Mega Bytes
 449  * @options:    Bitfield to store chip relevant options
 450  */
 451 struct nand_flash_dev {
 452         char *name;
 453         int id;
 454         unsigned long pagesize;
 455         unsigned long chipsize;
 456         unsigned long erasesize;
 457         unsigned long options;
 458 };
 459
 460 /**
 461  * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
 462  * @name:       Manufacturer name
 463  * @id:         manufacturer ID code of device.
 464 */
 465 struct nand_manufacturers {
 466         int id;
 467         char * name;
 468 };
 469
 470 extern struct nand_flash_dev nand_flash_ids[];
 471 extern struct nand_manufacturers nand_manuf_ids[];
 472
 473 #ifndef NAND_MAX_CHIPS
 474 #define NAND_MAX_CHIPS 8
 475 #endif
 476
 477 /**
 478  * struct nand_bbt_descr - bad block table descriptor
 479  * @options:    options for this descriptor
 480  * @pages:      the page(s) where we find the bbt, used with option BBT_ABSPAGE
 481  *              when bbt is searched, then we store the found bbts pages here.
 482  *              Its an array and supports up to 8 chips now
 483  * @offs:       offset of the pattern in the oob area of the page
 484  * @veroffs:    offset of the bbt version counter in the oob are of the page
 485  * @version:    version read from the bbt page during scan
 486  * @len:        length of the pattern, if 0 no pattern check is performed
 487  * @maxblocks:  maximum number of blocks to search for a bbt. This number of
 488  *              blocks is reserved at the end of the device where the tables are
 489  *              written.
 490  * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
 491  *              bad) block in the stored bbt
 492  * @pattern:    pattern to identify bad block table or factory marked good /
 493  *              bad blocks, can be NULL, if len = 0
 494  *
 495  * Descriptor for the bad block table marker and the descriptor for the
 496  * pattern which identifies good and bad blocks. The assumption is made
 497  * that the pattern and the version count are always located in the oob area
 498  * of the first block.
 499  */
 500 struct nand_bbt_descr {
 501         int     options;
 502         int     pages[NAND_MAX_CHIPS];
 503         int     offs;
 504         int     veroffs;
 505         uint8_t version[NAND_MAX_CHIPS];
 506         int     len;
 507         int     maxblocks;
 508         int     reserved_block_code;
 509         uint8_t *pattern;
 510 };
 511
 512 /* Options for the bad block table descriptors */
 513
 514 /* The number of bits used per block in the bbt on the device */
 515 #define NAND_BBT_NRBITS_MSK     0x0000000F
 516 #define NAND_BBT_1BIT           0x00000001
 517 #define NAND_BBT_2BIT           0x00000002
 518 #define NAND_BBT_4BIT           0x00000004
 519 #define NAND_BBT_8BIT           0x00000008
 520 /* The bad block table is in the last good block of the device */
 521 #define NAND_BBT_LASTBLOCK      0x00000010
 522 /* The bbt is at the given page, else we must scan for the bbt */
 523 #define NAND_BBT_ABSPAGE        0x00000020
 524 /* The bbt is at the given page, else we must scan for the bbt */
 525 #define NAND_BBT_SEARCH         0x00000040
 526 /* bbt is stored per chip on multichip devices */
 527 #define NAND_BBT_PERCHIP        0x00000080
 528 /* bbt has a version counter at offset veroffs */
 529 #define NAND_BBT_VERSION        0x00000100
 530 /* Create a bbt if none axists */
 531 #define NAND_BBT_CREATE         0x00000200
 532 /* Search good / bad pattern through all pages of a block */
 533 #define NAND_BBT_SCANALLPAGES   0x00000400
 534 /* Scan block empty during good / bad block scan */
 535 #define NAND_BBT_SCANEMPTY      0x00000800
 536 /* Write bbt if neccecary */
 537 #define NAND_BBT_WRITE          0x00001000
 538 /* Read and write back block contents when writing bbt */
 539 #define NAND_BBT_SAVECONTENT    0x00002000
 540 /* Search good / bad pattern on the first and the second page */
 541 #define NAND_BBT_SCAN2NDPAGE    0x00004000
 542
 543 /* The maximum number of blocks to scan for a bbt */
 544 #define NAND_BBT_SCAN_MAXBLOCKS 4
 545
 546 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
 547 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
 548 extern int nand_default_bbt(struct mtd_info *mtd);
 549 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
 550 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 551                            int allowbbt);
 552 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
 553                         size_t * retlen, uint8_t * buf);
 554
 555 /*
 556 * Constants for oob configuration
 557 */
 558 #define NAND_SMALL_BADBLOCK_POS         5
 559 #define NAND_LARGE_BADBLOCK_POS         0
 560
 561 /**
 562  * struct platform_nand_chip - chip level device structure
 563  * @nr_chips:           max. number of chips to scan for
 564  * @chip_offset:        chip number offset
 565  * @nr_partitions:      number of partitions pointed to by partitions (or zero)
 566  * @partitions:         mtd partition list
 567  * @chip_delay:         R/B delay value in us
 568  * @options:            Option flags, e.g. 16bit buswidth
 569  * @ecclayout:          ecc layout info structure
 570  * @part_probe_types:   NULL-terminated array of probe types
 571  * @priv:               hardware controller specific settings
 572  */
 573 struct platform_nand_chip {
 574         int                     nr_chips;
 575         int                     chip_offset;
 576         int                     nr_partitions;
 577         struct mtd_partition    *partitions;
 578         struct nand_ecclayout   *ecclayout;
 579         int                     chip_delay;
 580         unsigned int            options;
 581         const char              **part_probe_types;
 582         void                    *priv;
 583 };
 584
 585 /**
 586  * struct platform_nand_ctrl - controller level device structure
 587  * @hwcontrol:          platform specific hardware control structure
 588  * @dev_ready:          platform specific function to read ready/busy pin
 589  * @select_chip:        platform specific chip select function
 590  * @cmd_ctrl:           platform specific function for controlling
 591  *                      ALE/CLE/nCE. Also used to write command and address
 592  * @priv:               private data to transport driver specific settings
 593  *
 594  * All fields are optional and depend on the hardware driver requirements
 595  */
 596 struct platform_nand_ctrl {
 597         void            (*hwcontrol)(struct mtd_info *mtd, int cmd);
 598         int             (*dev_ready)(struct mtd_info *mtd);
 599         void            (*select_chip)(struct mtd_info *mtd, int chip);
 600         void            (*cmd_ctrl)(struct mtd_info *mtd, int dat,
 601                                     unsigned int ctrl);
 602         void            *priv;
 603 };
 604
 605 /**
 606  * struct platform_nand_data - container structure for platform-specific data
 607  * @chip:               chip level chip structure
 608  * @ctrl:               controller level device structure
 609  */
 610 struct platform_nand_data {
 611         struct platform_nand_chip       chip;
 612         struct platform_nand_ctrl       ctrl;
 613 };
 614
 615 /* Some helpers to access the data structures */
 616 static inline
 617 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
 618 {
 619         struct nand_chip *chip = mtd->priv;
 620
 621         return chip->priv;
 622 }
 623
 624 #endif /* __LINUX_MTD_NAND_H */