include/linux/mtd/nand.h

   1 /*
   2  *  linux/include/linux/mtd/nand.h
   3  *
   4  *  Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
   5  *                        Steven J. Hill <sjhill@realitydiluted.com>
   6  *                        Thomas Gleixner <tglx@linutronix.de>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  *
  10  * Info:
  11  *      Contains standard defines and IDs for NAND flash devices
  12  *
  13  * Changelog:
  14  *      See git changelog.
  15  */
  16 #ifndef __LINUX_MTD_NAND_H
  17 #define __LINUX_MTD_NAND_H
  18
  19 #define __UBOOT__
  20 #ifndef __UBOOT__
  21 #include <linux/wait.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/mtd/mtd.h>
  24 #include <linux/mtd/flashchip.h>
  25 #include <linux/mtd/bbm.h>
  26 #else
  27 #include "config.h"
  28
  29 #include "linux/compat.h"
  30 #include "linux/mtd/mtd.h"
  31 #include "linux/mtd/flashchip.h"
  32 #include "linux/mtd/bbm.h"
  33 #endif
  34
  35 struct mtd_info;
  36 struct nand_flash_dev;
  37 /* Scan and identify a NAND device */
  38 extern int nand_scan(struct mtd_info *mtd, int max_chips);
  39 /*
  40  * Separate phases of nand_scan(), allowing board driver to intervene
  41  * and override command or ECC setup according to flash type.
  42  */
  43 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
  44                            struct nand_flash_dev *table);
  45 extern int nand_scan_tail(struct mtd_info *mtd);
  46
  47 /* Free resources held by the NAND device */
  48 extern void nand_release(struct mtd_info *mtd);
  49
  50 /* Internal helper for board drivers which need to override command function */
  51 extern void nand_wait_ready(struct mtd_info *mtd);
  52
  53 #ifndef __UBOOT__
  54 /* locks all blocks present in the device */
  55 extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
  56
  57 /* unlocks specified locked blocks */
  58 extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
  59
  60 /* The maximum number of NAND chips in an array */
  61 #define NAND_MAX_CHIPS          8
  62 #else
  63 /*
  64  * This constant declares the max. oobsize / page, which
  65  * is supported now. If you add a chip with bigger oobsize/page
  66  * adjust this accordingly.
  67  */
  68 #define NAND_MAX_OOBSIZE       744
  69 #define NAND_MAX_PAGESIZE      8192
  70 #endif
  71
  72 /*
  73  * Constants for hardware specific CLE/ALE/NCE function
  74  *
  75  * These are bits which can be or'ed to set/clear multiple
  76  * bits in one go.
  77  */
  78 /* Select the chip by setting nCE to low */
  79 #define NAND_NCE                0x01
  80 /* Select the command latch by setting CLE to high */
  81 #define NAND_CLE                0x02
  82 /* Select the address latch by setting ALE to high */
  83 #define NAND_ALE                0x04
  84
  85 #define NAND_CTRL_CLE           (NAND_NCE | NAND_CLE)
  86 #define NAND_CTRL_ALE           (NAND_NCE | NAND_ALE)
  87 #define NAND_CTRL_CHANGE        0x80
  88
  89 /*
  90  * Standard NAND flash commands
  91  */
  92 #define NAND_CMD_READ0          0
  93 #define NAND_CMD_READ1          1
  94 #define NAND_CMD_RNDOUT         5
  95 #define NAND_CMD_PAGEPROG       0x10
  96 #define NAND_CMD_READOOB        0x50
  97 #define NAND_CMD_ERASE1         0x60
  98 #define NAND_CMD_STATUS         0x70
  99 #define NAND_CMD_SEQIN          0x80
 100 #define NAND_CMD_RNDIN          0x85
 101 #define NAND_CMD_READID         0x90
 102 #define NAND_CMD_ERASE2         0xd0
 103 #define NAND_CMD_PARAM          0xec
 104 #define NAND_CMD_GET_FEATURES   0xee
 105 #define NAND_CMD_SET_FEATURES   0xef
 106 #define NAND_CMD_RESET          0xff
 107
 108 #define NAND_CMD_LOCK           0x2a
 109 #define NAND_CMD_UNLOCK1        0x23
 110 #define NAND_CMD_UNLOCK2        0x24
 111
 112 /* Extended commands for large page devices */
 113 #define NAND_CMD_READSTART      0x30
 114 #define NAND_CMD_RNDOUTSTART    0xE0
 115 #define NAND_CMD_CACHEDPROG     0x15
 116
 117 /* Extended commands for AG-AND device */
 118 /*
 119  * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
 120  *       there is no way to distinguish that from NAND_CMD_READ0
 121  *       until the remaining sequence of commands has been completed
 122  *       so add a high order bit and mask it off in the command.
 123  */
 124 #define NAND_CMD_DEPLETE1       0x100
 125 #define NAND_CMD_DEPLETE2       0x38
 126 #define NAND_CMD_STATUS_MULTI   0x71
 127 #define NAND_CMD_STATUS_ERROR   0x72
 128 /* multi-bank error status (banks 0-3) */
 129 #define NAND_CMD_STATUS_ERROR0  0x73
 130 #define NAND_CMD_STATUS_ERROR1  0x74
 131 #define NAND_CMD_STATUS_ERROR2  0x75
 132 #define NAND_CMD_STATUS_ERROR3  0x76
 133 #define NAND_CMD_STATUS_RESET   0x7f
 134 #define NAND_CMD_STATUS_CLEAR   0xff
 135
 136 #define NAND_CMD_NONE           -1
 137
 138 /* Status bits */
 139 #define NAND_STATUS_FAIL        0x01
 140 #define NAND_STATUS_FAIL_N1     0x02
 141 #define NAND_STATUS_TRUE_READY  0x20
 142 #define NAND_STATUS_READY       0x40
 143 #define NAND_STATUS_WP          0x80
 144
 145 /*
 146  * Constants for ECC_MODES
 147  */
 148 typedef enum {
 149         NAND_ECC_NONE,
 150         NAND_ECC_SOFT,
 151         NAND_ECC_HW,
 152         NAND_ECC_HW_SYNDROME,
 153         NAND_ECC_HW_OOB_FIRST,
 154         NAND_ECC_SOFT_BCH,
 155 } nand_ecc_modes_t;
 156
 157 /*
 158  * Constants for Hardware ECC
 159  */
 160 /* Reset Hardware ECC for read */
 161 #define NAND_ECC_READ           0
 162 /* Reset Hardware ECC for write */
 163 #define NAND_ECC_WRITE          1
 164 /* Enable Hardware ECC before syndrome is read back from flash */
 165 #define NAND_ECC_READSYN        2
 166
 167 /* Bit mask for flags passed to do_nand_read_ecc */
 168 #define NAND_GET_DEVICE         0x80
 169
 170
 171 /*
 172  * Option constants for bizarre disfunctionality and real
 173  * features.
 174  */
 175 /* Buswidth is 16 bit */
 176 #define NAND_BUSWIDTH_16        0x00000002
 177 /* Device supports partial programming without padding */
 178 #define NAND_NO_PADDING         0x00000004
 179 /* Chip has cache program function */
 180 #define NAND_CACHEPRG           0x00000008
 181 /* Chip has copy back function */
 182 #define NAND_COPYBACK           0x00000010
 183 /*
 184  * Chip requires ready check on read (for auto-incremented sequential read).
 185  * True only for small page devices; large page devices do not support
 186  * autoincrement.
 187  */
 188 #define NAND_NEED_READRDY       0x00000100
 189
 190 /* Chip does not allow subpage writes */
 191 #define NAND_NO_SUBPAGE_WRITE   0x00000200
 192
 193 /* Device is one of 'new' xD cards that expose fake nand command set */
 194 #define NAND_BROKEN_XD          0x00000400
 195
 196 /* Device behaves just like nand, but is readonly */
 197 #define NAND_ROM                0x00000800
 198
 199 /* Device supports subpage reads */
 200 #define NAND_SUBPAGE_READ       0x00001000
 201
 202 /* Options valid for Samsung large page devices */
 203 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
 204
 205 /* Macros to identify the above */
 206 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
 207 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
 208
 209 /* Non chip related options */
 210 /* This option skips the bbt scan during initialization. */
 211 #define NAND_SKIP_BBTSCAN       0x00010000
 212 /*
 213  * This option is defined if the board driver allocates its own buffers
 214  * (e.g. because it needs them DMA-coherent).
 215  */
 216 #define NAND_OWN_BUFFERS        0x00020000
 217 /* Chip may not exist, so silence any errors in scan */
 218 #define NAND_SCAN_SILENT_NODEV  0x00040000
 219 /*
 220  * Autodetect nand buswidth with readid/onfi.
 221  * This suppose the driver will configure the hardware in 8 bits mode
 222  * when calling nand_scan_ident, and update its configuration
 223  * before calling nand_scan_tail.
 224  */
 225 #define NAND_BUSWIDTH_AUTO      0x00080000
 226
 227 /* Options set by nand scan */
 228 /* bbt has already been read */
 229 #define NAND_BBT_SCANNED        0x40000000
 230 /* Nand scan has allocated controller struct */
 231 #define NAND_CONTROLLER_ALLOC   0x80000000
 232
 233 /* Cell info constants */
 234 #define NAND_CI_CHIPNR_MSK      0x03
 235 #define NAND_CI_CELLTYPE_MSK    0x0C
 236 #define NAND_CI_CELLTYPE_SHIFT  2
 237
 238 /* Keep gcc happy */
 239 struct nand_chip;
 240
 241 /* ONFI features */
 242 #define ONFI_FEATURE_16_BIT_BUS         (1 << 0)
 243 #define ONFI_FEATURE_EXT_PARAM_PAGE     (1 << 7)
 244
 245 /* ONFI timing mode, used in both asynchronous and synchronous mode */
 246 #define ONFI_TIMING_MODE_0              (1 << 0)
 247 #define ONFI_TIMING_MODE_1              (1 << 1)
 248 #define ONFI_TIMING_MODE_2              (1 << 2)
 249 #define ONFI_TIMING_MODE_3              (1 << 3)
 250 #define ONFI_TIMING_MODE_4              (1 << 4)
 251 #define ONFI_TIMING_MODE_5              (1 << 5)
 252 #define ONFI_TIMING_MODE_UNKNOWN        (1 << 6)
 253
 254 /* ONFI feature address */
 255 #define ONFI_FEATURE_ADDR_TIMING_MODE   0x1
 256
 257 /* Vendor-specific feature address (Micron) */
 258 #define ONFI_FEATURE_ADDR_READ_RETRY    0x89
 259
 260 /* ONFI subfeature parameters length */
 261 #define ONFI_SUBFEATURE_PARAM_LEN       4
 262
 263 /* ONFI optional commands SET/GET FEATURES supported? */
 264 #define ONFI_OPT_CMD_SET_GET_FEATURES   (1 << 2)
 265
 266 struct nand_onfi_params {
 267         /* rev info and features block */
 268         /* 'O' 'N' 'F' 'I'  */
 269         u8 sig[4];
 270         __le16 revision;
 271         __le16 features;
 272         __le16 opt_cmd;
 273         u8 reserved0[2];
 274         __le16 ext_param_page_length; /* since ONFI 2.1 */
 275         u8 num_of_param_pages;        /* since ONFI 2.1 */
 276         u8 reserved1[17];
 277
 278         /* manufacturer information block */
 279         char manufacturer[12];
 280         char model[20];
 281         u8 jedec_id;
 282         __le16 date_code;
 283         u8 reserved2[13];
 284
 285         /* memory organization block */
 286         __le32 byte_per_page;
 287         __le16 spare_bytes_per_page;
 288         __le32 data_bytes_per_ppage;
 289         __le16 spare_bytes_per_ppage;
 290         __le32 pages_per_block;
 291         __le32 blocks_per_lun;
 292         u8 lun_count;
 293         u8 addr_cycles;
 294         u8 bits_per_cell;
 295         __le16 bb_per_lun;
 296         __le16 block_endurance;
 297         u8 guaranteed_good_blocks;
 298         __le16 guaranteed_block_endurance;
 299         u8 programs_per_page;
 300         u8 ppage_attr;
 301         u8 ecc_bits;
 302         u8 interleaved_bits;
 303         u8 interleaved_ops;
 304         u8 reserved3[13];
 305
 306         /* electrical parameter block */
 307         u8 io_pin_capacitance_max;
 308         __le16 async_timing_mode;
 309         __le16 program_cache_timing_mode;
 310         __le16 t_prog;
 311         __le16 t_bers;
 312         __le16 t_r;
 313         __le16 t_ccs;
 314         __le16 src_sync_timing_mode;
 315         __le16 src_ssync_features;
 316         __le16 clk_pin_capacitance_typ;
 317         __le16 io_pin_capacitance_typ;
 318         __le16 input_pin_capacitance_typ;
 319         u8 input_pin_capacitance_max;
 320         u8 driver_strength_support;
 321         __le16 t_int_r;
 322         __le16 t_ald;
 323         u8 reserved4[7];
 324
 325         /* vendor */
 326         __le16 vendor_revision;
 327         u8 vendor[88];
 328
 329         __le16 crc;
 330 } __packed;
 331
 332 #define ONFI_CRC_BASE   0x4F4E
 333
 334 /* Extended ECC information Block Definition (since ONFI 2.1) */
 335 struct onfi_ext_ecc_info {
 336         u8 ecc_bits;
 337         u8 codeword_size;
 338         __le16 bb_per_lun;
 339         __le16 block_endurance;
 340         u8 reserved[2];
 341 } __packed;
 342
 343 #define ONFI_SECTION_TYPE_0     0       /* Unused section. */
 344 #define ONFI_SECTION_TYPE_1     1       /* for additional sections. */
 345 #define ONFI_SECTION_TYPE_2     2       /* for ECC information. */
 346 struct onfi_ext_section {
 347         u8 type;
 348         u8 length;
 349 } __packed;
 350
 351 #define ONFI_EXT_SECTION_MAX 8
 352
 353 /* Extended Parameter Page Definition (since ONFI 2.1) */
 354 struct onfi_ext_param_page {
 355         __le16 crc;
 356         u8 sig[4];             /* 'E' 'P' 'P' 'S' */
 357         u8 reserved0[10];
 358         struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
 359
 360         /*
 361          * The actual size of the Extended Parameter Page is in
 362          * @ext_param_page_length of nand_onfi_params{}.
 363          * The following are the variable length sections.
 364          * So we do not add any fields below. Please see the ONFI spec.
 365          */
 366 } __packed;
 367
 368 struct nand_onfi_vendor_micron {
 369         u8 two_plane_read;
 370         u8 read_cache;
 371         u8 read_unique_id;
 372         u8 dq_imped;
 373         u8 dq_imped_num_settings;
 374         u8 dq_imped_feat_addr;
 375         u8 rb_pulldown_strength;
 376         u8 rb_pulldown_strength_feat_addr;
 377         u8 rb_pulldown_strength_num_settings;
 378         u8 otp_mode;
 379         u8 otp_page_start;
 380         u8 otp_data_prot_addr;
 381         u8 otp_num_pages;
 382         u8 otp_feat_addr;
 383         u8 read_retry_options;
 384         u8 reserved[72];
 385         u8 param_revision;
 386 } __packed;
 387
 388 struct jedec_ecc_info {
 389         u8 ecc_bits;
 390         u8 codeword_size;
 391         __le16 bb_per_lun;
 392         __le16 block_endurance;
 393         u8 reserved[2];
 394 } __packed;
 395
 396 /* JEDEC features */
 397 #define JEDEC_FEATURE_16_BIT_BUS        (1 << 0)
 398
 399 struct nand_jedec_params {
 400         /* rev info and features block */
 401         /* 'J' 'E' 'S' 'D'  */
 402         u8 sig[4];
 403         __le16 revision;
 404         __le16 features;
 405         u8 opt_cmd[3];
 406         __le16 sec_cmd;
 407         u8 num_of_param_pages;
 408         u8 reserved0[18];
 409
 410         /* manufacturer information block */
 411         char manufacturer[12];
 412         char model[20];
 413         u8 jedec_id[6];
 414         u8 reserved1[10];
 415
 416         /* memory organization block */
 417         __le32 byte_per_page;
 418         __le16 spare_bytes_per_page;
 419         u8 reserved2[6];
 420         __le32 pages_per_block;
 421         __le32 blocks_per_lun;
 422         u8 lun_count;
 423         u8 addr_cycles;
 424         u8 bits_per_cell;
 425         u8 programs_per_page;
 426         u8 multi_plane_addr;
 427         u8 multi_plane_op_attr;
 428         u8 reserved3[38];
 429
 430         /* electrical parameter block */
 431         __le16 async_sdr_speed_grade;
 432         __le16 toggle_ddr_speed_grade;
 433         __le16 sync_ddr_speed_grade;
 434         u8 async_sdr_features;
 435         u8 toggle_ddr_features;
 436         u8 sync_ddr_features;
 437         __le16 t_prog;
 438         __le16 t_bers;
 439         __le16 t_r;
 440         __le16 t_r_multi_plane;
 441         __le16 t_ccs;
 442         __le16 io_pin_capacitance_typ;
 443         __le16 input_pin_capacitance_typ;
 444         __le16 clk_pin_capacitance_typ;
 445         u8 driver_strength_support;
 446         __le16 t_ald;
 447         u8 reserved4[36];
 448
 449         /* ECC and endurance block */
 450         u8 guaranteed_good_blocks;
 451         __le16 guaranteed_block_endurance;
 452         struct jedec_ecc_info ecc_info[4];
 453         u8 reserved5[29];
 454
 455         /* reserved */
 456         u8 reserved6[148];
 457
 458         /* vendor */
 459         __le16 vendor_rev_num;
 460         u8 reserved7[88];
 461
 462         /* CRC for Parameter Page */
 463         __le16 crc;
 464 } __packed;
 465
 466 /**
 467  * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
 468  * @lock:               protection lock
 469  * @active:             the mtd device which holds the controller currently
 470  * @wq:                 wait queue to sleep on if a NAND operation is in
 471  *                      progress used instead of the per chip wait queue
 472  *                      when a hw controller is available.
 473  */
 474 struct nand_hw_control {
 475         spinlock_t lock;
 476         struct nand_chip *active;
 477 #ifndef __UBOOT__
 478         wait_queue_head_t wq;
 479 #endif
 480 };
 481
 482 /**
 483  * struct nand_ecc_ctrl - Control structure for ECC
 484  * @mode:       ECC mode
 485  * @steps:      number of ECC steps per page
 486  * @size:       data bytes per ECC step
 487  * @bytes:      ECC bytes per step
 488  * @strength:   max number of correctible bits per ECC step
 489  * @total:      total number of ECC bytes per page
 490  * @prepad:     padding information for syndrome based ECC generators
 491  * @postpad:    padding information for syndrome based ECC generators
 492  * @layout:     ECC layout control struct pointer
 493  * @priv:       pointer to private ECC control data
 494  * @hwctl:      function to control hardware ECC generator. Must only
 495  *              be provided if an hardware ECC is available
 496  * @calculate:  function for ECC calculation or readback from ECC hardware
 497  * @correct:    function for ECC correction, matching to ECC generator (sw/hw)
 498  * @read_page_raw:      function to read a raw page without ECC
 499  * @write_page_raw:     function to write a raw page without ECC
 500  * @read_page:  function to read a page according to the ECC generator
 501  *              requirements; returns maximum number of bitflips corrected in
 502  *              any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
 503  * @read_subpage:       function to read parts of the page covered by ECC;
 504  *                      returns same as read_page()
 505  * @write_subpage:      function to write parts of the page covered by ECC.
 506  * @write_page: function to write a page according to the ECC generator
 507  *              requirements.
 508  * @write_oob_raw:      function to write chip OOB data without ECC
 509  * @read_oob_raw:       function to read chip OOB data without ECC
 510  * @read_oob:   function to read chip OOB data
 511  * @write_oob:  function to write chip OOB data
 512  */
 513 struct nand_ecc_ctrl {
 514         nand_ecc_modes_t mode;
 515         int steps;
 516         int size;
 517         int bytes;
 518         int total;
 519         int strength;
 520         int prepad;
 521         int postpad;
 522         struct nand_ecclayout   *layout;
 523         void *priv;
 524         void (*hwctl)(struct mtd_info *mtd, int mode);
 525         int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
 526                         uint8_t *ecc_code);
 527         int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
 528                         uint8_t *calc_ecc);
 529         int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 530                         uint8_t *buf, int oob_required, int page);
 531         int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 532                         const uint8_t *buf, int oob_required);
 533         int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
 534                         uint8_t *buf, int oob_required, int page);
 535         int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
 536                         uint32_t offs, uint32_t len, uint8_t *buf, int page);
 537         int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
 538                         uint32_t offset, uint32_t data_len,
 539                         const uint8_t *data_buf, int oob_required);
 540         int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
 541                         const uint8_t *buf, int oob_required);
 542         int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 543                         int page);
 544         int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 545                         int page);
 546         int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
 547         int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
 548                         int page);
 549 };
 550
 551 /**
 552  * struct nand_buffers - buffer structure for read/write
 553  * @ecccalc:    buffer pointer for calculated ECC, size is oobsize.
 554  * @ecccode:    buffer pointer for ECC read from flash, size is oobsize.
 555  * @databuf:    buffer pointer for data, size is (page size + oobsize).
 556  *
 557  * Do not change the order of buffers. databuf and oobrbuf must be in
 558  * consecutive order.
 559  */
 560 struct nand_buffers {
 561 #ifndef __UBOOT__
 562         uint8_t *ecccalc;
 563         uint8_t *ecccode;
 564         uint8_t *databuf;
 565 #else
 566         uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
 567         uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
 568         uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
 569                               ARCH_DMA_MINALIGN)];
 570 #endif
 571 };
 572
 573 /**
 574  * struct nand_chip - NAND Private Flash Chip Data
 575  * @IO_ADDR_R:          [BOARDSPECIFIC] address to read the 8 I/O lines of the
 576  *                      flash device
 577  * @IO_ADDR_W:          [BOARDSPECIFIC] address to write the 8 I/O lines of the
 578  *                      flash device.
 579  * @read_byte:          [REPLACEABLE] read one byte from the chip
 580  * @read_word:          [REPLACEABLE] read one word from the chip
 581  * @write_byte:         [REPLACEABLE] write a single byte to the chip on the
 582  *                      low 8 I/O lines
 583  * @write_buf:          [REPLACEABLE] write data from the buffer to the chip
 584  * @read_buf:           [REPLACEABLE] read data from the chip into the buffer
 585  * @select_chip:        [REPLACEABLE] select chip nr
 586  * @block_bad:          [REPLACEABLE] check if a block is bad, using OOB markers
 587  * @block_markbad:      [REPLACEABLE] mark a block bad
 588  * @cmd_ctrl:           [BOARDSPECIFIC] hardwarespecific function for controlling
 589  *                      ALE/CLE/nCE. Also used to write command and address
 590  * @init_size:          [BOARDSPECIFIC] hardwarespecific function for setting
 591  *                      mtd->oobsize, mtd->writesize and so on.
 592  *                      @id_data contains the 8 bytes values of NAND_CMD_READID.
 593  *                      Return with the bus width.
 594  * @dev_ready:          [BOARDSPECIFIC] hardwarespecific function for accessing
 595  *                      device ready/busy line. If set to NULL no access to
 596  *                      ready/busy is available and the ready/busy information
 597  *                      is read from the chip status register.
 598  * @cmdfunc:            [REPLACEABLE] hardwarespecific function for writing
 599  *                      commands to the chip.
 600  * @waitfunc:           [REPLACEABLE] hardwarespecific function for wait on
 601  *                      ready.
 602  * @setup_read_retry:   [FLASHSPECIFIC] flash (vendor) specific function for
 603  *                      setting the read-retry mode. Mostly needed for MLC NAND.
 604  * @ecc:                [BOARDSPECIFIC] ECC control structure
 605  * @buffers:            buffer structure for read/write
 606  * @hwcontrol:          platform-specific hardware control structure
 607  * @erase_cmd:          [INTERN] erase command write function, selectable due
 608  *                      to AND support.
 609  * @scan_bbt:           [REPLACEABLE] function to scan bad block table
 610  * @chip_delay:         [BOARDSPECIFIC] chip dependent delay for transferring
 611  *                      data from array to read regs (tR).
 612  * @state:              [INTERN] the current state of the NAND device
 613  * @oob_poi:            "poison value buffer," used for laying out OOB data
 614  *                      before writing
 615  * @page_shift:         [INTERN] number of address bits in a page (column
 616  *                      address bits).
 617  * @phys_erase_shift:   [INTERN] number of address bits in a physical eraseblock
 618  * @bbt_erase_shift:    [INTERN] number of address bits in a bbt entry
 619  * @chip_shift:         [INTERN] number of address bits in one chip
 620  * @options:            [BOARDSPECIFIC] various chip options. They can partly
 621  *                      be set to inform nand_scan about special functionality.
 622  *                      See the defines for further explanation.
 623  * @bbt_options:        [INTERN] bad block specific options. All options used
 624  *                      here must come from bbm.h. By default, these options
 625  *                      will be copied to the appropriate nand_bbt_descr's.
 626  * @badblockpos:        [INTERN] position of the bad block marker in the oob
 627  *                      area.
 628  * @badblockbits:       [INTERN] minimum number of set bits in a good block's
 629  *                      bad block marker position; i.e., BBM == 11110111b is
 630  *                      not bad when badblockbits == 7
 631  * @bits_per_cell:      [INTERN] number of bits per cell. i.e., 1 means SLC.
 632  * @ecc_strength_ds:    [INTERN] ECC correctability from the datasheet.
 633  *                      Minimum amount of bit errors per @ecc_step_ds guaranteed
 634  *                      to be correctable. If unknown, set to zero.
 635  * @ecc_step_ds:        [INTERN] ECC step required by the @ecc_strength_ds,
 636  *                      also from the datasheet. It is the recommended ECC step
 637  *                      size, if known; if unknown, set to zero.
 638  * @numchips:           [INTERN] number of physical chips
 639  * @chipsize:           [INTERN] the size of one chip for multichip arrays
 640  * @pagemask:           [INTERN] page number mask = number of (pages / chip) - 1
 641  * @pagebuf:            [INTERN] holds the pagenumber which is currently in
 642  *                      data_buf.
 643  * @pagebuf_bitflips:   [INTERN] holds the bitflip count for the page which is
 644  *                      currently in data_buf.
 645  * @subpagesize:        [INTERN] holds the subpagesize
 646  * @onfi_version:       [INTERN] holds the chip ONFI version (BCD encoded),
 647  *                      non 0 if ONFI supported.
 648  * @jedec_version:      [INTERN] holds the chip JEDEC version (BCD encoded),
 649  *                      non 0 if JEDEC supported.
 650  * @onfi_params:        [INTERN] holds the ONFI page parameter when ONFI is
 651  *                      supported, 0 otherwise.
 652  * @jedec_params:       [INTERN] holds the JEDEC parameter page when JEDEC is
 653  *                      supported, 0 otherwise.
 654  * @read_retries:       [INTERN] the number of read retry modes supported
 655  * @onfi_set_features:  [REPLACEABLE] set the features for ONFI nand
 656  * @onfi_get_features:  [REPLACEABLE] get the features for ONFI nand
 657  * @bbt:                [INTERN] bad block table pointer
 658  * @bbt_td:             [REPLACEABLE] bad block table descriptor for flash
 659  *                      lookup.
 660  * @bbt_md:             [REPLACEABLE] bad block table mirror descriptor
 661  * @badblock_pattern:   [REPLACEABLE] bad block scan pattern used for initial
 662  *                      bad block scan.
 663  * @controller:         [REPLACEABLE] a pointer to a hardware controller
 664  *                      structure which is shared among multiple independent
 665  *                      devices.
 666  * @priv:               [OPTIONAL] pointer to private chip data
 667  * @errstat:            [OPTIONAL] hardware specific function to perform
 668  *                      additional error status checks (determine if errors are
 669  *                      correctable).
 670  * @write_page:         [REPLACEABLE] High-level page write function
 671  */
 672
 673 struct nand_chip {
 674         void __iomem *IO_ADDR_R;
 675         void __iomem *IO_ADDR_W;
 676
 677         uint8_t (*read_byte)(struct mtd_info *mtd);
 678         u16 (*read_word)(struct mtd_info *mtd);
 679         void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
 680         void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 681         void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
 682 #ifdef __UBOOT__
 683 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
 684         int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 685 #endif
 686 #endif
 687         void (*select_chip)(struct mtd_info *mtd, int chip);
 688         int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
 689         int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
 690         void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
 691         int (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
 692                         u8 *id_data);
 693         int (*dev_ready)(struct mtd_info *mtd);
 694         void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
 695                         int page_addr);
 696         int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
 697         void (*erase_cmd)(struct mtd_info *mtd, int page);
 698         int (*scan_bbt)(struct mtd_info *mtd);
 699         int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
 700                         int status, int page);
 701         int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
 702                         uint32_t offset, int data_len, const uint8_t *buf,
 703                         int oob_required, int page, int cached, int raw);
 704         int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
 705                         int feature_addr, uint8_t *subfeature_para);
 706         int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
 707                         int feature_addr, uint8_t *subfeature_para);
 708         int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
 709
 710         int chip_delay;
 711         unsigned int options;
 712         unsigned int bbt_options;
 713
 714         int page_shift;
 715         int phys_erase_shift;
 716         int bbt_erase_shift;
 717         int chip_shift;
 718         int numchips;
 719         uint64_t chipsize;
 720         int pagemask;
 721         int pagebuf;
 722         unsigned int pagebuf_bitflips;
 723         int subpagesize;
 724         uint8_t bits_per_cell;
 725         uint16_t ecc_strength_ds;
 726         uint16_t ecc_step_ds;
 727         int badblockpos;
 728         int badblockbits;
 729
 730         int onfi_version;
 731         int jedec_version;
 732 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
 733         struct nand_onfi_params onfi_params;
 734 #endif
 735         struct nand_jedec_params jedec_params;
 736
 737         int read_retries;
 738
 739         flstate_t state;
 740
 741         uint8_t *oob_poi;
 742         struct nand_hw_control *controller;
 743 #ifdef __UBOOT__
 744         struct nand_ecclayout *ecclayout;
 745 #endif
 746
 747         struct nand_ecc_ctrl ecc;
 748         struct nand_buffers *buffers;
 749         struct nand_hw_control hwcontrol;
 750
 751         uint8_t *bbt;
 752         struct nand_bbt_descr *bbt_td;
 753         struct nand_bbt_descr *bbt_md;
 754
 755         struct nand_bbt_descr *badblock_pattern;
 756
 757         void *priv;
 758 };
 759
 760 /*
 761  * NAND Flash Manufacturer ID Codes
 762  */
 763 #define NAND_MFR_TOSHIBA        0x98
 764 #define NAND_MFR_SAMSUNG        0xec
 765 #define NAND_MFR_FUJITSU        0x04
 766 #define NAND_MFR_NATIONAL       0x8f
 767 #define NAND_MFR_RENESAS        0x07
 768 #define NAND_MFR_STMICRO        0x20
 769 #define NAND_MFR_HYNIX          0xad
 770 #define NAND_MFR_MICRON         0x2c
 771 #define NAND_MFR_AMD            0x01
 772 #define NAND_MFR_MACRONIX       0xc2
 773 #define NAND_MFR_EON            0x92
 774 #define NAND_MFR_SANDISK        0x45
 775 #define NAND_MFR_INTEL          0x89
 776
 777 /* The maximum expected count of bytes in the NAND ID sequence */
 778 #define NAND_MAX_ID_LEN 8
 779
 780 /*
 781  * A helper for defining older NAND chips where the second ID byte fully
 782  * defined the chip, including the geometry (chip size, eraseblock size, page
 783  * size). All these chips have 512 bytes NAND page size.
 784  */
 785 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts)          \
 786         { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
 787           .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
 788
 789 /*
 790  * A helper for defining newer chips which report their page size and
 791  * eraseblock size via the extended ID bytes.
 792  *
 793  * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
 794  * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
 795  * device ID now only represented a particular total chip size (and voltage,
 796  * buswidth), and the page size, eraseblock size, and OOB size could vary while
 797  * using the same device ID.
 798  */
 799 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts)                      \
 800         { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
 801           .options = (opts) }
 802
 803 #define NAND_ECC_INFO(_strength, _step) \
 804                         { .strength_ds = (_strength), .step_ds = (_step) }
 805 #define NAND_ECC_STRENGTH(type)         ((type)->ecc.strength_ds)
 806 #define NAND_ECC_STEP(type)             ((type)->ecc.step_ds)
 807
 808 /**
 809  * struct nand_flash_dev - NAND Flash Device ID Structure
 810  * @name: a human-readable name of the NAND chip
 811  * @dev_id: the device ID (the second byte of the full chip ID array)
 812  * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
 813  *          memory address as @id[0])
 814  * @dev_id: device ID part of the full chip ID array (refers the same memory
 815  *          address as @id[1])
 816  * @id: full device ID array
 817  * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
 818  *            well as the eraseblock size) is determined from the extended NAND
 819  *            chip ID array)
 820  * @chipsize: total chip size in MiB
 821  * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
 822  * @options: stores various chip bit options
 823  * @id_len: The valid length of the @id.
 824  * @oobsize: OOB size
 825  * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
 826  *                   @ecc_strength_ds in nand_chip{}.
 827  * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
 828  *               @ecc_step_ds in nand_chip{}, also from the datasheet.
 829  *               For example, the "4bit ECC for each 512Byte" can be set with
 830  *               NAND_ECC_INFO(4, 512).
 831  */
 832 struct nand_flash_dev {
 833         char *name;
 834         union {
 835                 struct {
 836                         uint8_t mfr_id;
 837                         uint8_t dev_id;
 838                 };
 839                 uint8_t id[NAND_MAX_ID_LEN];
 840         };
 841         unsigned int pagesize;
 842         unsigned int chipsize;
 843         unsigned int erasesize;
 844         unsigned int options;
 845         uint16_t id_len;
 846         uint16_t oobsize;
 847         struct {
 848                 uint16_t strength_ds;
 849                 uint16_t step_ds;
 850         } ecc;
 851 };
 852
 853 /**
 854  * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
 855  * @name:       Manufacturer name
 856  * @id:         manufacturer ID code of device.
 857 */
 858 struct nand_manufacturers {
 859         int id;
 860         char *name;
 861 };
 862
 863 extern struct nand_flash_dev nand_flash_ids[];
 864 extern struct nand_manufacturers nand_manuf_ids[];
 865
 866 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
 867 extern int nand_default_bbt(struct mtd_info *mtd);
 868 extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
 869 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
 870 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 871                            int allowbbt);
 872 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
 873                         size_t *retlen, uint8_t *buf);
 874
 875 #ifdef __UBOOT__
 876 /*
 877 * Constants for oob configuration
 878 */
 879 #define NAND_SMALL_BADBLOCK_POS         5
 880 #define NAND_LARGE_BADBLOCK_POS         0
 881 #endif
 882
 883 /**
 884  * struct platform_nand_chip - chip level device structure
 885  * @nr_chips:           max. number of chips to scan for
 886  * @chip_offset:        chip number offset
 887  * @nr_partitions:      number of partitions pointed to by partitions (or zero)
 888  * @partitions:         mtd partition list
 889  * @chip_delay:         R/B delay value in us
 890  * @options:            Option flags, e.g. 16bit buswidth
 891  * @bbt_options:        BBT option flags, e.g. NAND_BBT_USE_FLASH
 892  * @ecclayout:          ECC layout info structure
 893  * @part_probe_types:   NULL-terminated array of probe types
 894  */
 895 struct platform_nand_chip {
 896         int nr_chips;
 897         int chip_offset;
 898         int nr_partitions;
 899         struct mtd_partition *partitions;
 900         struct nand_ecclayout *ecclayout;
 901         int chip_delay;
 902         unsigned int options;
 903         unsigned int bbt_options;
 904         const char **part_probe_types;
 905 };
 906
 907 /* Keep gcc happy */
 908 struct platform_device;
 909
 910 /**
 911  * struct platform_nand_ctrl - controller level device structure
 912  * @probe:              platform specific function to probe/setup hardware
 913  * @remove:             platform specific function to remove/teardown hardware
 914  * @hwcontrol:          platform specific hardware control structure
 915  * @dev_ready:          platform specific function to read ready/busy pin
 916  * @select_chip:        platform specific chip select function
 917  * @cmd_ctrl:           platform specific function for controlling
 918  *                      ALE/CLE/nCE. Also used to write command and address
 919  * @write_buf:          platform specific function for write buffer
 920  * @read_buf:           platform specific function for read buffer
 921  * @read_byte:          platform specific function to read one byte from chip
 922  * @priv:               private data to transport driver specific settings
 923  *
 924  * All fields are optional and depend on the hardware driver requirements
 925  */
 926 struct platform_nand_ctrl {
 927         int (*probe)(struct platform_device *pdev);
 928         void (*remove)(struct platform_device *pdev);
 929         void (*hwcontrol)(struct mtd_info *mtd, int cmd);
 930         int (*dev_ready)(struct mtd_info *mtd);
 931         void (*select_chip)(struct mtd_info *mtd, int chip);
 932         void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
 933         void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 934         void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
 935         unsigned char (*read_byte)(struct mtd_info *mtd);
 936         void *priv;
 937 };
 938
 939 /**
 940  * struct platform_nand_data - container structure for platform-specific data
 941  * @chip:               chip level chip structure
 942  * @ctrl:               controller level device structure
 943  */
 944 struct platform_nand_data {
 945         struct platform_nand_chip chip;
 946         struct platform_nand_ctrl ctrl;
 947 };
 948
 949 /* Some helpers to access the data structures */
 950 static inline
 951 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
 952 {
 953         struct nand_chip *chip = mtd->priv;
 954
 955         return chip->priv;
 956 }
 957
 958 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
 959 /* return the supported features. */
 960 static inline int onfi_feature(struct nand_chip *chip)
 961 {
 962         return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
 963 }
 964
 965 /* return the supported asynchronous timing mode. */
 966 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
 967 {
 968         if (!chip->onfi_version)
 969                 return ONFI_TIMING_MODE_UNKNOWN;
 970         return le16_to_cpu(chip->onfi_params.async_timing_mode);
 971 }
 972
 973 /* return the supported synchronous timing mode. */
 974 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
 975 {
 976         if (!chip->onfi_version)
 977                 return ONFI_TIMING_MODE_UNKNOWN;
 978         return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
 979 }
 980 #endif
 981
 982 /*
 983  * Check if it is a SLC nand.
 984  * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
 985  * We do not distinguish the MLC and TLC now.
 986  */
 987 static inline bool nand_is_slc(struct nand_chip *chip)
 988 {
 989         return chip->bits_per_cell == 1;
 990 }
 991
 992 /**
 993  * Check if the opcode's address should be sent only on the lower 8 bits
 994  * @command: opcode to check
 995  */
 996 static inline int nand_opcode_8bits(unsigned int command)
 997 {
 998         switch (command) {
 999         case NAND_CMD_READID:
1000         case NAND_CMD_PARAM:
1001         case NAND_CMD_GET_FEATURES:
1002         case NAND_CMD_SET_FEATURES:
1003                 return 1;
1004         default:
1005                 break;
1006         }
1007         return 0;
1008 }
1009
1010 /* return the supported JEDEC features. */
1011 static inline int jedec_feature(struct nand_chip *chip)
1012 {
1013         return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
1014                 : 0;
1015 }
1016
1017 #ifdef __UBOOT__
1018 /* Standard NAND functions from nand_base.c */
1019 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
1020 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);
1021 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
1022 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
1023 uint8_t nand_read_byte(struct mtd_info *mtd);
1024 #endif
1025 #endif /* __LINUX_MTD_NAND_H */