include/mmc.h

   1 /*
   2  * Copyright 2008,2010 Freescale Semiconductor, Inc
   3  * Andy Fleming
   4  *
   5  * Based (loosely) on the Linux code
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef _MMC_H_
  11 #define _MMC_H_
  12
  13 #include <linux/list.h>
  14 #include <linux/compiler.h>
  15 #include <part.h>
  16
  17 /* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
  18 #define SD_VERSION_SD   (1U << 31)
  19 #define MMC_VERSION_MMC (1U << 30)
  20
  21 #define MAKE_SDMMC_VERSION(a, b, c)     \
  22         ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c))
  23 #define MAKE_SD_VERSION(a, b, c)        \
  24         (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
  25 #define MAKE_MMC_VERSION(a, b, c)       \
  26         (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))
  27
  28 #define EXTRACT_SDMMC_MAJOR_VERSION(x)  \
  29         (((u32)(x) >> 16) & 0xff)
  30 #define EXTRACT_SDMMC_MINOR_VERSION(x)  \
  31         (((u32)(x) >> 8) & 0xff)
  32 #define EXTRACT_SDMMC_CHANGE_VERSION(x) \
  33         ((u32)(x) & 0xff)
  34
  35 #define SD_VERSION_3            MAKE_SD_VERSION(3, 0, 0)
  36 #define SD_VERSION_2            MAKE_SD_VERSION(2, 0, 0)
  37 #define SD_VERSION_1_0          MAKE_SD_VERSION(1, 0, 0)
  38 #define SD_VERSION_1_10         MAKE_SD_VERSION(1, 10, 0)
  39
  40 #define MMC_VERSION_UNKNOWN     MAKE_MMC_VERSION(0, 0, 0)
  41 #define MMC_VERSION_1_2         MAKE_MMC_VERSION(1, 2, 0)
  42 #define MMC_VERSION_1_4         MAKE_MMC_VERSION(1, 4, 0)
  43 #define MMC_VERSION_2_2         MAKE_MMC_VERSION(2, 2, 0)
  44 #define MMC_VERSION_3           MAKE_MMC_VERSION(3, 0, 0)
  45 #define MMC_VERSION_4           MAKE_MMC_VERSION(4, 0, 0)
  46 #define MMC_VERSION_4_1         MAKE_MMC_VERSION(4, 1, 0)
  47 #define MMC_VERSION_4_2         MAKE_MMC_VERSION(4, 2, 0)
  48 #define MMC_VERSION_4_3         MAKE_MMC_VERSION(4, 3, 0)
  49 #define MMC_VERSION_4_41        MAKE_MMC_VERSION(4, 4, 1)
  50 #define MMC_VERSION_4_5         MAKE_MMC_VERSION(4, 5, 0)
  51 #define MMC_VERSION_5_0         MAKE_MMC_VERSION(5, 0, 0)
  52
  53 #define MMC_MODE_HS             (1 << 0)
  54 #define MMC_MODE_HS_52MHz       (1 << 1)
  55 #define MMC_MODE_4BIT           (1 << 2)
  56 #define MMC_MODE_8BIT           (1 << 3)
  57 #define MMC_MODE_SPI            (1 << 4)
  58 #define MMC_MODE_HC             (1 << 5)
  59 #define MMC_MODE_DDR_52MHz      (1 << 6)
  60
  61 #define SD_DATA_4BIT    0x00040000
  62
  63 #define IS_SD(x)        ((x)->version & SD_VERSION_SD)
  64 #define IS_MMC(x)       ((x)->version & SD_VERSION_MMC)
  65
  66 #define MMC_DATA_READ           1
  67 #define MMC_DATA_WRITE          2
  68
  69 #define NO_CARD_ERR             -16 /* No SD/MMC card inserted */
  70 #define UNUSABLE_ERR            -17 /* Unusable Card */
  71 #define COMM_ERR                -18 /* Communications Error */
  72 #define TIMEOUT                 -19
  73 #define IN_PROGRESS             -20 /* operation is in progress */
  74 #define SWITCH_ERR              -21 /* Card reports failure to switch mode */
  75
  76 #define MMC_CMD_GO_IDLE_STATE           0
  77 #define MMC_CMD_SEND_OP_COND            1
  78 #define MMC_CMD_ALL_SEND_CID            2
  79 #define MMC_CMD_SET_RELATIVE_ADDR       3
  80 #define MMC_CMD_SET_DSR                 4
  81 #define MMC_CMD_SWITCH                  6
  82 #define MMC_CMD_SELECT_CARD             7
  83 #define MMC_CMD_SEND_EXT_CSD            8
  84 #define MMC_CMD_SEND_CSD                9
  85 #define MMC_CMD_SEND_CID                10
  86 #define MMC_CMD_STOP_TRANSMISSION       12
  87 #define MMC_CMD_SEND_STATUS             13
  88 #define MMC_CMD_SET_BLOCKLEN            16
  89 #define MMC_CMD_READ_SINGLE_BLOCK       17
  90 #define MMC_CMD_READ_MULTIPLE_BLOCK     18
  91 #define MMC_CMD_SET_BLOCK_COUNT         23
  92 #define MMC_CMD_WRITE_SINGLE_BLOCK      24
  93 #define MMC_CMD_WRITE_MULTIPLE_BLOCK    25
  94 #define MMC_CMD_ERASE_GROUP_START       35
  95 #define MMC_CMD_ERASE_GROUP_END         36
  96 #define MMC_CMD_ERASE                   38
  97 #define MMC_CMD_APP_CMD                 55
  98 #define MMC_CMD_SPI_READ_OCR            58
  99 #define MMC_CMD_SPI_CRC_ON_OFF          59
 100 #define MMC_CMD_RES_MAN                 62
 101
 102 #define MMC_CMD62_ARG1                  0xefac62ec
 103 #define MMC_CMD62_ARG2                  0xcbaea7
 104
 105
 106 #define SD_CMD_SEND_RELATIVE_ADDR       3
 107 #define SD_CMD_SWITCH_FUNC              6
 108 #define SD_CMD_SEND_IF_COND             8
 109 #define SD_CMD_SWITCH_UHS18V            11
 110
 111 #define SD_CMD_APP_SET_BUS_WIDTH        6
 112 #define SD_CMD_ERASE_WR_BLK_START       32
 113 #define SD_CMD_ERASE_WR_BLK_END         33
 114 #define SD_CMD_APP_SEND_OP_COND         41
 115 #define SD_CMD_APP_SEND_SCR             51
 116
 117 /* SCR definitions in different words */
 118 #define SD_HIGHSPEED_BUSY       0x00020000
 119 #define SD_HIGHSPEED_SUPPORTED  0x00020000
 120
 121 #define OCR_BUSY                0x80000000
 122 #define OCR_HCS                 0x40000000
 123 #define OCR_VOLTAGE_MASK        0x007FFF80
 124 #define OCR_ACCESS_MODE         0x60000000
 125
 126 #define SECURE_ERASE            0x80000000
 127
 128 #define MMC_STATUS_MASK         (~0x0206BF7F)
 129 #define MMC_STATUS_SWITCH_ERROR (1 << 7)
 130 #define MMC_STATUS_RDY_FOR_DATA (1 << 8)
 131 #define MMC_STATUS_CURR_STATE   (0xf << 9)
 132 #define MMC_STATUS_ERROR        (1 << 19)
 133
 134 #define MMC_STATE_PRG           (7 << 9)
 135
 136 #define MMC_VDD_165_195         0x00000080      /* VDD voltage 1.65 - 1.95 */
 137 #define MMC_VDD_20_21           0x00000100      /* VDD voltage 2.0 ~ 2.1 */
 138 #define MMC_VDD_21_22           0x00000200      /* VDD voltage 2.1 ~ 2.2 */
 139 #define MMC_VDD_22_23           0x00000400      /* VDD voltage 2.2 ~ 2.3 */
 140 #define MMC_VDD_23_24           0x00000800      /* VDD voltage 2.3 ~ 2.4 */
 141 #define MMC_VDD_24_25           0x00001000      /* VDD voltage 2.4 ~ 2.5 */
 142 #define MMC_VDD_25_26           0x00002000      /* VDD voltage 2.5 ~ 2.6 */
 143 #define MMC_VDD_26_27           0x00004000      /* VDD voltage 2.6 ~ 2.7 */
 144 #define MMC_VDD_27_28           0x00008000      /* VDD voltage 2.7 ~ 2.8 */
 145 #define MMC_VDD_28_29           0x00010000      /* VDD voltage 2.8 ~ 2.9 */
 146 #define MMC_VDD_29_30           0x00020000      /* VDD voltage 2.9 ~ 3.0 */
 147 #define MMC_VDD_30_31           0x00040000      /* VDD voltage 3.0 ~ 3.1 */
 148 #define MMC_VDD_31_32           0x00080000      /* VDD voltage 3.1 ~ 3.2 */
 149 #define MMC_VDD_32_33           0x00100000      /* VDD voltage 3.2 ~ 3.3 */
 150 #define MMC_VDD_33_34           0x00200000      /* VDD voltage 3.3 ~ 3.4 */
 151 #define MMC_VDD_34_35           0x00400000      /* VDD voltage 3.4 ~ 3.5 */
 152 #define MMC_VDD_35_36           0x00800000      /* VDD voltage 3.5 ~ 3.6 */
 153
 154 #define MMC_SWITCH_MODE_CMD_SET         0x00 /* Change the command set */
 155 #define MMC_SWITCH_MODE_SET_BITS        0x01 /* Set bits in EXT_CSD byte
 156                                                 addressed by index which are
 157                                                 1 in value field */
 158 #define MMC_SWITCH_MODE_CLEAR_BITS      0x02 /* Clear bits in EXT_CSD byte
 159                                                 addressed by index, which are
 160                                                 1 in value field */
 161 #define MMC_SWITCH_MODE_WRITE_BYTE      0x03 /* Set target byte to value */
 162
 163 #define SD_SWITCH_CHECK         0
 164 #define SD_SWITCH_SWITCH        1
 165
 166 /*
 167  * EXT_CSD fields
 168  */
 169 #define EXT_CSD_ENH_START_ADDR          136     /* R/W */
 170 #define EXT_CSD_ENH_SIZE_MULT           140     /* R/W */
 171 #define EXT_CSD_GP_SIZE_MULT            143     /* R/W */
 172 #define EXT_CSD_PARTITION_SETTING       155     /* R/W */
 173 #define EXT_CSD_PARTITIONS_ATTRIBUTE    156     /* R/W */
 174 #define EXT_CSD_MAX_ENH_SIZE_MULT       157     /* R */
 175 #define EXT_CSD_PARTITIONING_SUPPORT    160     /* RO */
 176 #define EXT_CSD_RST_N_FUNCTION          162     /* R/W */
 177 #define EXT_CSD_WR_REL_PARAM            166     /* R */
 178 #define EXT_CSD_WR_REL_SET              167     /* R/W */
 179 #define EXT_CSD_RPMB_MULT               168     /* RO */
 180 #define EXT_CSD_ERASE_GROUP_DEF         175     /* R/W */
 181 #define EXT_CSD_BOOT_BUS_WIDTH          177
 182 #define EXT_CSD_PART_CONF               179     /* R/W */
 183 #define EXT_CSD_BUS_WIDTH               183     /* R/W */
 184 #define EXT_CSD_HS_TIMING               185     /* R/W */
 185 #define EXT_CSD_REV                     192     /* RO */
 186 #define EXT_CSD_CARD_TYPE               196     /* RO */
 187 #define EXT_CSD_SEC_CNT                 212     /* RO, 4 bytes */
 188 #define EXT_CSD_HC_WP_GRP_SIZE          221     /* RO */
 189 #define EXT_CSD_HC_ERASE_GRP_SIZE       224     /* RO */
 190 #define EXT_CSD_BOOT_MULT               226     /* RO */
 191
 192 /*
 193  * EXT_CSD field definitions
 194  */
 195
 196 #define EXT_CSD_CMD_SET_NORMAL          (1 << 0)
 197 #define EXT_CSD_CMD_SET_SECURE          (1 << 1)
 198 #define EXT_CSD_CMD_SET_CPSECURE        (1 << 2)
 199
 200 #define EXT_CSD_CARD_TYPE_26    (1 << 0)        /* Card can run at 26MHz */
 201 #define EXT_CSD_CARD_TYPE_52    (1 << 1)        /* Card can run at 52MHz */
 202 #define EXT_CSD_CARD_TYPE_DDR_1_8V      (1 << 2)
 203 #define EXT_CSD_CARD_TYPE_DDR_1_2V      (1 << 3)
 204 #define EXT_CSD_CARD_TYPE_DDR_52        (EXT_CSD_CARD_TYPE_DDR_1_8V \
 205                                         | EXT_CSD_CARD_TYPE_DDR_1_2V)
 206
 207 #define EXT_CSD_BUS_WIDTH_1     0       /* Card is in 1 bit mode */
 208 #define EXT_CSD_BUS_WIDTH_4     1       /* Card is in 4 bit mode */
 209 #define EXT_CSD_BUS_WIDTH_8     2       /* Card is in 8 bit mode */
 210 #define EXT_CSD_DDR_BUS_WIDTH_4 5       /* Card is in 4 bit DDR mode */
 211 #define EXT_CSD_DDR_BUS_WIDTH_8 6       /* Card is in 8 bit DDR mode */
 212
 213 #define EXT_CSD_BOOT_ACK_ENABLE                 (1 << 6)
 214 #define EXT_CSD_BOOT_PARTITION_ENABLE           (1 << 3)
 215 #define EXT_CSD_PARTITION_ACCESS_ENABLE         (1 << 0)
 216 #define EXT_CSD_PARTITION_ACCESS_DISABLE        (0 << 0)
 217
 218 #define EXT_CSD_BOOT_ACK(x)             (x << 6)
 219 #define EXT_CSD_BOOT_PART_NUM(x)        (x << 3)
 220 #define EXT_CSD_PARTITION_ACCESS(x)     (x << 0)
 221
 222 #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x)  (x << 3)
 223 #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
 224 #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
 225
 226 #define EXT_CSD_PARTITION_SETTING_COMPLETED     (1 << 0)
 227
 228 #define EXT_CSD_ENH_USR         (1 << 0)        /* user data area is enhanced */
 229 #define EXT_CSD_ENH_GP(x)       (1 << ((x)+1))  /* GP part (x+1) is enhanced */
 230
 231 #define EXT_CSD_HS_CTRL_REL     (1 << 0)        /* host controlled WR_REL_SET */
 232
 233 #define EXT_CSD_WR_DATA_REL_USR         (1 << 0)        /* user data area WR_REL */
 234 #define EXT_CSD_WR_DATA_REL_GP(x)       (1 << ((x)+1))  /* GP part (x+1) WR_REL */
 235
 236 #define R1_ILLEGAL_COMMAND              (1 << 22)
 237 #define R1_APP_CMD                      (1 << 5)
 238
 239 #define MMC_RSP_PRESENT (1 << 0)
 240 #define MMC_RSP_136     (1 << 1)                /* 136 bit response */
 241 #define MMC_RSP_CRC     (1 << 2)                /* expect valid crc */
 242 #define MMC_RSP_BUSY    (1 << 3)                /* card may send busy */
 243 #define MMC_RSP_OPCODE  (1 << 4)                /* response contains opcode */
 244
 245 #define MMC_RSP_NONE    (0)
 246 #define MMC_RSP_R1      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 247 #define MMC_RSP_R1b     (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
 248                         MMC_RSP_BUSY)
 249 #define MMC_RSP_R2      (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
 250 #define MMC_RSP_R3      (MMC_RSP_PRESENT)
 251 #define MMC_RSP_R4      (MMC_RSP_PRESENT)
 252 #define MMC_RSP_R5      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 253 #define MMC_RSP_R6      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 254 #define MMC_RSP_R7      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 255
 256 #define MMCPART_NOAVAILABLE     (0xff)
 257 #define PART_ACCESS_MASK        (0x7)
 258 #define PART_SUPPORT            (0x1)
 259 #define ENHNCD_SUPPORT          (0x2)
 260 #define PART_ENH_ATTRIB         (0x1f)
 261
 262 /* Maximum block size for MMC */
 263 #define MMC_MAX_BLOCK_LEN       512
 264
 265 /* The number of MMC physical partitions.  These consist of:
 266  * boot partitions (2), general purpose partitions (4) in MMC v4.4.
 267  */
 268 #define MMC_NUM_BOOT_PARTITION  2
 269 #define MMC_PART_RPMB           3       /* RPMB partition number */
 270
 271 struct mmc_cid {
 272         unsigned long psn;
 273         unsigned short oid;
 274         unsigned char mid;
 275         unsigned char prv;
 276         unsigned char mdt;
 277         char pnm[7];
 278 };
 279
 280 struct mmc_cmd {
 281         ushort cmdidx;
 282         uint resp_type;
 283         uint cmdarg;
 284         uint response[4];
 285 };
 286
 287 struct mmc_data {
 288         union {
 289                 char *dest;
 290                 const char *src; /* src buffers don't get written to */
 291         };
 292         uint flags;
 293         uint blocks;
 294         uint blocksize;
 295 };
 296
 297 /* forward decl. */
 298 struct mmc;
 299
 300 struct mmc_ops {
 301         int (*send_cmd)(struct mmc *mmc,
 302                         struct mmc_cmd *cmd, struct mmc_data *data);
 303         void (*set_ios)(struct mmc *mmc);
 304         int (*init)(struct mmc *mmc);
 305         int (*getcd)(struct mmc *mmc);
 306         int (*getwp)(struct mmc *mmc);
 307 };
 308
 309 struct mmc_config {
 310         const char *name;
 311         const struct mmc_ops *ops;
 312         uint host_caps;
 313         uint voltages;
 314         uint f_min;
 315         uint f_max;
 316         uint b_max;
 317         unsigned char part_type;
 318 };
 319
 320 /* TODO struct mmc should be in mmc_private but it's hard to fix right now */
 321 struct mmc {
 322         struct list_head link;
 323         const struct mmc_config *cfg;   /* provided configuration */
 324         uint version;
 325         void *priv;
 326         uint has_init;
 327         int high_capacity;
 328         uint bus_width;
 329         uint clock;
 330         uint card_caps;
 331         uint ocr;
 332         uint dsr;
 333         uint dsr_imp;
 334         uint scr[2];
 335         uint csd[4];
 336         uint cid[4];
 337         ushort rca;
 338         u8 part_support;
 339         u8 part_attr;
 340         u8 wr_rel_set;
 341         char part_config;
 342         char part_num;
 343         uint tran_speed;
 344         uint read_bl_len;
 345         uint write_bl_len;
 346         uint erase_grp_size;    /* in 512-byte sectors */
 347         uint hc_wp_grp_size;    /* in 512-byte sectors */
 348         u64 capacity;
 349         u64 capacity_user;
 350         u64 capacity_boot;
 351         u64 capacity_rpmb;
 352         u64 capacity_gp[4];
 353         u64 enh_user_start;
 354         u64 enh_user_size;
 355         block_dev_desc_t block_dev;
 356         char op_cond_pending;   /* 1 if we are waiting on an op_cond command */
 357         char init_in_progress;  /* 1 if we have done mmc_start_init() */
 358         char preinit;           /* start init as early as possible */
 359         uint op_cond_response;  /* the response byte from the last op_cond */
 360         int ddr_mode;
 361 };
 362
 363 struct mmc_hwpart_conf {
 364         struct {
 365                 uint enh_start; /* in 512-byte sectors */
 366                 uint enh_size;  /* in 512-byte sectors, if 0 no enh area */
 367                 unsigned wr_rel_change : 1;
 368                 unsigned wr_rel_set : 1;
 369         } user;
 370         struct {
 371                 uint size;      /* in 512-byte sectors */
 372                 unsigned enhanced : 1;
 373                 unsigned wr_rel_change : 1;
 374                 unsigned wr_rel_set : 1;
 375         } gp_part[4];
 376 };
 377
 378 enum mmc_hwpart_conf_mode {
 379         MMC_HWPART_CONF_CHECK,
 380         MMC_HWPART_CONF_SET,
 381         MMC_HWPART_CONF_COMPLETE,
 382 };
 383
 384 int mmc_register(struct mmc *mmc);
 385 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
 386 void mmc_destroy(struct mmc *mmc);
 387 int mmc_initialize(bd_t *bis);
 388 int mmc_init(struct mmc *mmc);
 389 int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
 390 void mmc_set_clock(struct mmc *mmc, uint clock);
 391 struct mmc *find_mmc_device(int dev_num);
 392 int mmc_set_dev(int dev_num);
 393 void print_mmc_devices(char separator);
 394 int get_mmc_num(void);
 395 int mmc_switch_part(int dev_num, unsigned int part_num);
 396 int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
 397                       enum mmc_hwpart_conf_mode mode);
 398 int mmc_getcd(struct mmc *mmc);
 399 int board_mmc_getcd(struct mmc *mmc);
 400 int mmc_getwp(struct mmc *mmc);
 401 int board_mmc_getwp(struct mmc *mmc);
 402 int mmc_set_dsr(struct mmc *mmc, u16 val);
 403 /* Function to change the size of boot partition and rpmb partitions */
 404 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
 405                                         unsigned long rpmbsize);
 406 /* Function to modify the PARTITION_CONFIG field of EXT_CSD */
 407 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
 408 /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
 409 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
 410 /* Function to modify the RST_n_FUNCTION field of EXT_CSD */
 411 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
 412 /* Functions to read / write the RPMB partition */
 413 int mmc_rpmb_set_key(struct mmc *mmc, void *key);
 414 int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
 415 int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
 416                   unsigned short cnt, unsigned char *key);
 417 int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
 418                    unsigned short cnt, unsigned char *key);
 419 /**
 420  * Start device initialization and return immediately; it does not block on
 421  * polling OCR (operation condition register) status.  Then you should call
 422  * mmc_init, which would block on polling OCR status and complete the device
 423  * initializatin.
 424  *
 425  * @param mmc   Pointer to a MMC device struct
 426  * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error.
 427  */
 428 int mmc_start_init(struct mmc *mmc);
 429
 430 /**
 431  * Set preinit flag of mmc device.
 432  *
 433  * This will cause the device to be pre-inited during mmc_initialize(),
 434  * which may save boot time if the device is not accessed until later.
 435  * Some eMMC devices take 200-300ms to init, but unfortunately they
 436  * must be sent a series of commands to even get them to start preparing
 437  * for operation.
 438  *
 439  * @param mmc           Pointer to a MMC device struct
 440  * @param preinit       preinit flag value
 441  */
 442 void mmc_set_preinit(struct mmc *mmc, int preinit);
 443
 444 #ifdef CONFIG_GENERIC_MMC
 445 #ifdef CONFIG_MMC_SPI
 446 #define mmc_host_is_spi(mmc)    ((mmc)->cfg->host_caps & MMC_MODE_SPI)
 447 #else
 448 #define mmc_host_is_spi(mmc)    0
 449 #endif
 450 struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
 451 #else
 452 int mmc_legacy_init(int verbose);
 453 #endif
 454
 455 void board_mmc_power_init(void);
 456 int board_mmc_init(bd_t *bis);
 457 int cpu_mmc_init(bd_t *bis);
 458 int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
 459
 460 struct pci_device_id;
 461
 462 /**
 463  * pci_mmc_init() - set up PCI MMC devices
 464  *
 465  * This finds all the matching PCI IDs and sets them up as MMC devices.
 466  *
 467  * @name:               Name to use for devices
 468  * @mmc_supported:      PCI IDs to search for
 469  * @num_ids:            Number of elements in @mmc_supported
 470  */
 471 int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported,
 472                  int num_ids);
 473
 474 /* Set block count limit because of 16 bit register limit on some hardware*/
 475 #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
 476 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
 477 #endif
 478
 479 #endif /* _MMC_H_ */