include/mmc.h

   1 /*
   2  * Copyright 2008,2010 Freescale Semiconductor, Inc
   3  * Andy Fleming
   4  *
   5  * Based (loosely) on the Linux code
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef _MMC_H_
  11 #define _MMC_H_
  12
  13 #include <linux/list.h>
  14 #include <linux/sizes.h>
  15 #include <linux/compiler.h>
  16 #include <part.h>
  17
  18 /* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
  19 #define SD_VERSION_SD   (1U << 31)
  20 #define MMC_VERSION_MMC (1U << 30)
  21
  22 #define MAKE_SDMMC_VERSION(a, b, c)     \
  23         ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c))
  24 #define MAKE_SD_VERSION(a, b, c)        \
  25         (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
  26 #define MAKE_MMC_VERSION(a, b, c)       \
  27         (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))
  28
  29 #define EXTRACT_SDMMC_MAJOR_VERSION(x)  \
  30         (((u32)(x) >> 16) & 0xff)
  31 #define EXTRACT_SDMMC_MINOR_VERSION(x)  \
  32         (((u32)(x) >> 8) & 0xff)
  33 #define EXTRACT_SDMMC_CHANGE_VERSION(x) \
  34         ((u32)(x) & 0xff)
  35
  36 #define SD_VERSION_3            MAKE_SD_VERSION(3, 0, 0)
  37 #define SD_VERSION_2            MAKE_SD_VERSION(2, 0, 0)
  38 #define SD_VERSION_1_0          MAKE_SD_VERSION(1, 0, 0)
  39 #define SD_VERSION_1_10         MAKE_SD_VERSION(1, 10, 0)
  40
  41 #define MMC_VERSION_UNKNOWN     MAKE_MMC_VERSION(0, 0, 0)
  42 #define MMC_VERSION_1_2         MAKE_MMC_VERSION(1, 2, 0)
  43 #define MMC_VERSION_1_4         MAKE_MMC_VERSION(1, 4, 0)
  44 #define MMC_VERSION_2_2         MAKE_MMC_VERSION(2, 2, 0)
  45 #define MMC_VERSION_3           MAKE_MMC_VERSION(3, 0, 0)
  46 #define MMC_VERSION_4           MAKE_MMC_VERSION(4, 0, 0)
  47 #define MMC_VERSION_4_1         MAKE_MMC_VERSION(4, 1, 0)
  48 #define MMC_VERSION_4_2         MAKE_MMC_VERSION(4, 2, 0)
  49 #define MMC_VERSION_4_3         MAKE_MMC_VERSION(4, 3, 0)
  50 #define MMC_VERSION_4_41        MAKE_MMC_VERSION(4, 4, 1)
  51 #define MMC_VERSION_4_5         MAKE_MMC_VERSION(4, 5, 0)
  52 #define MMC_VERSION_5_0         MAKE_MMC_VERSION(5, 0, 0)
  53 #define MMC_VERSION_5_1         MAKE_MMC_VERSION(5, 1, 0)
  54
  55 #define MMC_CAP(mode)           (1 << mode)
  56 #define MMC_MODE_HS             (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS))
  57 #define MMC_MODE_HS_52MHz       MMC_CAP(MMC_HS_52)
  58 #define MMC_MODE_DDR_52MHz      MMC_CAP(MMC_DDR_52)
  59
  60 #define MMC_MODE_8BIT           BIT(30)
  61 #define MMC_MODE_4BIT           BIT(29)
  62 #define MMC_MODE_1BIT           BIT(28)
  63 #define MMC_MODE_SPI            BIT(27)
  64
  65
  66 #define SD_DATA_4BIT    0x00040000
  67
  68 #define IS_SD(x)        ((x)->version & SD_VERSION_SD)
  69 #define IS_MMC(x)       ((x)->version & MMC_VERSION_MMC)
  70
  71 #define MMC_DATA_READ           1
  72 #define MMC_DATA_WRITE          2
  73
  74 #define MMC_CMD_GO_IDLE_STATE           0
  75 #define MMC_CMD_SEND_OP_COND            1
  76 #define MMC_CMD_ALL_SEND_CID            2
  77 #define MMC_CMD_SET_RELATIVE_ADDR       3
  78 #define MMC_CMD_SET_DSR                 4
  79 #define MMC_CMD_SWITCH                  6
  80 #define MMC_CMD_SELECT_CARD             7
  81 #define MMC_CMD_SEND_EXT_CSD            8
  82 #define MMC_CMD_SEND_CSD                9
  83 #define MMC_CMD_SEND_CID                10
  84 #define MMC_CMD_STOP_TRANSMISSION       12
  85 #define MMC_CMD_SEND_STATUS             13
  86 #define MMC_CMD_SET_BLOCKLEN            16
  87 #define MMC_CMD_READ_SINGLE_BLOCK       17
  88 #define MMC_CMD_READ_MULTIPLE_BLOCK     18
  89 #define MMC_CMD_SET_BLOCK_COUNT         23
  90 #define MMC_CMD_WRITE_SINGLE_BLOCK      24
  91 #define MMC_CMD_WRITE_MULTIPLE_BLOCK    25
  92 #define MMC_CMD_ERASE_GROUP_START       35
  93 #define MMC_CMD_ERASE_GROUP_END         36
  94 #define MMC_CMD_ERASE                   38
  95 #define MMC_CMD_APP_CMD                 55
  96 #define MMC_CMD_SPI_READ_OCR            58
  97 #define MMC_CMD_SPI_CRC_ON_OFF          59
  98 #define MMC_CMD_RES_MAN                 62
  99
 100 #define MMC_CMD62_ARG1                  0xefac62ec
 101 #define MMC_CMD62_ARG2                  0xcbaea7
 102
 103
 104 #define SD_CMD_SEND_RELATIVE_ADDR       3
 105 #define SD_CMD_SWITCH_FUNC              6
 106 #define SD_CMD_SEND_IF_COND             8
 107 #define SD_CMD_SWITCH_UHS18V            11
 108
 109 #define SD_CMD_APP_SET_BUS_WIDTH        6
 110 #define SD_CMD_APP_SD_STATUS            13
 111 #define SD_CMD_ERASE_WR_BLK_START       32
 112 #define SD_CMD_ERASE_WR_BLK_END         33
 113 #define SD_CMD_APP_SEND_OP_COND         41
 114 #define SD_CMD_APP_SEND_SCR             51
 115
 116 /* SCR definitions in different words */
 117 #define SD_HIGHSPEED_BUSY       0x00020000
 118 #define SD_HIGHSPEED_SUPPORTED  0x00020000
 119
 120 #define OCR_BUSY                0x80000000
 121 #define OCR_HCS                 0x40000000
 122 #define OCR_VOLTAGE_MASK        0x007FFF80
 123 #define OCR_ACCESS_MODE         0x60000000
 124
 125 #define MMC_ERASE_ARG           0x00000000
 126 #define MMC_SECURE_ERASE_ARG    0x80000000
 127 #define MMC_TRIM_ARG            0x00000001
 128 #define MMC_DISCARD_ARG         0x00000003
 129 #define MMC_SECURE_TRIM1_ARG    0x80000001
 130 #define MMC_SECURE_TRIM2_ARG    0x80008000
 131
 132 #define MMC_STATUS_MASK         (~0x0206BF7F)
 133 #define MMC_STATUS_SWITCH_ERROR (1 << 7)
 134 #define MMC_STATUS_RDY_FOR_DATA (1 << 8)
 135 #define MMC_STATUS_CURR_STATE   (0xf << 9)
 136 #define MMC_STATUS_ERROR        (1 << 19)
 137
 138 #define MMC_STATE_PRG           (7 << 9)
 139
 140 #define MMC_VDD_165_195         0x00000080      /* VDD voltage 1.65 - 1.95 */
 141 #define MMC_VDD_20_21           0x00000100      /* VDD voltage 2.0 ~ 2.1 */
 142 #define MMC_VDD_21_22           0x00000200      /* VDD voltage 2.1 ~ 2.2 */
 143 #define MMC_VDD_22_23           0x00000400      /* VDD voltage 2.2 ~ 2.3 */
 144 #define MMC_VDD_23_24           0x00000800      /* VDD voltage 2.3 ~ 2.4 */
 145 #define MMC_VDD_24_25           0x00001000      /* VDD voltage 2.4 ~ 2.5 */
 146 #define MMC_VDD_25_26           0x00002000      /* VDD voltage 2.5 ~ 2.6 */
 147 #define MMC_VDD_26_27           0x00004000      /* VDD voltage 2.6 ~ 2.7 */
 148 #define MMC_VDD_27_28           0x00008000      /* VDD voltage 2.7 ~ 2.8 */
 149 #define MMC_VDD_28_29           0x00010000      /* VDD voltage 2.8 ~ 2.9 */
 150 #define MMC_VDD_29_30           0x00020000      /* VDD voltage 2.9 ~ 3.0 */
 151 #define MMC_VDD_30_31           0x00040000      /* VDD voltage 3.0 ~ 3.1 */
 152 #define MMC_VDD_31_32           0x00080000      /* VDD voltage 3.1 ~ 3.2 */
 153 #define MMC_VDD_32_33           0x00100000      /* VDD voltage 3.2 ~ 3.3 */
 154 #define MMC_VDD_33_34           0x00200000      /* VDD voltage 3.3 ~ 3.4 */
 155 #define MMC_VDD_34_35           0x00400000      /* VDD voltage 3.4 ~ 3.5 */
 156 #define MMC_VDD_35_36           0x00800000      /* VDD voltage 3.5 ~ 3.6 */
 157
 158 #define MMC_SWITCH_MODE_CMD_SET         0x00 /* Change the command set */
 159 #define MMC_SWITCH_MODE_SET_BITS        0x01 /* Set bits in EXT_CSD byte
 160                                                 addressed by index which are
 161                                                 1 in value field */
 162 #define MMC_SWITCH_MODE_CLEAR_BITS      0x02 /* Clear bits in EXT_CSD byte
 163                                                 addressed by index, which are
 164                                                 1 in value field */
 165 #define MMC_SWITCH_MODE_WRITE_BYTE      0x03 /* Set target byte to value */
 166
 167 #define SD_SWITCH_CHECK         0
 168 #define SD_SWITCH_SWITCH        1
 169
 170 /*
 171  * EXT_CSD fields
 172  */
 173 #define EXT_CSD_ENH_START_ADDR          136     /* R/W */
 174 #define EXT_CSD_ENH_SIZE_MULT           140     /* R/W */
 175 #define EXT_CSD_GP_SIZE_MULT            143     /* R/W */
 176 #define EXT_CSD_PARTITION_SETTING       155     /* R/W */
 177 #define EXT_CSD_PARTITIONS_ATTRIBUTE    156     /* R/W */
 178 #define EXT_CSD_MAX_ENH_SIZE_MULT       157     /* R */
 179 #define EXT_CSD_PARTITIONING_SUPPORT    160     /* RO */
 180 #define EXT_CSD_RST_N_FUNCTION          162     /* R/W */
 181 #define EXT_CSD_BKOPS_EN                163     /* R/W & R/W/E */
 182 #define EXT_CSD_WR_REL_PARAM            166     /* R */
 183 #define EXT_CSD_WR_REL_SET              167     /* R/W */
 184 #define EXT_CSD_RPMB_MULT               168     /* RO */
 185 #define EXT_CSD_ERASE_GROUP_DEF         175     /* R/W */
 186 #define EXT_CSD_BOOT_BUS_WIDTH          177
 187 #define EXT_CSD_PART_CONF               179     /* R/W */
 188 #define EXT_CSD_BUS_WIDTH               183     /* R/W */
 189 #define EXT_CSD_HS_TIMING               185     /* R/W */
 190 #define EXT_CSD_REV                     192     /* RO */
 191 #define EXT_CSD_CARD_TYPE               196     /* RO */
 192 #define EXT_CSD_SEC_CNT                 212     /* RO, 4 bytes */
 193 #define EXT_CSD_HC_WP_GRP_SIZE          221     /* RO */
 194 #define EXT_CSD_HC_ERASE_GRP_SIZE       224     /* RO */
 195 #define EXT_CSD_BOOT_MULT               226     /* RO */
 196 #define EXT_CSD_BKOPS_SUPPORT           502     /* RO */
 197
 198 /*
 199  * EXT_CSD field definitions
 200  */
 201
 202 #define EXT_CSD_CMD_SET_NORMAL          (1 << 0)
 203 #define EXT_CSD_CMD_SET_SECURE          (1 << 1)
 204 #define EXT_CSD_CMD_SET_CPSECURE        (1 << 2)
 205
 206 #define EXT_CSD_CARD_TYPE_26    (1 << 0)        /* Card can run at 26MHz */
 207 #define EXT_CSD_CARD_TYPE_52    (1 << 1)        /* Card can run at 52MHz */
 208 #define EXT_CSD_CARD_TYPE_DDR_1_8V      (1 << 2)
 209 #define EXT_CSD_CARD_TYPE_DDR_1_2V      (1 << 3)
 210 #define EXT_CSD_CARD_TYPE_DDR_52        (EXT_CSD_CARD_TYPE_DDR_1_8V \
 211                                         | EXT_CSD_CARD_TYPE_DDR_1_2V)
 212
 213 #define EXT_CSD_BUS_WIDTH_1     0       /* Card is in 1 bit mode */
 214 #define EXT_CSD_BUS_WIDTH_4     1       /* Card is in 4 bit mode */
 215 #define EXT_CSD_BUS_WIDTH_8     2       /* Card is in 8 bit mode */
 216 #define EXT_CSD_DDR_BUS_WIDTH_4 5       /* Card is in 4 bit DDR mode */
 217 #define EXT_CSD_DDR_BUS_WIDTH_8 6       /* Card is in 8 bit DDR mode */
 218 #define EXT_CSD_DDR_FLAG        BIT(2)  /* Flag for DDR mode */
 219
 220 #define EXT_CSD_TIMING_LEGACY   0       /* no high speed */
 221 #define EXT_CSD_TIMING_HS       1       /* HS */
 222 #define EXT_CSD_BOOT_ACK_ENABLE                 (1 << 6)
 223 #define EXT_CSD_BOOT_PARTITION_ENABLE           (1 << 3)
 224 #define EXT_CSD_PARTITION_ACCESS_ENABLE         (1 << 0)
 225 #define EXT_CSD_PARTITION_ACCESS_DISABLE        (0 << 0)
 226
 227 #define EXT_CSD_BOOT_ACK(x)             (x << 6)
 228 #define EXT_CSD_BOOT_PART_NUM(x)        (x << 3)
 229 #define EXT_CSD_PARTITION_ACCESS(x)     (x << 0)
 230
 231 #define EXT_CSD_EXTRACT_BOOT_ACK(x)             (((x) >> 6) & 0x1)
 232 #define EXT_CSD_EXTRACT_BOOT_PART(x)            (((x) >> 3) & 0x7)
 233 #define EXT_CSD_EXTRACT_PARTITION_ACCESS(x)     ((x) & 0x7)
 234
 235 #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x)  (x << 3)
 236 #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
 237 #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
 238
 239 #define EXT_CSD_PARTITION_SETTING_COMPLETED     (1 << 0)
 240
 241 #define EXT_CSD_ENH_USR         (1 << 0)        /* user data area is enhanced */
 242 #define EXT_CSD_ENH_GP(x)       (1 << ((x)+1))  /* GP part (x+1) is enhanced */
 243
 244 #define EXT_CSD_HS_CTRL_REL     (1 << 0)        /* host controlled WR_REL_SET */
 245
 246 #define EXT_CSD_WR_DATA_REL_USR         (1 << 0)        /* user data area WR_REL */
 247 #define EXT_CSD_WR_DATA_REL_GP(x)       (1 << ((x)+1))  /* GP part (x+1) WR_REL */
 248
 249 #define R1_ILLEGAL_COMMAND              (1 << 22)
 250 #define R1_APP_CMD                      (1 << 5)
 251
 252 #define MMC_RSP_PRESENT (1 << 0)
 253 #define MMC_RSP_136     (1 << 1)                /* 136 bit response */
 254 #define MMC_RSP_CRC     (1 << 2)                /* expect valid crc */
 255 #define MMC_RSP_BUSY    (1 << 3)                /* card may send busy */
 256 #define MMC_RSP_OPCODE  (1 << 4)                /* response contains opcode */
 257
 258 #define MMC_RSP_NONE    (0)
 259 #define MMC_RSP_R1      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 260 #define MMC_RSP_R1b     (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
 261                         MMC_RSP_BUSY)
 262 #define MMC_RSP_R2      (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
 263 #define MMC_RSP_R3      (MMC_RSP_PRESENT)
 264 #define MMC_RSP_R4      (MMC_RSP_PRESENT)
 265 #define MMC_RSP_R5      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 266 #define MMC_RSP_R6      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 267 #define MMC_RSP_R7      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 268
 269 #define MMCPART_NOAVAILABLE     (0xff)
 270 #define PART_ACCESS_MASK        (0x7)
 271 #define PART_SUPPORT            (0x1)
 272 #define ENHNCD_SUPPORT          (0x2)
 273 #define PART_ENH_ATTRIB         (0x1f)
 274
 275 enum mmc_voltage {
 276         MMC_SIGNAL_VOLTAGE_000 = 0,
 277         MMC_SIGNAL_VOLTAGE_120,
 278         MMC_SIGNAL_VOLTAGE_180,
 279         MMC_SIGNAL_VOLTAGE_330
 280 };
 281
 282 /* Maximum block size for MMC */
 283 #define MMC_MAX_BLOCK_LEN       512
 284
 285 /* The number of MMC physical partitions.  These consist of:
 286  * boot partitions (2), general purpose partitions (4) in MMC v4.4.
 287  */
 288 #define MMC_NUM_BOOT_PARTITION  2
 289 #define MMC_PART_RPMB           3       /* RPMB partition number */
 290
 291 /* Driver model support */
 292
 293 /**
 294  * struct mmc_uclass_priv - Holds information about a device used by the uclass
 295  */
 296 struct mmc_uclass_priv {
 297         struct mmc *mmc;
 298 };
 299
 300 /**
 301  * mmc_get_mmc_dev() - get the MMC struct pointer for a device
 302  *
 303  * Provided that the device is already probed and ready for use, this value
 304  * will be available.
 305  *
 306  * @dev:        Device
 307  * @return associated mmc struct pointer if available, else NULL
 308  */
 309 struct mmc *mmc_get_mmc_dev(struct udevice *dev);
 310
 311 /* End of driver model support */
 312
 313 struct mmc_cid {
 314         unsigned long psn;
 315         unsigned short oid;
 316         unsigned char mid;
 317         unsigned char prv;
 318         unsigned char mdt;
 319         char pnm[7];
 320 };
 321
 322 struct mmc_cmd {
 323         ushort cmdidx;
 324         uint resp_type;
 325         uint cmdarg;
 326         uint response[4];
 327 };
 328
 329 struct mmc_data {
 330         union {
 331                 char *dest;
 332                 const char *src; /* src buffers don't get written to */
 333         };
 334         uint flags;
 335         uint blocks;
 336         uint blocksize;
 337 };
 338
 339 /* forward decl. */
 340 struct mmc;
 341
 342 #if CONFIG_IS_ENABLED(DM_MMC)
 343 struct dm_mmc_ops {
 344         /**
 345          * send_cmd() - Send a command to the MMC device
 346          *
 347          * @dev:        Device to receive the command
 348          * @cmd:        Command to send
 349          * @data:       Additional data to send/receive
 350          * @return 0 if OK, -ve on error
 351          */
 352         int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd,
 353                         struct mmc_data *data);
 354
 355         /**
 356          * set_ios() - Set the I/O speed/width for an MMC device
 357          *
 358          * @dev:        Device to update
 359          * @return 0 if OK, -ve on error
 360          */
 361         int (*set_ios)(struct udevice *dev);
 362
 363         /**
 364          * send_init_stream() - send the initialization stream: 74 clock cycles
 365          * This is used after power up before sending the first command
 366          *
 367          * @dev:        Device to update
 368          */
 369         void (*send_init_stream)(struct udevice *dev);
 370
 371         /**
 372          * get_cd() - See whether a card is present
 373          *
 374          * @dev:        Device to check
 375          * @return 0 if not present, 1 if present, -ve on error
 376          */
 377         int (*get_cd)(struct udevice *dev);
 378
 379         /**
 380          * get_wp() - See whether a card has write-protect enabled
 381          *
 382          * @dev:        Device to check
 383          * @return 0 if write-enabled, 1 if write-protected, -ve on error
 384          */
 385         int (*get_wp)(struct udevice *dev);
 386
 387         /**
 388          * execute_tuning() - Start the tuning process
 389          *
 390          * @dev:        Device to start the tuning
 391          * @opcode:     Command opcode to send
 392          * @return 0 if OK, -ve on error
 393          */
 394         int (*execute_tuning)(struct udevice *dev, uint opcode);
 395 };
 396
 397 #define mmc_get_ops(dev)        ((struct dm_mmc_ops *)(dev)->driver->ops)
 398
 399 int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 400                     struct mmc_data *data);
 401 int dm_mmc_set_ios(struct udevice *dev);
 402 void dm_mmc_send_init_stream(struct udevice *dev);
 403 int dm_mmc_get_cd(struct udevice *dev);
 404 int dm_mmc_get_wp(struct udevice *dev);
 405 int dm_mmc_execute_tuning(struct udevice *dev, uint opcode);
 406
 407 /* Transition functions for compatibility */
 408 int mmc_set_ios(struct mmc *mmc);
 409 void mmc_send_init_stream(struct mmc *mmc);
 410 int mmc_getcd(struct mmc *mmc);
 411 int mmc_getwp(struct mmc *mmc);
 412 int mmc_execute_tuning(struct mmc *mmc, uint opcode);
 413
 414 #else
 415 struct mmc_ops {
 416         int (*send_cmd)(struct mmc *mmc,
 417                         struct mmc_cmd *cmd, struct mmc_data *data);
 418         int (*set_ios)(struct mmc *mmc);
 419         int (*init)(struct mmc *mmc);
 420         int (*getcd)(struct mmc *mmc);
 421         int (*getwp)(struct mmc *mmc);
 422 };
 423 #endif
 424
 425 struct mmc_config {
 426         const char *name;
 427 #if !CONFIG_IS_ENABLED(DM_MMC)
 428         const struct mmc_ops *ops;
 429 #endif
 430         uint host_caps;
 431         uint voltages;
 432         uint f_min;
 433         uint f_max;
 434         uint b_max;
 435         unsigned char part_type;
 436 };
 437
 438 struct sd_ssr {
 439         unsigned int au;                /* In sectors */
 440         unsigned int erase_timeout;     /* In milliseconds */
 441         unsigned int erase_offset;      /* In milliseconds */
 442 };
 443
 444 enum bus_mode {
 445         MMC_LEGACY,
 446         SD_LEGACY,
 447         MMC_HS,
 448         SD_HS,
 449         UHS_SDR12,
 450         UHS_SDR25,
 451         UHS_SDR50,
 452         UHS_SDR104,
 453         UHS_DDR50,
 454         MMC_HS_52,
 455         MMC_DDR_52,
 456         MMC_HS_200,
 457         MMC_MODES_END
 458 };
 459
 460 const char *mmc_mode_name(enum bus_mode mode);
 461 void mmc_dump_capabilities(const char *text, uint caps);
 462
 463 static inline bool mmc_is_mode_ddr(enum bus_mode mode)
 464 {
 465         if ((mode == MMC_DDR_52) || (mode == UHS_DDR50))
 466                 return true;
 467         else
 468                 return false;
 469 }
 470
 471 /*
 472  * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device
 473  * with mmc_get_mmc_dev().
 474  *
 475  * TODO struct mmc should be in mmc_private but it's hard to fix right now
 476  */
 477 struct mmc {
 478 #if !CONFIG_IS_ENABLED(BLK)
 479         struct list_head link;
 480 #endif
 481         const struct mmc_config *cfg;   /* provided configuration */
 482         uint version;
 483         void *priv;
 484         uint has_init;
 485         int high_capacity;
 486         bool clk_disable; /* true if the clock can be turned off */
 487         uint bus_width;
 488         uint clock;
 489         enum mmc_voltage signal_voltage;
 490         uint card_caps;
 491         uint ocr;
 492         uint dsr;
 493         uint dsr_imp;
 494         uint scr[2];
 495         uint csd[4];
 496         uint cid[4];
 497         ushort rca;
 498         u8 part_support;
 499         u8 part_attr;
 500         u8 wr_rel_set;
 501         u8 part_config;
 502         uint tran_speed;
 503         uint legacy_speed; /* speed for the legacy mode provided by the card */
 504         uint read_bl_len;
 505         uint write_bl_len;
 506         uint erase_grp_size;    /* in 512-byte sectors */
 507         uint hc_wp_grp_size;    /* in 512-byte sectors */
 508         struct sd_ssr   ssr;    /* SD status register */
 509         u64 capacity;
 510         u64 capacity_user;
 511         u64 capacity_boot;
 512         u64 capacity_rpmb;
 513         u64 capacity_gp[4];
 514         u64 enh_user_start;
 515         u64 enh_user_size;
 516 #if !CONFIG_IS_ENABLED(BLK)
 517         struct blk_desc block_dev;
 518 #endif
 519         char op_cond_pending;   /* 1 if we are waiting on an op_cond command */
 520         char init_in_progress;  /* 1 if we have done mmc_start_init() */
 521         char preinit;           /* start init as early as possible */
 522         int ddr_mode;
 523 #if CONFIG_IS_ENABLED(DM_MMC)
 524         struct udevice *dev;    /* Device for this MMC controller */
 525 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 526         struct udevice *vmmc_supply;    /* Main voltage regulator (Vcc)*/
 527         struct udevice *vqmmc_supply;   /* IO voltage regulator (Vccq)*/
 528 #endif
 529 #endif
 530         u8 *ext_csd;
 531         enum bus_mode selected_mode;
 532 };
 533
 534 struct mmc_hwpart_conf {
 535         struct {
 536                 uint enh_start; /* in 512-byte sectors */
 537                 uint enh_size;  /* in 512-byte sectors, if 0 no enh area */
 538                 unsigned wr_rel_change : 1;
 539                 unsigned wr_rel_set : 1;
 540         } user;
 541         struct {
 542                 uint size;      /* in 512-byte sectors */
 543                 unsigned enhanced : 1;
 544                 unsigned wr_rel_change : 1;
 545                 unsigned wr_rel_set : 1;
 546         } gp_part[4];
 547 };
 548
 549 enum mmc_hwpart_conf_mode {
 550         MMC_HWPART_CONF_CHECK,
 551         MMC_HWPART_CONF_SET,
 552         MMC_HWPART_CONF_COMPLETE,
 553 };
 554
 555 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
 556
 557 /**
 558  * mmc_bind() - Set up a new MMC device ready for probing
 559  *
 560  * A child block device is bound with the IF_TYPE_MMC interface type. This
 561  * allows the device to be used with CONFIG_BLK
 562  *
 563  * @dev:        MMC device to set up
 564  * @mmc:        MMC struct
 565  * @cfg:        MMC configuration
 566  * @return 0 if OK, -ve on error
 567  */
 568 int mmc_bind(struct udevice *dev, struct mmc *mmc,
 569              const struct mmc_config *cfg);
 570 void mmc_destroy(struct mmc *mmc);
 571
 572 /**
 573  * mmc_unbind() - Unbind a MMC device's child block device
 574  *
 575  * @dev:        MMC device
 576  * @return 0 if OK, -ve on error
 577  */
 578 int mmc_unbind(struct udevice *dev);
 579 int mmc_initialize(bd_t *bis);
 580 int mmc_init(struct mmc *mmc);
 581 int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
 582
 583 /**
 584  * mmc_set_clock() - change the bus clock
 585  * @mmc:        MMC struct
 586  * @clock:      bus frequency in Hz
 587  * @disable:    flag indicating if the clock must on or off
 588  * @return 0 if OK, -ve on error
 589  */
 590 int mmc_set_clock(struct mmc *mmc, uint clock, bool disable);
 591
 592 struct mmc *find_mmc_device(int dev_num);
 593 int mmc_set_dev(int dev_num);
 594 void print_mmc_devices(char separator);
 595
 596 /**
 597  * get_mmc_num() - get the total MMC device number
 598  *
 599  * @return 0 if there is no MMC device, else the number of devices
 600  */
 601 int get_mmc_num(void);
 602 int mmc_switch_part(struct mmc *mmc, unsigned int part_num);
 603 int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
 604                       enum mmc_hwpart_conf_mode mode);
 605
 606 #if !CONFIG_IS_ENABLED(DM_MMC)
 607 int mmc_getcd(struct mmc *mmc);
 608 int board_mmc_getcd(struct mmc *mmc);
 609 int mmc_getwp(struct mmc *mmc);
 610 int board_mmc_getwp(struct mmc *mmc);
 611 #endif
 612
 613 int mmc_set_dsr(struct mmc *mmc, u16 val);
 614 /* Function to change the size of boot partition and rpmb partitions */
 615 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
 616                                         unsigned long rpmbsize);
 617 /* Function to modify the PARTITION_CONFIG field of EXT_CSD */
 618 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
 619 /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
 620 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
 621 /* Function to modify the RST_n_FUNCTION field of EXT_CSD */
 622 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
 623 /* Functions to read / write the RPMB partition */
 624 int mmc_rpmb_set_key(struct mmc *mmc, void *key);
 625 int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
 626 int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
 627                   unsigned short cnt, unsigned char *key);
 628 int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
 629                    unsigned short cnt, unsigned char *key);
 630 #ifdef CONFIG_CMD_BKOPS_ENABLE
 631 int mmc_set_bkops_enable(struct mmc *mmc);
 632 #endif
 633
 634 /**
 635  * Start device initialization and return immediately; it does not block on
 636  * polling OCR (operation condition register) status.  Then you should call
 637  * mmc_init, which would block on polling OCR status and complete the device
 638  * initializatin.
 639  *
 640  * @param mmc   Pointer to a MMC device struct
 641  * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error.
 642  */
 643 int mmc_start_init(struct mmc *mmc);
 644
 645 /**
 646  * Set preinit flag of mmc device.
 647  *
 648  * This will cause the device to be pre-inited during mmc_initialize(),
 649  * which may save boot time if the device is not accessed until later.
 650  * Some eMMC devices take 200-300ms to init, but unfortunately they
 651  * must be sent a series of commands to even get them to start preparing
 652  * for operation.
 653  *
 654  * @param mmc           Pointer to a MMC device struct
 655  * @param preinit       preinit flag value
 656  */
 657 void mmc_set_preinit(struct mmc *mmc, int preinit);
 658
 659 #ifdef CONFIG_MMC_SPI
 660 #define mmc_host_is_spi(mmc)    ((mmc)->cfg->host_caps & MMC_MODE_SPI)
 661 #else
 662 #define mmc_host_is_spi(mmc)    0
 663 #endif
 664 struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
 665
 666 void board_mmc_power_init(void);
 667 int board_mmc_init(bd_t *bis);
 668 int cpu_mmc_init(bd_t *bis);
 669 int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
 670 int mmc_get_env_dev(void);
 671
 672 /* Set block count limit because of 16 bit register limit on some hardware*/
 673 #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
 674 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
 675 #endif
 676
 677 /**
 678  * mmc_get_blk_desc() - Get the block descriptor for an MMC device
 679  *
 680  * @mmc:        MMC device
 681  * @return block device if found, else NULL
 682  */
 683 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc);
 684
 685 #endif /* _MMC_H_ */