include/mmc.h

   1 /*
   2  * Copyright 2008,2010 Freescale Semiconductor, Inc
   3  * Andy Fleming
   4  *
   5  * Based (loosely) on the Linux code
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef _MMC_H_
  11 #define _MMC_H_
  12
  13 #include <linux/list.h>
  14 #include <linux/sizes.h>
  15 #include <linux/compiler.h>
  16 #include <part.h>
  17
  18 /* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
  19 #define SD_VERSION_SD   (1U << 31)
  20 #define MMC_VERSION_MMC (1U << 30)
  21
  22 #define MAKE_SDMMC_VERSION(a, b, c)     \
  23         ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c))
  24 #define MAKE_SD_VERSION(a, b, c)        \
  25         (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
  26 #define MAKE_MMC_VERSION(a, b, c)       \
  27         (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))
  28
  29 #define EXTRACT_SDMMC_MAJOR_VERSION(x)  \
  30         (((u32)(x) >> 16) & 0xff)
  31 #define EXTRACT_SDMMC_MINOR_VERSION(x)  \
  32         (((u32)(x) >> 8) & 0xff)
  33 #define EXTRACT_SDMMC_CHANGE_VERSION(x) \
  34         ((u32)(x) & 0xff)
  35
  36 #define SD_VERSION_3            MAKE_SD_VERSION(3, 0, 0)
  37 #define SD_VERSION_2            MAKE_SD_VERSION(2, 0, 0)
  38 #define SD_VERSION_1_0          MAKE_SD_VERSION(1, 0, 0)
  39 #define SD_VERSION_1_10         MAKE_SD_VERSION(1, 10, 0)
  40
  41 #define MMC_VERSION_UNKNOWN     MAKE_MMC_VERSION(0, 0, 0)
  42 #define MMC_VERSION_1_2         MAKE_MMC_VERSION(1, 2, 0)
  43 #define MMC_VERSION_1_4         MAKE_MMC_VERSION(1, 4, 0)
  44 #define MMC_VERSION_2_2         MAKE_MMC_VERSION(2, 2, 0)
  45 #define MMC_VERSION_3           MAKE_MMC_VERSION(3, 0, 0)
  46 #define MMC_VERSION_4           MAKE_MMC_VERSION(4, 0, 0)
  47 #define MMC_VERSION_4_1         MAKE_MMC_VERSION(4, 1, 0)
  48 #define MMC_VERSION_4_2         MAKE_MMC_VERSION(4, 2, 0)
  49 #define MMC_VERSION_4_3         MAKE_MMC_VERSION(4, 3, 0)
  50 #define MMC_VERSION_4_41        MAKE_MMC_VERSION(4, 4, 1)
  51 #define MMC_VERSION_4_5         MAKE_MMC_VERSION(4, 5, 0)
  52 #define MMC_VERSION_5_0         MAKE_MMC_VERSION(5, 0, 0)
  53 #define MMC_VERSION_5_1         MAKE_MMC_VERSION(5, 1, 0)
  54
  55 #define MMC_CAP(mode)           (1 << mode)
  56 #define MMC_MODE_HS             (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS))
  57 #define MMC_MODE_HS_52MHz       MMC_CAP(MMC_HS_52)
  58 #define MMC_MODE_DDR_52MHz      MMC_CAP(MMC_DDR_52)
  59 #define MMC_MODE_HS200          MMC_CAP(MMC_HS_200)
  60
  61 #define MMC_MODE_8BIT           BIT(30)
  62 #define MMC_MODE_4BIT           BIT(29)
  63 #define MMC_MODE_1BIT           BIT(28)
  64 #define MMC_MODE_SPI            BIT(27)
  65
  66
  67 #define SD_DATA_4BIT    0x00040000
  68
  69 #define IS_SD(x)        ((x)->version & SD_VERSION_SD)
  70 #define IS_MMC(x)       ((x)->version & MMC_VERSION_MMC)
  71
  72 #define MMC_DATA_READ           1
  73 #define MMC_DATA_WRITE          2
  74
  75 #define MMC_CMD_GO_IDLE_STATE           0
  76 #define MMC_CMD_SEND_OP_COND            1
  77 #define MMC_CMD_ALL_SEND_CID            2
  78 #define MMC_CMD_SET_RELATIVE_ADDR       3
  79 #define MMC_CMD_SET_DSR                 4
  80 #define MMC_CMD_SWITCH                  6
  81 #define MMC_CMD_SELECT_CARD             7
  82 #define MMC_CMD_SEND_EXT_CSD            8
  83 #define MMC_CMD_SEND_CSD                9
  84 #define MMC_CMD_SEND_CID                10
  85 #define MMC_CMD_STOP_TRANSMISSION       12
  86 #define MMC_CMD_SEND_STATUS             13
  87 #define MMC_CMD_SET_BLOCKLEN            16
  88 #define MMC_CMD_READ_SINGLE_BLOCK       17
  89 #define MMC_CMD_READ_MULTIPLE_BLOCK     18
  90 #define MMC_CMD_SEND_TUNING_BLOCK               19
  91 #define MMC_CMD_SEND_TUNING_BLOCK_HS200 21
  92 #define MMC_CMD_SET_BLOCK_COUNT         23
  93 #define MMC_CMD_WRITE_SINGLE_BLOCK      24
  94 #define MMC_CMD_WRITE_MULTIPLE_BLOCK    25
  95 #define MMC_CMD_ERASE_GROUP_START       35
  96 #define MMC_CMD_ERASE_GROUP_END         36
  97 #define MMC_CMD_ERASE                   38
  98 #define MMC_CMD_APP_CMD                 55
  99 #define MMC_CMD_SPI_READ_OCR            58
 100 #define MMC_CMD_SPI_CRC_ON_OFF          59
 101 #define MMC_CMD_RES_MAN                 62
 102
 103 #define MMC_CMD62_ARG1                  0xefac62ec
 104 #define MMC_CMD62_ARG2                  0xcbaea7
 105
 106
 107 #define SD_CMD_SEND_RELATIVE_ADDR       3
 108 #define SD_CMD_SWITCH_FUNC              6
 109 #define SD_CMD_SEND_IF_COND             8
 110 #define SD_CMD_SWITCH_UHS18V            11
 111
 112 #define SD_CMD_APP_SET_BUS_WIDTH        6
 113 #define SD_CMD_APP_SD_STATUS            13
 114 #define SD_CMD_ERASE_WR_BLK_START       32
 115 #define SD_CMD_ERASE_WR_BLK_END         33
 116 #define SD_CMD_APP_SEND_OP_COND         41
 117 #define SD_CMD_APP_SEND_SCR             51
 118
 119 static inline bool mmc_is_tuning_cmd(uint cmdidx)
 120 {
 121         if ((cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) ||
 122             (cmdidx == MMC_CMD_SEND_TUNING_BLOCK))
 123                 return true;
 124         return false;
 125 }
 126
 127 /* SCR definitions in different words */
 128 #define SD_HIGHSPEED_BUSY       0x00020000
 129 #define SD_HIGHSPEED_SUPPORTED  0x00020000
 130
 131 #define UHS_SDR12_BUS_SPEED     0
 132 #define HIGH_SPEED_BUS_SPEED    1
 133 #define UHS_SDR25_BUS_SPEED     1
 134 #define UHS_SDR50_BUS_SPEED     2
 135 #define UHS_SDR104_BUS_SPEED    3
 136 #define UHS_DDR50_BUS_SPEED     4
 137
 138 #define SD_MODE_UHS_SDR12       BIT(UHS_SDR12_BUS_SPEED)
 139 #define SD_MODE_UHS_SDR25       BIT(UHS_SDR25_BUS_SPEED)
 140 #define SD_MODE_UHS_SDR50       BIT(UHS_SDR50_BUS_SPEED)
 141 #define SD_MODE_UHS_SDR104      BIT(UHS_SDR104_BUS_SPEED)
 142 #define SD_MODE_UHS_DDR50       BIT(UHS_DDR50_BUS_SPEED)
 143
 144 #define OCR_BUSY                0x80000000
 145 #define OCR_HCS                 0x40000000
 146 #define OCR_S18R                0x1000000
 147 #define OCR_VOLTAGE_MASK        0x007FFF80
 148 #define OCR_ACCESS_MODE         0x60000000
 149
 150 #define MMC_ERASE_ARG           0x00000000
 151 #define MMC_SECURE_ERASE_ARG    0x80000000
 152 #define MMC_TRIM_ARG            0x00000001
 153 #define MMC_DISCARD_ARG         0x00000003
 154 #define MMC_SECURE_TRIM1_ARG    0x80000001
 155 #define MMC_SECURE_TRIM2_ARG    0x80008000
 156
 157 #define MMC_STATUS_MASK         (~0x0206BF7F)
 158 #define MMC_STATUS_SWITCH_ERROR (1 << 7)
 159 #define MMC_STATUS_RDY_FOR_DATA (1 << 8)
 160 #define MMC_STATUS_CURR_STATE   (0xf << 9)
 161 #define MMC_STATUS_ERROR        (1 << 19)
 162
 163 #define MMC_STATE_PRG           (7 << 9)
 164
 165 #define MMC_VDD_165_195         0x00000080      /* VDD voltage 1.65 - 1.95 */
 166 #define MMC_VDD_20_21           0x00000100      /* VDD voltage 2.0 ~ 2.1 */
 167 #define MMC_VDD_21_22           0x00000200      /* VDD voltage 2.1 ~ 2.2 */
 168 #define MMC_VDD_22_23           0x00000400      /* VDD voltage 2.2 ~ 2.3 */
 169 #define MMC_VDD_23_24           0x00000800      /* VDD voltage 2.3 ~ 2.4 */
 170 #define MMC_VDD_24_25           0x00001000      /* VDD voltage 2.4 ~ 2.5 */
 171 #define MMC_VDD_25_26           0x00002000      /* VDD voltage 2.5 ~ 2.6 */
 172 #define MMC_VDD_26_27           0x00004000      /* VDD voltage 2.6 ~ 2.7 */
 173 #define MMC_VDD_27_28           0x00008000      /* VDD voltage 2.7 ~ 2.8 */
 174 #define MMC_VDD_28_29           0x00010000      /* VDD voltage 2.8 ~ 2.9 */
 175 #define MMC_VDD_29_30           0x00020000      /* VDD voltage 2.9 ~ 3.0 */
 176 #define MMC_VDD_30_31           0x00040000      /* VDD voltage 3.0 ~ 3.1 */
 177 #define MMC_VDD_31_32           0x00080000      /* VDD voltage 3.1 ~ 3.2 */
 178 #define MMC_VDD_32_33           0x00100000      /* VDD voltage 3.2 ~ 3.3 */
 179 #define MMC_VDD_33_34           0x00200000      /* VDD voltage 3.3 ~ 3.4 */
 180 #define MMC_VDD_34_35           0x00400000      /* VDD voltage 3.4 ~ 3.5 */
 181 #define MMC_VDD_35_36           0x00800000      /* VDD voltage 3.5 ~ 3.6 */
 182
 183 #define MMC_SWITCH_MODE_CMD_SET         0x00 /* Change the command set */
 184 #define MMC_SWITCH_MODE_SET_BITS        0x01 /* Set bits in EXT_CSD byte
 185                                                 addressed by index which are
 186                                                 1 in value field */
 187 #define MMC_SWITCH_MODE_CLEAR_BITS      0x02 /* Clear bits in EXT_CSD byte
 188                                                 addressed by index, which are
 189                                                 1 in value field */
 190 #define MMC_SWITCH_MODE_WRITE_BYTE      0x03 /* Set target byte to value */
 191
 192 #define SD_SWITCH_CHECK         0
 193 #define SD_SWITCH_SWITCH        1
 194
 195 /*
 196  * EXT_CSD fields
 197  */
 198 #define EXT_CSD_ENH_START_ADDR          136     /* R/W */
 199 #define EXT_CSD_ENH_SIZE_MULT           140     /* R/W */
 200 #define EXT_CSD_GP_SIZE_MULT            143     /* R/W */
 201 #define EXT_CSD_PARTITION_SETTING       155     /* R/W */
 202 #define EXT_CSD_PARTITIONS_ATTRIBUTE    156     /* R/W */
 203 #define EXT_CSD_MAX_ENH_SIZE_MULT       157     /* R */
 204 #define EXT_CSD_PARTITIONING_SUPPORT    160     /* RO */
 205 #define EXT_CSD_RST_N_FUNCTION          162     /* R/W */
 206 #define EXT_CSD_BKOPS_EN                163     /* R/W & R/W/E */
 207 #define EXT_CSD_WR_REL_PARAM            166     /* R */
 208 #define EXT_CSD_WR_REL_SET              167     /* R/W */
 209 #define EXT_CSD_RPMB_MULT               168     /* RO */
 210 #define EXT_CSD_ERASE_GROUP_DEF         175     /* R/W */
 211 #define EXT_CSD_BOOT_BUS_WIDTH          177
 212 #define EXT_CSD_PART_CONF               179     /* R/W */
 213 #define EXT_CSD_BUS_WIDTH               183     /* R/W */
 214 #define EXT_CSD_HS_TIMING               185     /* R/W */
 215 #define EXT_CSD_REV                     192     /* RO */
 216 #define EXT_CSD_CARD_TYPE               196     /* RO */
 217 #define EXT_CSD_SEC_CNT                 212     /* RO, 4 bytes */
 218 #define EXT_CSD_HC_WP_GRP_SIZE          221     /* RO */
 219 #define EXT_CSD_HC_ERASE_GRP_SIZE       224     /* RO */
 220 #define EXT_CSD_BOOT_MULT               226     /* RO */
 221 #define EXT_CSD_BKOPS_SUPPORT           502     /* RO */
 222
 223 /*
 224  * EXT_CSD field definitions
 225  */
 226
 227 #define EXT_CSD_CMD_SET_NORMAL          (1 << 0)
 228 #define EXT_CSD_CMD_SET_SECURE          (1 << 1)
 229 #define EXT_CSD_CMD_SET_CPSECURE        (1 << 2)
 230
 231 #define EXT_CSD_CARD_TYPE_26    (1 << 0)        /* Card can run at 26MHz */
 232 #define EXT_CSD_CARD_TYPE_52    (1 << 1)        /* Card can run at 52MHz */
 233 #define EXT_CSD_CARD_TYPE_DDR_1_8V      (1 << 2)
 234 #define EXT_CSD_CARD_TYPE_DDR_1_2V      (1 << 3)
 235 #define EXT_CSD_CARD_TYPE_DDR_52        (EXT_CSD_CARD_TYPE_DDR_1_8V \
 236                                         | EXT_CSD_CARD_TYPE_DDR_1_2V)
 237
 238 #define EXT_CSD_CARD_TYPE_HS200_1_8V    BIT(4)  /* Card can run at 200MHz */
 239                                                 /* SDR mode @1.8V I/O */
 240 #define EXT_CSD_CARD_TYPE_HS200_1_2V    BIT(5)  /* Card can run at 200MHz */
 241                                                 /* SDR mode @1.2V I/O */
 242 #define EXT_CSD_CARD_TYPE_HS200         (EXT_CSD_CARD_TYPE_HS200_1_8V | \
 243                                          EXT_CSD_CARD_TYPE_HS200_1_2V)
 244
 245 #define EXT_CSD_BUS_WIDTH_1     0       /* Card is in 1 bit mode */
 246 #define EXT_CSD_BUS_WIDTH_4     1       /* Card is in 4 bit mode */
 247 #define EXT_CSD_BUS_WIDTH_8     2       /* Card is in 8 bit mode */
 248 #define EXT_CSD_DDR_BUS_WIDTH_4 5       /* Card is in 4 bit DDR mode */
 249 #define EXT_CSD_DDR_BUS_WIDTH_8 6       /* Card is in 8 bit DDR mode */
 250 #define EXT_CSD_DDR_FLAG        BIT(2)  /* Flag for DDR mode */
 251
 252 #define EXT_CSD_TIMING_LEGACY   0       /* no high speed */
 253 #define EXT_CSD_TIMING_HS       1       /* HS */
 254 #define EXT_CSD_TIMING_HS200    2       /* HS200 */
 255
 256 #define EXT_CSD_BOOT_ACK_ENABLE                 (1 << 6)
 257 #define EXT_CSD_BOOT_PARTITION_ENABLE           (1 << 3)
 258 #define EXT_CSD_PARTITION_ACCESS_ENABLE         (1 << 0)
 259 #define EXT_CSD_PARTITION_ACCESS_DISABLE        (0 << 0)
 260
 261 #define EXT_CSD_BOOT_ACK(x)             (x << 6)
 262 #define EXT_CSD_BOOT_PART_NUM(x)        (x << 3)
 263 #define EXT_CSD_PARTITION_ACCESS(x)     (x << 0)
 264
 265 #define EXT_CSD_EXTRACT_BOOT_ACK(x)             (((x) >> 6) & 0x1)
 266 #define EXT_CSD_EXTRACT_BOOT_PART(x)            (((x) >> 3) & 0x7)
 267 #define EXT_CSD_EXTRACT_PARTITION_ACCESS(x)     ((x) & 0x7)
 268
 269 #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x)  (x << 3)
 270 #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
 271 #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
 272
 273 #define EXT_CSD_PARTITION_SETTING_COMPLETED     (1 << 0)
 274
 275 #define EXT_CSD_ENH_USR         (1 << 0)        /* user data area is enhanced */
 276 #define EXT_CSD_ENH_GP(x)       (1 << ((x)+1))  /* GP part (x+1) is enhanced */
 277
 278 #define EXT_CSD_HS_CTRL_REL     (1 << 0)        /* host controlled WR_REL_SET */
 279
 280 #define EXT_CSD_WR_DATA_REL_USR         (1 << 0)        /* user data area WR_REL */
 281 #define EXT_CSD_WR_DATA_REL_GP(x)       (1 << ((x)+1))  /* GP part (x+1) WR_REL */
 282
 283 #define R1_ILLEGAL_COMMAND              (1 << 22)
 284 #define R1_APP_CMD                      (1 << 5)
 285
 286 #define MMC_RSP_PRESENT (1 << 0)
 287 #define MMC_RSP_136     (1 << 1)                /* 136 bit response */
 288 #define MMC_RSP_CRC     (1 << 2)                /* expect valid crc */
 289 #define MMC_RSP_BUSY    (1 << 3)                /* card may send busy */
 290 #define MMC_RSP_OPCODE  (1 << 4)                /* response contains opcode */
 291
 292 #define MMC_RSP_NONE    (0)
 293 #define MMC_RSP_R1      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 294 #define MMC_RSP_R1b     (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
 295                         MMC_RSP_BUSY)
 296 #define MMC_RSP_R2      (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
 297 #define MMC_RSP_R3      (MMC_RSP_PRESENT)
 298 #define MMC_RSP_R4      (MMC_RSP_PRESENT)
 299 #define MMC_RSP_R5      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 300 #define MMC_RSP_R6      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 301 #define MMC_RSP_R7      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 302
 303 #define MMCPART_NOAVAILABLE     (0xff)
 304 #define PART_ACCESS_MASK        (0x7)
 305 #define PART_SUPPORT            (0x1)
 306 #define ENHNCD_SUPPORT          (0x2)
 307 #define PART_ENH_ATTRIB         (0x1f)
 308
 309 enum mmc_voltage {
 310         MMC_SIGNAL_VOLTAGE_000 = 0,
 311         MMC_SIGNAL_VOLTAGE_120,
 312         MMC_SIGNAL_VOLTAGE_180,
 313         MMC_SIGNAL_VOLTAGE_330
 314 };
 315
 316 /* Maximum block size for MMC */
 317 #define MMC_MAX_BLOCK_LEN       512
 318
 319 /* The number of MMC physical partitions.  These consist of:
 320  * boot partitions (2), general purpose partitions (4) in MMC v4.4.
 321  */
 322 #define MMC_NUM_BOOT_PARTITION  2
 323 #define MMC_PART_RPMB           3       /* RPMB partition number */
 324
 325 /* Driver model support */
 326
 327 /**
 328  * struct mmc_uclass_priv - Holds information about a device used by the uclass
 329  */
 330 struct mmc_uclass_priv {
 331         struct mmc *mmc;
 332 };
 333
 334 /**
 335  * mmc_get_mmc_dev() - get the MMC struct pointer for a device
 336  *
 337  * Provided that the device is already probed and ready for use, this value
 338  * will be available.
 339  *
 340  * @dev:        Device
 341  * @return associated mmc struct pointer if available, else NULL
 342  */
 343 struct mmc *mmc_get_mmc_dev(struct udevice *dev);
 344
 345 /* End of driver model support */
 346
 347 struct mmc_cid {
 348         unsigned long psn;
 349         unsigned short oid;
 350         unsigned char mid;
 351         unsigned char prv;
 352         unsigned char mdt;
 353         char pnm[7];
 354 };
 355
 356 struct mmc_cmd {
 357         ushort cmdidx;
 358         uint resp_type;
 359         uint cmdarg;
 360         uint response[4];
 361 };
 362
 363 struct mmc_data {
 364         union {
 365                 char *dest;
 366                 const char *src; /* src buffers don't get written to */
 367         };
 368         uint flags;
 369         uint blocks;
 370         uint blocksize;
 371 };
 372
 373 /* forward decl. */
 374 struct mmc;
 375
 376 #if CONFIG_IS_ENABLED(DM_MMC)
 377 struct dm_mmc_ops {
 378         /**
 379          * send_cmd() - Send a command to the MMC device
 380          *
 381          * @dev:        Device to receive the command
 382          * @cmd:        Command to send
 383          * @data:       Additional data to send/receive
 384          * @return 0 if OK, -ve on error
 385          */
 386         int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd,
 387                         struct mmc_data *data);
 388
 389         /**
 390          * set_ios() - Set the I/O speed/width for an MMC device
 391          *
 392          * @dev:        Device to update
 393          * @return 0 if OK, -ve on error
 394          */
 395         int (*set_ios)(struct udevice *dev);
 396
 397         /**
 398          * send_init_stream() - send the initialization stream: 74 clock cycles
 399          * This is used after power up before sending the first command
 400          *
 401          * @dev:        Device to update
 402          */
 403         void (*send_init_stream)(struct udevice *dev);
 404
 405         /**
 406          * get_cd() - See whether a card is present
 407          *
 408          * @dev:        Device to check
 409          * @return 0 if not present, 1 if present, -ve on error
 410          */
 411         int (*get_cd)(struct udevice *dev);
 412
 413         /**
 414          * get_wp() - See whether a card has write-protect enabled
 415          *
 416          * @dev:        Device to check
 417          * @return 0 if write-enabled, 1 if write-protected, -ve on error
 418          */
 419         int (*get_wp)(struct udevice *dev);
 420
 421         /**
 422          * execute_tuning() - Start the tuning process
 423          *
 424          * @dev:        Device to start the tuning
 425          * @opcode:     Command opcode to send
 426          * @return 0 if OK, -ve on error
 427          */
 428         int (*execute_tuning)(struct udevice *dev, uint opcode);
 429
 430         /**
 431          * wait_dat0() - wait until dat0 is in the target state
 432          *              (CLK must be running during the wait)
 433          *
 434          * @dev:        Device to check
 435          * @state:      target state
 436          * @timeout:    timeout in us
 437          * @return 0 if dat0 is in the target state, -ve on error
 438          */
 439         int (*wait_dat0)(struct udevice *dev, int state, int timeout);
 440 };
 441
 442 #define mmc_get_ops(dev)        ((struct dm_mmc_ops *)(dev)->driver->ops)
 443
 444 int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 445                     struct mmc_data *data);
 446 int dm_mmc_set_ios(struct udevice *dev);
 447 void dm_mmc_send_init_stream(struct udevice *dev);
 448 int dm_mmc_get_cd(struct udevice *dev);
 449 int dm_mmc_get_wp(struct udevice *dev);
 450 int dm_mmc_execute_tuning(struct udevice *dev, uint opcode);
 451 int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout);
 452
 453 /* Transition functions for compatibility */
 454 int mmc_set_ios(struct mmc *mmc);
 455 void mmc_send_init_stream(struct mmc *mmc);
 456 int mmc_getcd(struct mmc *mmc);
 457 int mmc_getwp(struct mmc *mmc);
 458 int mmc_execute_tuning(struct mmc *mmc, uint opcode);
 459 int mmc_wait_dat0(struct mmc *mmc, int state, int timeout);
 460
 461 #else
 462 struct mmc_ops {
 463         int (*send_cmd)(struct mmc *mmc,
 464                         struct mmc_cmd *cmd, struct mmc_data *data);
 465         int (*set_ios)(struct mmc *mmc);
 466         int (*init)(struct mmc *mmc);
 467         int (*getcd)(struct mmc *mmc);
 468         int (*getwp)(struct mmc *mmc);
 469 };
 470 #endif
 471
 472 struct mmc_config {
 473         const char *name;
 474 #if !CONFIG_IS_ENABLED(DM_MMC)
 475         const struct mmc_ops *ops;
 476 #endif
 477         uint host_caps;
 478         uint voltages;
 479         uint f_min;
 480         uint f_max;
 481         uint b_max;
 482         unsigned char part_type;
 483 };
 484
 485 struct sd_ssr {
 486         unsigned int au;                /* In sectors */
 487         unsigned int erase_timeout;     /* In milliseconds */
 488         unsigned int erase_offset;      /* In milliseconds */
 489 };
 490
 491 enum bus_mode {
 492         MMC_LEGACY,
 493         SD_LEGACY,
 494         MMC_HS,
 495         SD_HS,
 496         UHS_SDR12,
 497         UHS_SDR25,
 498         UHS_SDR50,
 499         UHS_SDR104,
 500         UHS_DDR50,
 501         MMC_HS_52,
 502         MMC_DDR_52,
 503         MMC_HS_200,
 504         MMC_MODES_END
 505 };
 506
 507 const char *mmc_mode_name(enum bus_mode mode);
 508 void mmc_dump_capabilities(const char *text, uint caps);
 509
 510 static inline bool mmc_is_mode_ddr(enum bus_mode mode)
 511 {
 512         if ((mode == MMC_DDR_52) || (mode == UHS_DDR50))
 513                 return true;
 514         else
 515                 return false;
 516 }
 517
 518 #define UHS_CAPS (MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) | \
 519                   MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_SDR104) | \
 520                   MMC_CAP(UHS_DDR50))
 521
 522 static inline bool supports_uhs(uint caps)
 523 {
 524         return (caps & UHS_CAPS) ? true : false;
 525 }
 526
 527 /*
 528  * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device
 529  * with mmc_get_mmc_dev().
 530  *
 531  * TODO struct mmc should be in mmc_private but it's hard to fix right now
 532  */
 533 struct mmc {
 534 #if !CONFIG_IS_ENABLED(BLK)
 535         struct list_head link;
 536 #endif
 537         const struct mmc_config *cfg;   /* provided configuration */
 538         uint version;
 539         void *priv;
 540         uint has_init;
 541         int high_capacity;
 542         bool clk_disable; /* true if the clock can be turned off */
 543         uint bus_width;
 544         uint clock;
 545         enum mmc_voltage signal_voltage;
 546         uint card_caps;
 547         uint ocr;
 548         uint dsr;
 549         uint dsr_imp;
 550         uint scr[2];
 551         uint csd[4];
 552         uint cid[4];
 553         ushort rca;
 554         u8 part_support;
 555         u8 part_attr;
 556         u8 wr_rel_set;
 557         u8 part_config;
 558         uint tran_speed;
 559         uint legacy_speed; /* speed for the legacy mode provided by the card */
 560         uint read_bl_len;
 561         uint write_bl_len;
 562         uint erase_grp_size;    /* in 512-byte sectors */
 563         uint hc_wp_grp_size;    /* in 512-byte sectors */
 564         struct sd_ssr   ssr;    /* SD status register */
 565         u64 capacity;
 566         u64 capacity_user;
 567         u64 capacity_boot;
 568         u64 capacity_rpmb;
 569         u64 capacity_gp[4];
 570         u64 enh_user_start;
 571         u64 enh_user_size;
 572 #if !CONFIG_IS_ENABLED(BLK)
 573         struct blk_desc block_dev;
 574 #endif
 575         char op_cond_pending;   /* 1 if we are waiting on an op_cond command */
 576         char init_in_progress;  /* 1 if we have done mmc_start_init() */
 577         char preinit;           /* start init as early as possible */
 578         int ddr_mode;
 579 #if CONFIG_IS_ENABLED(DM_MMC)
 580         struct udevice *dev;    /* Device for this MMC controller */
 581 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 582         struct udevice *vmmc_supply;    /* Main voltage regulator (Vcc)*/
 583         struct udevice *vqmmc_supply;   /* IO voltage regulator (Vccq)*/
 584 #endif
 585 #endif
 586         u8 *ext_csd;
 587         enum bus_mode selected_mode;
 588 };
 589
 590 struct mmc_hwpart_conf {
 591         struct {
 592                 uint enh_start; /* in 512-byte sectors */
 593                 uint enh_size;  /* in 512-byte sectors, if 0 no enh area */
 594                 unsigned wr_rel_change : 1;
 595                 unsigned wr_rel_set : 1;
 596         } user;
 597         struct {
 598                 uint size;      /* in 512-byte sectors */
 599                 unsigned enhanced : 1;
 600                 unsigned wr_rel_change : 1;
 601                 unsigned wr_rel_set : 1;
 602         } gp_part[4];
 603 };
 604
 605 enum mmc_hwpart_conf_mode {
 606         MMC_HWPART_CONF_CHECK,
 607         MMC_HWPART_CONF_SET,
 608         MMC_HWPART_CONF_COMPLETE,
 609 };
 610
 611 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
 612
 613 /**
 614  * mmc_bind() - Set up a new MMC device ready for probing
 615  *
 616  * A child block device is bound with the IF_TYPE_MMC interface type. This
 617  * allows the device to be used with CONFIG_BLK
 618  *
 619  * @dev:        MMC device to set up
 620  * @mmc:        MMC struct
 621  * @cfg:        MMC configuration
 622  * @return 0 if OK, -ve on error
 623  */
 624 int mmc_bind(struct udevice *dev, struct mmc *mmc,
 625              const struct mmc_config *cfg);
 626 void mmc_destroy(struct mmc *mmc);
 627
 628 /**
 629  * mmc_unbind() - Unbind a MMC device's child block device
 630  *
 631  * @dev:        MMC device
 632  * @return 0 if OK, -ve on error
 633  */
 634 int mmc_unbind(struct udevice *dev);
 635 int mmc_initialize(bd_t *bis);
 636 int mmc_init(struct mmc *mmc);
 637 int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
 638
 639 /**
 640  * mmc_set_clock() - change the bus clock
 641  * @mmc:        MMC struct
 642  * @clock:      bus frequency in Hz
 643  * @disable:    flag indicating if the clock must on or off
 644  * @return 0 if OK, -ve on error
 645  */
 646 int mmc_set_clock(struct mmc *mmc, uint clock, bool disable);
 647
 648 struct mmc *find_mmc_device(int dev_num);
 649 int mmc_set_dev(int dev_num);
 650 void print_mmc_devices(char separator);
 651
 652 /**
 653  * get_mmc_num() - get the total MMC device number
 654  *
 655  * @return 0 if there is no MMC device, else the number of devices
 656  */
 657 int get_mmc_num(void);
 658 int mmc_switch_part(struct mmc *mmc, unsigned int part_num);
 659 int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
 660                       enum mmc_hwpart_conf_mode mode);
 661
 662 #if !CONFIG_IS_ENABLED(DM_MMC)
 663 int mmc_getcd(struct mmc *mmc);
 664 int board_mmc_getcd(struct mmc *mmc);
 665 int mmc_getwp(struct mmc *mmc);
 666 int board_mmc_getwp(struct mmc *mmc);
 667 #endif
 668
 669 int mmc_set_dsr(struct mmc *mmc, u16 val);
 670 /* Function to change the size of boot partition and rpmb partitions */
 671 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
 672                                         unsigned long rpmbsize);
 673 /* Function to modify the PARTITION_CONFIG field of EXT_CSD */
 674 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
 675 /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
 676 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
 677 /* Function to modify the RST_n_FUNCTION field of EXT_CSD */
 678 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
 679 /* Functions to read / write the RPMB partition */
 680 int mmc_rpmb_set_key(struct mmc *mmc, void *key);
 681 int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
 682 int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
 683                   unsigned short cnt, unsigned char *key);
 684 int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
 685                    unsigned short cnt, unsigned char *key);
 686 #ifdef CONFIG_CMD_BKOPS_ENABLE
 687 int mmc_set_bkops_enable(struct mmc *mmc);
 688 #endif
 689
 690 /**
 691  * Start device initialization and return immediately; it does not block on
 692  * polling OCR (operation condition register) status.  Then you should call
 693  * mmc_init, which would block on polling OCR status and complete the device
 694  * initializatin.
 695  *
 696  * @param mmc   Pointer to a MMC device struct
 697  * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error.
 698  */
 699 int mmc_start_init(struct mmc *mmc);
 700
 701 /**
 702  * Set preinit flag of mmc device.
 703  *
 704  * This will cause the device to be pre-inited during mmc_initialize(),
 705  * which may save boot time if the device is not accessed until later.
 706  * Some eMMC devices take 200-300ms to init, but unfortunately they
 707  * must be sent a series of commands to even get them to start preparing
 708  * for operation.
 709  *
 710  * @param mmc           Pointer to a MMC device struct
 711  * @param preinit       preinit flag value
 712  */
 713 void mmc_set_preinit(struct mmc *mmc, int preinit);
 714
 715 #ifdef CONFIG_MMC_SPI
 716 #define mmc_host_is_spi(mmc)    ((mmc)->cfg->host_caps & MMC_MODE_SPI)
 717 #else
 718 #define mmc_host_is_spi(mmc)    0
 719 #endif
 720 struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
 721
 722 void board_mmc_power_init(void);
 723 int board_mmc_init(bd_t *bis);
 724 int cpu_mmc_init(bd_t *bis);
 725 int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
 726 int mmc_get_env_dev(void);
 727
 728 /* Set block count limit because of 16 bit register limit on some hardware*/
 729 #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
 730 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
 731 #endif
 732
 733 /**
 734  * mmc_get_blk_desc() - Get the block descriptor for an MMC device
 735  *
 736  * @mmc:        MMC device
 737  * @return block device if found, else NULL
 738  */
 739 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc);
 740
 741 #endif /* _MMC_H_ */