include/mmc.h

   1 /*
   2  * Copyright 2008,2010 Freescale Semiconductor, Inc
   3  * Andy Fleming
   4  *
   5  * Based (loosely) on the Linux code
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef _MMC_H_
  11 #define _MMC_H_
  12
  13 #include <linux/list.h>
  14 #include <linux/compiler.h>
  15 #include <part.h>
  16
  17 #define SD_VERSION_SD   0x20000
  18 #define SD_VERSION_3    (SD_VERSION_SD | 0x300)
  19 #define SD_VERSION_2    (SD_VERSION_SD | 0x200)
  20 #define SD_VERSION_1_0  (SD_VERSION_SD | 0x100)
  21 #define SD_VERSION_1_10 (SD_VERSION_SD | 0x10a)
  22 #define MMC_VERSION_MMC         0x10000
  23 #define MMC_VERSION_UNKNOWN     (MMC_VERSION_MMC)
  24 #define MMC_VERSION_1_2         (MMC_VERSION_MMC | 0x102)
  25 #define MMC_VERSION_1_4         (MMC_VERSION_MMC | 0x104)
  26 #define MMC_VERSION_2_2         (MMC_VERSION_MMC | 0x202)
  27 #define MMC_VERSION_3           (MMC_VERSION_MMC | 0x300)
  28 #define MMC_VERSION_4           (MMC_VERSION_MMC | 0x400)
  29 #define MMC_VERSION_4_1         (MMC_VERSION_MMC | 0x401)
  30 #define MMC_VERSION_4_2         (MMC_VERSION_MMC | 0x402)
  31 #define MMC_VERSION_4_3         (MMC_VERSION_MMC | 0x403)
  32 #define MMC_VERSION_4_41        (MMC_VERSION_MMC | 0x429)
  33 #define MMC_VERSION_4_5         (MMC_VERSION_MMC | 0x405)
  34
  35 #define MMC_MODE_HS             0x001
  36 #define MMC_MODE_HS_52MHz       0x010
  37 #define MMC_MODE_4BIT           0x100
  38 #define MMC_MODE_8BIT           0x200
  39 #define MMC_MODE_SPI            0x400
  40 #define MMC_MODE_HC             0x800
  41
  42 #define MMC_MODE_MASK_WIDTH_BITS (MMC_MODE_4BIT | MMC_MODE_8BIT)
  43 #define MMC_MODE_WIDTH_BITS_SHIFT 8
  44
  45 #define SD_DATA_4BIT    0x00040000
  46
  47 #define IS_SD(x) (x->version & SD_VERSION_SD)
  48
  49 #define MMC_DATA_READ           1
  50 #define MMC_DATA_WRITE          2
  51
  52 #define NO_CARD_ERR             -16 /* No SD/MMC card inserted */
  53 #define UNUSABLE_ERR            -17 /* Unusable Card */
  54 #define COMM_ERR                -18 /* Communications Error */
  55 #define TIMEOUT                 -19
  56 #define IN_PROGRESS             -20 /* operation is in progress */
  57 #define SWITCH_ERR              -21 /* Card reports failure to switch mode */
  58
  59 #define MMC_CMD_GO_IDLE_STATE           0
  60 #define MMC_CMD_SEND_OP_COND            1
  61 #define MMC_CMD_ALL_SEND_CID            2
  62 #define MMC_CMD_SET_RELATIVE_ADDR       3
  63 #define MMC_CMD_SET_DSR                 4
  64 #define MMC_CMD_SWITCH                  6
  65 #define MMC_CMD_SELECT_CARD             7
  66 #define MMC_CMD_SEND_EXT_CSD            8
  67 #define MMC_CMD_SEND_CSD                9
  68 #define MMC_CMD_SEND_CID                10
  69 #define MMC_CMD_STOP_TRANSMISSION       12
  70 #define MMC_CMD_SEND_STATUS             13
  71 #define MMC_CMD_SET_BLOCKLEN            16
  72 #define MMC_CMD_READ_SINGLE_BLOCK       17
  73 #define MMC_CMD_READ_MULTIPLE_BLOCK     18
  74 #define MMC_CMD_SET_BLOCK_COUNT         23
  75 #define MMC_CMD_WRITE_SINGLE_BLOCK      24
  76 #define MMC_CMD_WRITE_MULTIPLE_BLOCK    25
  77 #define MMC_CMD_ERASE_GROUP_START       35
  78 #define MMC_CMD_ERASE_GROUP_END         36
  79 #define MMC_CMD_ERASE                   38
  80 #define MMC_CMD_APP_CMD                 55
  81 #define MMC_CMD_SPI_READ_OCR            58
  82 #define MMC_CMD_SPI_CRC_ON_OFF          59
  83 #define MMC_CMD_RES_MAN                 62
  84
  85 #define MMC_CMD62_ARG1                  0xefac62ec
  86 #define MMC_CMD62_ARG2                  0xcbaea7
  87
  88
  89 #define SD_CMD_SEND_RELATIVE_ADDR       3
  90 #define SD_CMD_SWITCH_FUNC              6
  91 #define SD_CMD_SEND_IF_COND             8
  92
  93 #define SD_CMD_APP_SET_BUS_WIDTH        6
  94 #define SD_CMD_ERASE_WR_BLK_START       32
  95 #define SD_CMD_ERASE_WR_BLK_END         33
  96 #define SD_CMD_APP_SEND_OP_COND         41
  97 #define SD_CMD_APP_SEND_SCR             51
  98
  99 /* SCR definitions in different words */
 100 #define SD_HIGHSPEED_BUSY       0x00020000
 101 #define SD_HIGHSPEED_SUPPORTED  0x00020000
 102
 103 #define MMC_HS_TIMING           0x00000100
 104 #define MMC_HS_52MHZ            0x2
 105
 106 #define OCR_BUSY                0x80000000
 107 #define OCR_HCS                 0x40000000
 108 #define OCR_VOLTAGE_MASK        0x007FFF80
 109 #define OCR_ACCESS_MODE         0x60000000
 110
 111 #define SECURE_ERASE            0x80000000
 112
 113 #define MMC_STATUS_MASK         (~0x0206BF7F)
 114 #define MMC_STATUS_SWITCH_ERROR (1 << 7)
 115 #define MMC_STATUS_RDY_FOR_DATA (1 << 8)
 116 #define MMC_STATUS_CURR_STATE   (0xf << 9)
 117 #define MMC_STATUS_ERROR        (1 << 19)
 118
 119 #define MMC_STATE_PRG           (7 << 9)
 120
 121 #define MMC_VDD_165_195         0x00000080      /* VDD voltage 1.65 - 1.95 */
 122 #define MMC_VDD_20_21           0x00000100      /* VDD voltage 2.0 ~ 2.1 */
 123 #define MMC_VDD_21_22           0x00000200      /* VDD voltage 2.1 ~ 2.2 */
 124 #define MMC_VDD_22_23           0x00000400      /* VDD voltage 2.2 ~ 2.3 */
 125 #define MMC_VDD_23_24           0x00000800      /* VDD voltage 2.3 ~ 2.4 */
 126 #define MMC_VDD_24_25           0x00001000      /* VDD voltage 2.4 ~ 2.5 */
 127 #define MMC_VDD_25_26           0x00002000      /* VDD voltage 2.5 ~ 2.6 */
 128 #define MMC_VDD_26_27           0x00004000      /* VDD voltage 2.6 ~ 2.7 */
 129 #define MMC_VDD_27_28           0x00008000      /* VDD voltage 2.7 ~ 2.8 */
 130 #define MMC_VDD_28_29           0x00010000      /* VDD voltage 2.8 ~ 2.9 */
 131 #define MMC_VDD_29_30           0x00020000      /* VDD voltage 2.9 ~ 3.0 */
 132 #define MMC_VDD_30_31           0x00040000      /* VDD voltage 3.0 ~ 3.1 */
 133 #define MMC_VDD_31_32           0x00080000      /* VDD voltage 3.1 ~ 3.2 */
 134 #define MMC_VDD_32_33           0x00100000      /* VDD voltage 3.2 ~ 3.3 */
 135 #define MMC_VDD_33_34           0x00200000      /* VDD voltage 3.3 ~ 3.4 */
 136 #define MMC_VDD_34_35           0x00400000      /* VDD voltage 3.4 ~ 3.5 */
 137 #define MMC_VDD_35_36           0x00800000      /* VDD voltage 3.5 ~ 3.6 */
 138
 139 #define MMC_SWITCH_MODE_CMD_SET         0x00 /* Change the command set */
 140 #define MMC_SWITCH_MODE_SET_BITS        0x01 /* Set bits in EXT_CSD byte
 141                                                 addressed by index which are
 142                                                 1 in value field */
 143 #define MMC_SWITCH_MODE_CLEAR_BITS      0x02 /* Clear bits in EXT_CSD byte
 144                                                 addressed by index, which are
 145                                                 1 in value field */
 146 #define MMC_SWITCH_MODE_WRITE_BYTE      0x03 /* Set target byte to value */
 147
 148 #define SD_SWITCH_CHECK         0
 149 #define SD_SWITCH_SWITCH        1
 150
 151 /*
 152  * EXT_CSD fields
 153  */
 154 #define EXT_CSD_GP_SIZE_MULT            143     /* R/W */
 155 #define EXT_CSD_PARTITIONS_ATTRIBUTE    156     /* R/W */
 156 #define EXT_CSD_PARTITIONING_SUPPORT    160     /* RO */
 157 #define EXT_CSD_RST_N_FUNCTION          162     /* R/W */
 158 #define EXT_CSD_RPMB_MULT               168     /* RO */
 159 #define EXT_CSD_ERASE_GROUP_DEF         175     /* R/W */
 160 #define EXT_CSD_BOOT_BUS_WIDTH          177
 161 #define EXT_CSD_PART_CONF               179     /* R/W */
 162 #define EXT_CSD_BUS_WIDTH               183     /* R/W */
 163 #define EXT_CSD_HS_TIMING               185     /* R/W */
 164 #define EXT_CSD_REV                     192     /* RO */
 165 #define EXT_CSD_CARD_TYPE               196     /* RO */
 166 #define EXT_CSD_SEC_CNT                 212     /* RO, 4 bytes */
 167 #define EXT_CSD_HC_WP_GRP_SIZE          221     /* RO */
 168 #define EXT_CSD_HC_ERASE_GRP_SIZE       224     /* RO */
 169 #define EXT_CSD_BOOT_MULT               226     /* RO */
 170
 171 /*
 172  * EXT_CSD field definitions
 173  */
 174
 175 #define EXT_CSD_CMD_SET_NORMAL          (1 << 0)
 176 #define EXT_CSD_CMD_SET_SECURE          (1 << 1)
 177 #define EXT_CSD_CMD_SET_CPSECURE        (1 << 2)
 178
 179 #define EXT_CSD_CARD_TYPE_26    (1 << 0)        /* Card can run at 26MHz */
 180 #define EXT_CSD_CARD_TYPE_52    (1 << 1)        /* Card can run at 52MHz */
 181
 182 #define EXT_CSD_BUS_WIDTH_1     0       /* Card is in 1 bit mode */
 183 #define EXT_CSD_BUS_WIDTH_4     1       /* Card is in 4 bit mode */
 184 #define EXT_CSD_BUS_WIDTH_8     2       /* Card is in 8 bit mode */
 185
 186 #define EXT_CSD_BOOT_ACK_ENABLE                 (1 << 6)
 187 #define EXT_CSD_BOOT_PARTITION_ENABLE           (1 << 3)
 188 #define EXT_CSD_PARTITION_ACCESS_ENABLE         (1 << 0)
 189 #define EXT_CSD_PARTITION_ACCESS_DISABLE        (0 << 0)
 190
 191 #define EXT_CSD_BOOT_ACK(x)             (x << 6)
 192 #define EXT_CSD_BOOT_PART_NUM(x)        (x << 3)
 193 #define EXT_CSD_PARTITION_ACCESS(x)     (x << 0)
 194
 195 #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x)  (x << 3)
 196 #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
 197 #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
 198
 199 #define R1_ILLEGAL_COMMAND              (1 << 22)
 200 #define R1_APP_CMD                      (1 << 5)
 201
 202 #define MMC_RSP_PRESENT (1 << 0)
 203 #define MMC_RSP_136     (1 << 1)                /* 136 bit response */
 204 #define MMC_RSP_CRC     (1 << 2)                /* expect valid crc */
 205 #define MMC_RSP_BUSY    (1 << 3)                /* card may send busy */
 206 #define MMC_RSP_OPCODE  (1 << 4)                /* response contains opcode */
 207
 208 #define MMC_RSP_NONE    (0)
 209 #define MMC_RSP_R1      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 210 #define MMC_RSP_R1b     (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
 211                         MMC_RSP_BUSY)
 212 #define MMC_RSP_R2      (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
 213 #define MMC_RSP_R3      (MMC_RSP_PRESENT)
 214 #define MMC_RSP_R4      (MMC_RSP_PRESENT)
 215 #define MMC_RSP_R5      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 216 #define MMC_RSP_R6      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 217 #define MMC_RSP_R7      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 218
 219 #define MMCPART_NOAVAILABLE     (0xff)
 220 #define PART_ACCESS_MASK        (0x7)
 221 #define PART_SUPPORT            (0x1)
 222 #define PART_ENH_ATTRIB         (0x1f)
 223
 224 /* Maximum block size for MMC */
 225 #define MMC_MAX_BLOCK_LEN       512
 226
 227 /* The number of MMC physical partitions.  These consist of:
 228  * boot partitions (2), general purpose partitions (4) in MMC v4.4.
 229  */
 230 #define MMC_NUM_BOOT_PARTITION  2
 231 #define MMC_PART_RPMB           3       /* RPMB partition number */
 232
 233 struct mmc_cid {
 234         unsigned long psn;
 235         unsigned short oid;
 236         unsigned char mid;
 237         unsigned char prv;
 238         unsigned char mdt;
 239         char pnm[7];
 240 };
 241
 242 struct mmc_cmd {
 243         ushort cmdidx;
 244         uint resp_type;
 245         uint cmdarg;
 246         uint response[4];
 247 };
 248
 249 struct mmc_data {
 250         union {
 251                 char *dest;
 252                 const char *src; /* src buffers don't get written to */
 253         };
 254         uint flags;
 255         uint blocks;
 256         uint blocksize;
 257 };
 258
 259 /* forward decl. */
 260 struct mmc;
 261
 262 struct mmc_ops {
 263         int (*send_cmd)(struct mmc *mmc,
 264                         struct mmc_cmd *cmd, struct mmc_data *data);
 265         void (*set_ios)(struct mmc *mmc);
 266         int (*init)(struct mmc *mmc);
 267         int (*getcd)(struct mmc *mmc);
 268         int (*getwp)(struct mmc *mmc);
 269 };
 270
 271 struct mmc_config {
 272         const char *name;
 273         const struct mmc_ops *ops;
 274         uint host_caps;
 275         uint voltages;
 276         uint f_min;
 277         uint f_max;
 278         uint b_max;
 279         unsigned char part_type;
 280 };
 281
 282 /* TODO struct mmc should be in mmc_private but it's hard to fix right now */
 283 struct mmc {
 284         struct list_head link;
 285         const struct mmc_config *cfg;   /* provided configuration */
 286         uint version;
 287         void *priv;
 288         uint has_init;
 289         int high_capacity;
 290         uint bus_width;
 291         uint clock;
 292         uint card_caps;
 293         uint ocr;
 294         uint dsr;
 295         uint dsr_imp;
 296         uint scr[2];
 297         uint csd[4];
 298         uint cid[4];
 299         ushort rca;
 300         char part_config;
 301         char part_num;
 302         uint tran_speed;
 303         uint read_bl_len;
 304         uint write_bl_len;
 305         uint erase_grp_size;
 306         u64 capacity;
 307         u64 capacity_user;
 308         u64 capacity_boot;
 309         u64 capacity_rpmb;
 310         u64 capacity_gp[4];
 311         block_dev_desc_t block_dev;
 312         char op_cond_pending;   /* 1 if we are waiting on an op_cond command */
 313         char init_in_progress;  /* 1 if we have done mmc_start_init() */
 314         char preinit;           /* start init as early as possible */
 315         uint op_cond_response;  /* the response byte from the last op_cond */
 316 };
 317
 318 int mmc_register(struct mmc *mmc);
 319 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
 320 void mmc_destroy(struct mmc *mmc);
 321 int mmc_initialize(bd_t *bis);
 322 int mmc_init(struct mmc *mmc);
 323 int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
 324 void mmc_set_clock(struct mmc *mmc, uint clock);
 325 struct mmc *find_mmc_device(int dev_num);
 326 int mmc_set_dev(int dev_num);
 327 void print_mmc_devices(char separator);
 328 int get_mmc_num(void);
 329 int board_mmc_getcd(struct mmc *mmc);
 330 int mmc_switch_part(int dev_num, unsigned int part_num);
 331 int mmc_getcd(struct mmc *mmc);
 332 int mmc_getwp(struct mmc *mmc);
 333 int mmc_set_dsr(struct mmc *mmc, u16 val);
 334 /* Function to change the size of boot partition and rpmb partitions */
 335 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
 336                                         unsigned long rpmbsize);
 337 /* Function to modify the PARTITION_CONFIG field of EXT_CSD */
 338 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
 339 /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
 340 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
 341 /* Function to modify the RST_n_FUNCTION field of EXT_CSD */
 342 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
 343 /* Functions to read / write the RPMB partition */
 344 int mmc_rpmb_set_key(struct mmc *mmc, void *key);
 345 int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
 346 int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
 347                   unsigned short cnt, unsigned char *key);
 348 int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
 349                    unsigned short cnt, unsigned char *key);
 350 /**
 351  * Start device initialization and return immediately; it does not block on
 352  * polling OCR (operation condition register) status.  Then you should call
 353  * mmc_init, which would block on polling OCR status and complete the device
 354  * initializatin.
 355  *
 356  * @param mmc   Pointer to a MMC device struct
 357  * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error.
 358  */
 359 int mmc_start_init(struct mmc *mmc);
 360
 361 /**
 362  * Set preinit flag of mmc device.
 363  *
 364  * This will cause the device to be pre-inited during mmc_initialize(),
 365  * which may save boot time if the device is not accessed until later.
 366  * Some eMMC devices take 200-300ms to init, but unfortunately they
 367  * must be sent a series of commands to even get them to start preparing
 368  * for operation.
 369  *
 370  * @param mmc           Pointer to a MMC device struct
 371  * @param preinit       preinit flag value
 372  */
 373 void mmc_set_preinit(struct mmc *mmc, int preinit);
 374
 375 #ifdef CONFIG_GENERIC_MMC
 376 #ifdef CONFIG_MMC_SPI
 377 #define mmc_host_is_spi(mmc)    ((mmc)->cfg->host_caps & MMC_MODE_SPI)
 378 #else
 379 #define mmc_host_is_spi(mmc)    0
 380 #endif
 381 struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
 382 #else
 383 int mmc_legacy_init(int verbose);
 384 #endif
 385
 386 int board_mmc_init(bd_t *bis);
 387
 388 /* Set block count limit because of 16 bit register limit on some hardware*/
 389 #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
 390 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
 391 #endif
 392
 393 #endif /* _MMC_H_ */