include/mmc.h

   1 /*
   2  * Copyright 2008,2010 Freescale Semiconductor, Inc
   3  * Andy Fleming
   4  *
   5  * Based (loosely) on the Linux code
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef _MMC_H_
  11 #define _MMC_H_
  12
  13 #include <linux/list.h>
  14 #include <linux/sizes.h>
  15 #include <linux/compiler.h>
  16 #include <part.h>
  17
  18 /* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
  19 #define SD_VERSION_SD   (1U << 31)
  20 #define MMC_VERSION_MMC (1U << 30)
  21
  22 #define MAKE_SDMMC_VERSION(a, b, c)     \
  23         ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c))
  24 #define MAKE_SD_VERSION(a, b, c)        \
  25         (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
  26 #define MAKE_MMC_VERSION(a, b, c)       \
  27         (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))
  28
  29 #define EXTRACT_SDMMC_MAJOR_VERSION(x)  \
  30         (((u32)(x) >> 16) & 0xff)
  31 #define EXTRACT_SDMMC_MINOR_VERSION(x)  \
  32         (((u32)(x) >> 8) & 0xff)
  33 #define EXTRACT_SDMMC_CHANGE_VERSION(x) \
  34         ((u32)(x) & 0xff)
  35
  36 #define SD_VERSION_3            MAKE_SD_VERSION(3, 0, 0)
  37 #define SD_VERSION_2            MAKE_SD_VERSION(2, 0, 0)
  38 #define SD_VERSION_1_0          MAKE_SD_VERSION(1, 0, 0)
  39 #define SD_VERSION_1_10         MAKE_SD_VERSION(1, 10, 0)
  40
  41 #define MMC_VERSION_UNKNOWN     MAKE_MMC_VERSION(0, 0, 0)
  42 #define MMC_VERSION_1_2         MAKE_MMC_VERSION(1, 2, 0)
  43 #define MMC_VERSION_1_4         MAKE_MMC_VERSION(1, 4, 0)
  44 #define MMC_VERSION_2_2         MAKE_MMC_VERSION(2, 2, 0)
  45 #define MMC_VERSION_3           MAKE_MMC_VERSION(3, 0, 0)
  46 #define MMC_VERSION_4           MAKE_MMC_VERSION(4, 0, 0)
  47 #define MMC_VERSION_4_1         MAKE_MMC_VERSION(4, 1, 0)
  48 #define MMC_VERSION_4_2         MAKE_MMC_VERSION(4, 2, 0)
  49 #define MMC_VERSION_4_3         MAKE_MMC_VERSION(4, 3, 0)
  50 #define MMC_VERSION_4_41        MAKE_MMC_VERSION(4, 4, 1)
  51 #define MMC_VERSION_4_5         MAKE_MMC_VERSION(4, 5, 0)
  52 #define MMC_VERSION_5_0         MAKE_MMC_VERSION(5, 0, 0)
  53 #define MMC_VERSION_5_1         MAKE_MMC_VERSION(5, 1, 0)
  54
  55 #define MMC_CAP(mode)           (1 << mode)
  56 #define MMC_MODE_HS             (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS))
  57 #define MMC_MODE_HS_52MHz       MMC_CAP(MMC_HS_52)
  58 #define MMC_MODE_DDR_52MHz      MMC_CAP(MMC_DDR_52)
  59
  60 #define MMC_MODE_8BIT           BIT(30)
  61 #define MMC_MODE_4BIT           BIT(29)
  62 #define MMC_MODE_1BIT           BIT(28)
  63 #define MMC_MODE_SPI            BIT(27)
  64
  65
  66 #define SD_DATA_4BIT    0x00040000
  67
  68 #define IS_SD(x)        ((x)->version & SD_VERSION_SD)
  69 #define IS_MMC(x)       ((x)->version & MMC_VERSION_MMC)
  70
  71 #define MMC_DATA_READ           1
  72 #define MMC_DATA_WRITE          2
  73
  74 #define MMC_CMD_GO_IDLE_STATE           0
  75 #define MMC_CMD_SEND_OP_COND            1
  76 #define MMC_CMD_ALL_SEND_CID            2
  77 #define MMC_CMD_SET_RELATIVE_ADDR       3
  78 #define MMC_CMD_SET_DSR                 4
  79 #define MMC_CMD_SWITCH                  6
  80 #define MMC_CMD_SELECT_CARD             7
  81 #define MMC_CMD_SEND_EXT_CSD            8
  82 #define MMC_CMD_SEND_CSD                9
  83 #define MMC_CMD_SEND_CID                10
  84 #define MMC_CMD_STOP_TRANSMISSION       12
  85 #define MMC_CMD_SEND_STATUS             13
  86 #define MMC_CMD_SET_BLOCKLEN            16
  87 #define MMC_CMD_READ_SINGLE_BLOCK       17
  88 #define MMC_CMD_READ_MULTIPLE_BLOCK     18
  89 #define MMC_CMD_SET_BLOCK_COUNT         23
  90 #define MMC_CMD_WRITE_SINGLE_BLOCK      24
  91 #define MMC_CMD_WRITE_MULTIPLE_BLOCK    25
  92 #define MMC_CMD_ERASE_GROUP_START       35
  93 #define MMC_CMD_ERASE_GROUP_END         36
  94 #define MMC_CMD_ERASE                   38
  95 #define MMC_CMD_APP_CMD                 55
  96 #define MMC_CMD_SPI_READ_OCR            58
  97 #define MMC_CMD_SPI_CRC_ON_OFF          59
  98 #define MMC_CMD_RES_MAN                 62
  99
 100 #define MMC_CMD62_ARG1                  0xefac62ec
 101 #define MMC_CMD62_ARG2                  0xcbaea7
 102
 103
 104 #define SD_CMD_SEND_RELATIVE_ADDR       3
 105 #define SD_CMD_SWITCH_FUNC              6
 106 #define SD_CMD_SEND_IF_COND             8
 107 #define SD_CMD_SWITCH_UHS18V            11
 108
 109 #define SD_CMD_APP_SET_BUS_WIDTH        6
 110 #define SD_CMD_APP_SD_STATUS            13
 111 #define SD_CMD_ERASE_WR_BLK_START       32
 112 #define SD_CMD_ERASE_WR_BLK_END         33
 113 #define SD_CMD_APP_SEND_OP_COND         41
 114 #define SD_CMD_APP_SEND_SCR             51
 115
 116 /* SCR definitions in different words */
 117 #define SD_HIGHSPEED_BUSY       0x00020000
 118 #define SD_HIGHSPEED_SUPPORTED  0x00020000
 119
 120 #define OCR_BUSY                0x80000000
 121 #define OCR_HCS                 0x40000000
 122 #define OCR_VOLTAGE_MASK        0x007FFF80
 123 #define OCR_ACCESS_MODE         0x60000000
 124
 125 #define MMC_ERASE_ARG           0x00000000
 126 #define MMC_SECURE_ERASE_ARG    0x80000000
 127 #define MMC_TRIM_ARG            0x00000001
 128 #define MMC_DISCARD_ARG         0x00000003
 129 #define MMC_SECURE_TRIM1_ARG    0x80000001
 130 #define MMC_SECURE_TRIM2_ARG    0x80008000
 131
 132 #define MMC_STATUS_MASK         (~0x0206BF7F)
 133 #define MMC_STATUS_SWITCH_ERROR (1 << 7)
 134 #define MMC_STATUS_RDY_FOR_DATA (1 << 8)
 135 #define MMC_STATUS_CURR_STATE   (0xf << 9)
 136 #define MMC_STATUS_ERROR        (1 << 19)
 137
 138 #define MMC_STATE_PRG           (7 << 9)
 139
 140 #define MMC_VDD_165_195         0x00000080      /* VDD voltage 1.65 - 1.95 */
 141 #define MMC_VDD_20_21           0x00000100      /* VDD voltage 2.0 ~ 2.1 */
 142 #define MMC_VDD_21_22           0x00000200      /* VDD voltage 2.1 ~ 2.2 */
 143 #define MMC_VDD_22_23           0x00000400      /* VDD voltage 2.2 ~ 2.3 */
 144 #define MMC_VDD_23_24           0x00000800      /* VDD voltage 2.3 ~ 2.4 */
 145 #define MMC_VDD_24_25           0x00001000      /* VDD voltage 2.4 ~ 2.5 */
 146 #define MMC_VDD_25_26           0x00002000      /* VDD voltage 2.5 ~ 2.6 */
 147 #define MMC_VDD_26_27           0x00004000      /* VDD voltage 2.6 ~ 2.7 */
 148 #define MMC_VDD_27_28           0x00008000      /* VDD voltage 2.7 ~ 2.8 */
 149 #define MMC_VDD_28_29           0x00010000      /* VDD voltage 2.8 ~ 2.9 */
 150 #define MMC_VDD_29_30           0x00020000      /* VDD voltage 2.9 ~ 3.0 */
 151 #define MMC_VDD_30_31           0x00040000      /* VDD voltage 3.0 ~ 3.1 */
 152 #define MMC_VDD_31_32           0x00080000      /* VDD voltage 3.1 ~ 3.2 */
 153 #define MMC_VDD_32_33           0x00100000      /* VDD voltage 3.2 ~ 3.3 */
 154 #define MMC_VDD_33_34           0x00200000      /* VDD voltage 3.3 ~ 3.4 */
 155 #define MMC_VDD_34_35           0x00400000      /* VDD voltage 3.4 ~ 3.5 */
 156 #define MMC_VDD_35_36           0x00800000      /* VDD voltage 3.5 ~ 3.6 */
 157
 158 #define MMC_SWITCH_MODE_CMD_SET         0x00 /* Change the command set */
 159 #define MMC_SWITCH_MODE_SET_BITS        0x01 /* Set bits in EXT_CSD byte
 160                                                 addressed by index which are
 161                                                 1 in value field */
 162 #define MMC_SWITCH_MODE_CLEAR_BITS      0x02 /* Clear bits in EXT_CSD byte
 163                                                 addressed by index, which are
 164                                                 1 in value field */
 165 #define MMC_SWITCH_MODE_WRITE_BYTE      0x03 /* Set target byte to value */
 166
 167 #define SD_SWITCH_CHECK         0
 168 #define SD_SWITCH_SWITCH        1
 169
 170 /*
 171  * EXT_CSD fields
 172  */
 173 #define EXT_CSD_ENH_START_ADDR          136     /* R/W */
 174 #define EXT_CSD_ENH_SIZE_MULT           140     /* R/W */
 175 #define EXT_CSD_GP_SIZE_MULT            143     /* R/W */
 176 #define EXT_CSD_PARTITION_SETTING       155     /* R/W */
 177 #define EXT_CSD_PARTITIONS_ATTRIBUTE    156     /* R/W */
 178 #define EXT_CSD_MAX_ENH_SIZE_MULT       157     /* R */
 179 #define EXT_CSD_PARTITIONING_SUPPORT    160     /* RO */
 180 #define EXT_CSD_RST_N_FUNCTION          162     /* R/W */
 181 #define EXT_CSD_BKOPS_EN                163     /* R/W & R/W/E */
 182 #define EXT_CSD_WR_REL_PARAM            166     /* R */
 183 #define EXT_CSD_WR_REL_SET              167     /* R/W */
 184 #define EXT_CSD_RPMB_MULT               168     /* RO */
 185 #define EXT_CSD_ERASE_GROUP_DEF         175     /* R/W */
 186 #define EXT_CSD_BOOT_BUS_WIDTH          177
 187 #define EXT_CSD_PART_CONF               179     /* R/W */
 188 #define EXT_CSD_BUS_WIDTH               183     /* R/W */
 189 #define EXT_CSD_HS_TIMING               185     /* R/W */
 190 #define EXT_CSD_REV                     192     /* RO */
 191 #define EXT_CSD_CARD_TYPE               196     /* RO */
 192 #define EXT_CSD_SEC_CNT                 212     /* RO, 4 bytes */
 193 #define EXT_CSD_HC_WP_GRP_SIZE          221     /* RO */
 194 #define EXT_CSD_HC_ERASE_GRP_SIZE       224     /* RO */
 195 #define EXT_CSD_BOOT_MULT               226     /* RO */
 196 #define EXT_CSD_BKOPS_SUPPORT           502     /* RO */
 197
 198 /*
 199  * EXT_CSD field definitions
 200  */
 201
 202 #define EXT_CSD_CMD_SET_NORMAL          (1 << 0)
 203 #define EXT_CSD_CMD_SET_SECURE          (1 << 1)
 204 #define EXT_CSD_CMD_SET_CPSECURE        (1 << 2)
 205
 206 #define EXT_CSD_CARD_TYPE_26    (1 << 0)        /* Card can run at 26MHz */
 207 #define EXT_CSD_CARD_TYPE_52    (1 << 1)        /* Card can run at 52MHz */
 208 #define EXT_CSD_CARD_TYPE_DDR_1_8V      (1 << 2)
 209 #define EXT_CSD_CARD_TYPE_DDR_1_2V      (1 << 3)
 210 #define EXT_CSD_CARD_TYPE_DDR_52        (EXT_CSD_CARD_TYPE_DDR_1_8V \
 211                                         | EXT_CSD_CARD_TYPE_DDR_1_2V)
 212
 213 #define EXT_CSD_BUS_WIDTH_1     0       /* Card is in 1 bit mode */
 214 #define EXT_CSD_BUS_WIDTH_4     1       /* Card is in 4 bit mode */
 215 #define EXT_CSD_BUS_WIDTH_8     2       /* Card is in 8 bit mode */
 216 #define EXT_CSD_DDR_BUS_WIDTH_4 5       /* Card is in 4 bit DDR mode */
 217 #define EXT_CSD_DDR_BUS_WIDTH_8 6       /* Card is in 8 bit DDR mode */
 218
 219 #define EXT_CSD_BOOT_ACK_ENABLE                 (1 << 6)
 220 #define EXT_CSD_BOOT_PARTITION_ENABLE           (1 << 3)
 221 #define EXT_CSD_PARTITION_ACCESS_ENABLE         (1 << 0)
 222 #define EXT_CSD_PARTITION_ACCESS_DISABLE        (0 << 0)
 223
 224 #define EXT_CSD_BOOT_ACK(x)             (x << 6)
 225 #define EXT_CSD_BOOT_PART_NUM(x)        (x << 3)
 226 #define EXT_CSD_PARTITION_ACCESS(x)     (x << 0)
 227
 228 #define EXT_CSD_EXTRACT_BOOT_ACK(x)             (((x) >> 6) & 0x1)
 229 #define EXT_CSD_EXTRACT_BOOT_PART(x)            (((x) >> 3) & 0x7)
 230 #define EXT_CSD_EXTRACT_PARTITION_ACCESS(x)     ((x) & 0x7)
 231
 232 #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x)  (x << 3)
 233 #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
 234 #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
 235
 236 #define EXT_CSD_PARTITION_SETTING_COMPLETED     (1 << 0)
 237
 238 #define EXT_CSD_ENH_USR         (1 << 0)        /* user data area is enhanced */
 239 #define EXT_CSD_ENH_GP(x)       (1 << ((x)+1))  /* GP part (x+1) is enhanced */
 240
 241 #define EXT_CSD_HS_CTRL_REL     (1 << 0)        /* host controlled WR_REL_SET */
 242
 243 #define EXT_CSD_WR_DATA_REL_USR         (1 << 0)        /* user data area WR_REL */
 244 #define EXT_CSD_WR_DATA_REL_GP(x)       (1 << ((x)+1))  /* GP part (x+1) WR_REL */
 245
 246 #define R1_ILLEGAL_COMMAND              (1 << 22)
 247 #define R1_APP_CMD                      (1 << 5)
 248
 249 #define MMC_RSP_PRESENT (1 << 0)
 250 #define MMC_RSP_136     (1 << 1)                /* 136 bit response */
 251 #define MMC_RSP_CRC     (1 << 2)                /* expect valid crc */
 252 #define MMC_RSP_BUSY    (1 << 3)                /* card may send busy */
 253 #define MMC_RSP_OPCODE  (1 << 4)                /* response contains opcode */
 254
 255 #define MMC_RSP_NONE    (0)
 256 #define MMC_RSP_R1      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 257 #define MMC_RSP_R1b     (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
 258                         MMC_RSP_BUSY)
 259 #define MMC_RSP_R2      (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
 260 #define MMC_RSP_R3      (MMC_RSP_PRESENT)
 261 #define MMC_RSP_R4      (MMC_RSP_PRESENT)
 262 #define MMC_RSP_R5      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 263 #define MMC_RSP_R6      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 264 #define MMC_RSP_R7      (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
 265
 266 #define MMCPART_NOAVAILABLE     (0xff)
 267 #define PART_ACCESS_MASK        (0x7)
 268 #define PART_SUPPORT            (0x1)
 269 #define ENHNCD_SUPPORT          (0x2)
 270 #define PART_ENH_ATTRIB         (0x1f)
 271
 272 /* Maximum block size for MMC */
 273 #define MMC_MAX_BLOCK_LEN       512
 274
 275 /* The number of MMC physical partitions.  These consist of:
 276  * boot partitions (2), general purpose partitions (4) in MMC v4.4.
 277  */
 278 #define MMC_NUM_BOOT_PARTITION  2
 279 #define MMC_PART_RPMB           3       /* RPMB partition number */
 280
 281 /* Driver model support */
 282
 283 /**
 284  * struct mmc_uclass_priv - Holds information about a device used by the uclass
 285  */
 286 struct mmc_uclass_priv {
 287         struct mmc *mmc;
 288 };
 289
 290 /**
 291  * mmc_get_mmc_dev() - get the MMC struct pointer for a device
 292  *
 293  * Provided that the device is already probed and ready for use, this value
 294  * will be available.
 295  *
 296  * @dev:        Device
 297  * @return associated mmc struct pointer if available, else NULL
 298  */
 299 struct mmc *mmc_get_mmc_dev(struct udevice *dev);
 300
 301 /* End of driver model support */
 302
 303 struct mmc_cid {
 304         unsigned long psn;
 305         unsigned short oid;
 306         unsigned char mid;
 307         unsigned char prv;
 308         unsigned char mdt;
 309         char pnm[7];
 310 };
 311
 312 struct mmc_cmd {
 313         ushort cmdidx;
 314         uint resp_type;
 315         uint cmdarg;
 316         uint response[4];
 317 };
 318
 319 struct mmc_data {
 320         union {
 321                 char *dest;
 322                 const char *src; /* src buffers don't get written to */
 323         };
 324         uint flags;
 325         uint blocks;
 326         uint blocksize;
 327 };
 328
 329 /* forward decl. */
 330 struct mmc;
 331
 332 #if CONFIG_IS_ENABLED(DM_MMC)
 333 struct dm_mmc_ops {
 334         /**
 335          * send_cmd() - Send a command to the MMC device
 336          *
 337          * @dev:        Device to receive the command
 338          * @cmd:        Command to send
 339          * @data:       Additional data to send/receive
 340          * @return 0 if OK, -ve on error
 341          */
 342         int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd,
 343                         struct mmc_data *data);
 344
 345         /**
 346          * set_ios() - Set the I/O speed/width for an MMC device
 347          *
 348          * @dev:        Device to update
 349          * @return 0 if OK, -ve on error
 350          */
 351         int (*set_ios)(struct udevice *dev);
 352
 353         /**
 354          * get_cd() - See whether a card is present
 355          *
 356          * @dev:        Device to check
 357          * @return 0 if not present, 1 if present, -ve on error
 358          */
 359         int (*get_cd)(struct udevice *dev);
 360
 361         /**
 362          * get_wp() - See whether a card has write-protect enabled
 363          *
 364          * @dev:        Device to check
 365          * @return 0 if write-enabled, 1 if write-protected, -ve on error
 366          */
 367         int (*get_wp)(struct udevice *dev);
 368 };
 369
 370 #define mmc_get_ops(dev)        ((struct dm_mmc_ops *)(dev)->driver->ops)
 371
 372 int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 373                     struct mmc_data *data);
 374 int dm_mmc_set_ios(struct udevice *dev);
 375 int dm_mmc_get_cd(struct udevice *dev);
 376 int dm_mmc_get_wp(struct udevice *dev);
 377
 378 /* Transition functions for compatibility */
 379 int mmc_set_ios(struct mmc *mmc);
 380 int mmc_getcd(struct mmc *mmc);
 381 int mmc_getwp(struct mmc *mmc);
 382
 383 #else
 384 struct mmc_ops {
 385         int (*send_cmd)(struct mmc *mmc,
 386                         struct mmc_cmd *cmd, struct mmc_data *data);
 387         int (*set_ios)(struct mmc *mmc);
 388         int (*init)(struct mmc *mmc);
 389         int (*getcd)(struct mmc *mmc);
 390         int (*getwp)(struct mmc *mmc);
 391 };
 392 #endif
 393
 394 struct mmc_config {
 395         const char *name;
 396 #if !CONFIG_IS_ENABLED(DM_MMC)
 397         const struct mmc_ops *ops;
 398 #endif
 399         uint host_caps;
 400         uint voltages;
 401         uint f_min;
 402         uint f_max;
 403         uint b_max;
 404         unsigned char part_type;
 405 };
 406
 407 struct sd_ssr {
 408         unsigned int au;                /* In sectors */
 409         unsigned int erase_timeout;     /* In milliseconds */
 410         unsigned int erase_offset;      /* In milliseconds */
 411 };
 412
 413 enum bus_mode {
 414         MMC_LEGACY,
 415         SD_LEGACY,
 416         MMC_HS,
 417         SD_HS,
 418         UHS_SDR12,
 419         UHS_SDR25,
 420         UHS_SDR50,
 421         UHS_SDR104,
 422         UHS_DDR50,
 423         MMC_HS_52,
 424         MMC_DDR_52,
 425         MMC_HS_200,
 426         MMC_MODES_END
 427 };
 428
 429 const char *mmc_mode_name(enum bus_mode mode);
 430 void mmc_dump_capabilities(const char *text, uint caps);
 431
 432 /*
 433  * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device
 434  * with mmc_get_mmc_dev().
 435  *
 436  * TODO struct mmc should be in mmc_private but it's hard to fix right now
 437  */
 438 struct mmc {
 439 #if !CONFIG_IS_ENABLED(BLK)
 440         struct list_head link;
 441 #endif
 442         const struct mmc_config *cfg;   /* provided configuration */
 443         uint version;
 444         void *priv;
 445         uint has_init;
 446         int high_capacity;
 447         uint bus_width;
 448         uint clock;
 449         uint card_caps;
 450         uint ocr;
 451         uint dsr;
 452         uint dsr_imp;
 453         uint scr[2];
 454         uint csd[4];
 455         uint cid[4];
 456         ushort rca;
 457         u8 part_support;
 458         u8 part_attr;
 459         u8 wr_rel_set;
 460         u8 part_config;
 461         uint tran_speed;
 462         uint legacy_speed; /* speed for the legacy mode provided by the card */
 463         uint read_bl_len;
 464         uint write_bl_len;
 465         uint erase_grp_size;    /* in 512-byte sectors */
 466         uint hc_wp_grp_size;    /* in 512-byte sectors */
 467         struct sd_ssr   ssr;    /* SD status register */
 468         u64 capacity;
 469         u64 capacity_user;
 470         u64 capacity_boot;
 471         u64 capacity_rpmb;
 472         u64 capacity_gp[4];
 473         u64 enh_user_start;
 474         u64 enh_user_size;
 475 #if !CONFIG_IS_ENABLED(BLK)
 476         struct blk_desc block_dev;
 477 #endif
 478         char op_cond_pending;   /* 1 if we are waiting on an op_cond command */
 479         char init_in_progress;  /* 1 if we have done mmc_start_init() */
 480         char preinit;           /* start init as early as possible */
 481         int ddr_mode;
 482 #if CONFIG_IS_ENABLED(DM_MMC)
 483         struct udevice *dev;    /* Device for this MMC controller */
 484 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 485         struct udevice *vmmc_supply;    /* Main voltage regulator (Vcc)*/
 486         struct udevice *vqmmc_supply;   /* IO voltage regulator (Vccq)*/
 487 #endif
 488 #endif
 489         u8 *ext_csd;
 490         enum bus_mode selected_mode;
 491 };
 492
 493 struct mmc_hwpart_conf {
 494         struct {
 495                 uint enh_start; /* in 512-byte sectors */
 496                 uint enh_size;  /* in 512-byte sectors, if 0 no enh area */
 497                 unsigned wr_rel_change : 1;
 498                 unsigned wr_rel_set : 1;
 499         } user;
 500         struct {
 501                 uint size;      /* in 512-byte sectors */
 502                 unsigned enhanced : 1;
 503                 unsigned wr_rel_change : 1;
 504                 unsigned wr_rel_set : 1;
 505         } gp_part[4];
 506 };
 507
 508 enum mmc_hwpart_conf_mode {
 509         MMC_HWPART_CONF_CHECK,
 510         MMC_HWPART_CONF_SET,
 511         MMC_HWPART_CONF_COMPLETE,
 512 };
 513
 514 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
 515
 516 /**
 517  * mmc_bind() - Set up a new MMC device ready for probing
 518  *
 519  * A child block device is bound with the IF_TYPE_MMC interface type. This
 520  * allows the device to be used with CONFIG_BLK
 521  *
 522  * @dev:        MMC device to set up
 523  * @mmc:        MMC struct
 524  * @cfg:        MMC configuration
 525  * @return 0 if OK, -ve on error
 526  */
 527 int mmc_bind(struct udevice *dev, struct mmc *mmc,
 528              const struct mmc_config *cfg);
 529 void mmc_destroy(struct mmc *mmc);
 530
 531 /**
 532  * mmc_unbind() - Unbind a MMC device's child block device
 533  *
 534  * @dev:        MMC device
 535  * @return 0 if OK, -ve on error
 536  */
 537 int mmc_unbind(struct udevice *dev);
 538 int mmc_initialize(bd_t *bis);
 539 int mmc_init(struct mmc *mmc);
 540 int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
 541 void mmc_set_clock(struct mmc *mmc, uint clock);
 542 struct mmc *find_mmc_device(int dev_num);
 543 int mmc_set_dev(int dev_num);
 544 void print_mmc_devices(char separator);
 545
 546 /**
 547  * get_mmc_num() - get the total MMC device number
 548  *
 549  * @return 0 if there is no MMC device, else the number of devices
 550  */
 551 int get_mmc_num(void);
 552 int mmc_switch_part(struct mmc *mmc, unsigned int part_num);
 553 int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
 554                       enum mmc_hwpart_conf_mode mode);
 555
 556 #if !CONFIG_IS_ENABLED(DM_MMC)
 557 int mmc_getcd(struct mmc *mmc);
 558 int board_mmc_getcd(struct mmc *mmc);
 559 int mmc_getwp(struct mmc *mmc);
 560 int board_mmc_getwp(struct mmc *mmc);
 561 #endif
 562
 563 int mmc_set_dsr(struct mmc *mmc, u16 val);
 564 /* Function to change the size of boot partition and rpmb partitions */
 565 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
 566                                         unsigned long rpmbsize);
 567 /* Function to modify the PARTITION_CONFIG field of EXT_CSD */
 568 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
 569 /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
 570 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
 571 /* Function to modify the RST_n_FUNCTION field of EXT_CSD */
 572 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
 573 /* Functions to read / write the RPMB partition */
 574 int mmc_rpmb_set_key(struct mmc *mmc, void *key);
 575 int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
 576 int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
 577                   unsigned short cnt, unsigned char *key);
 578 int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
 579                    unsigned short cnt, unsigned char *key);
 580 #ifdef CONFIG_CMD_BKOPS_ENABLE
 581 int mmc_set_bkops_enable(struct mmc *mmc);
 582 #endif
 583
 584 /**
 585  * Start device initialization and return immediately; it does not block on
 586  * polling OCR (operation condition register) status.  Then you should call
 587  * mmc_init, which would block on polling OCR status and complete the device
 588  * initializatin.
 589  *
 590  * @param mmc   Pointer to a MMC device struct
 591  * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error.
 592  */
 593 int mmc_start_init(struct mmc *mmc);
 594
 595 /**
 596  * Set preinit flag of mmc device.
 597  *
 598  * This will cause the device to be pre-inited during mmc_initialize(),
 599  * which may save boot time if the device is not accessed until later.
 600  * Some eMMC devices take 200-300ms to init, but unfortunately they
 601  * must be sent a series of commands to even get them to start preparing
 602  * for operation.
 603  *
 604  * @param mmc           Pointer to a MMC device struct
 605  * @param preinit       preinit flag value
 606  */
 607 void mmc_set_preinit(struct mmc *mmc, int preinit);
 608
 609 #ifdef CONFIG_MMC_SPI
 610 #define mmc_host_is_spi(mmc)    ((mmc)->cfg->host_caps & MMC_MODE_SPI)
 611 #else
 612 #define mmc_host_is_spi(mmc)    0
 613 #endif
 614 struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
 615
 616 void board_mmc_power_init(void);
 617 int board_mmc_init(bd_t *bis);
 618 int cpu_mmc_init(bd_t *bis);
 619 int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
 620 int mmc_get_env_dev(void);
 621
 622 /* Set block count limit because of 16 bit register limit on some hardware*/
 623 #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
 624 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
 625 #endif
 626
 627 /**
 628  * mmc_get_blk_desc() - Get the block descriptor for an MMC device
 629  *
 630  * @mmc:        MMC device
 631  * @return block device if found, else NULL
 632  */
 633 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc);
 634
 635 #endif /* _MMC_H_ */